Commit Graph

1441 Commits

Author SHA1 Message Date
whitequark 4b6e764c46 cxxrtl: do not use `->template` for non-dependent names.
This breaks build on MSVC but not GCC/Clang.
2021-01-26 18:09:53 +00:00
Iris Johnson c8415884d1 Improves the previous commit with a more complete coverage of the cases 2021-01-15 13:59:20 -06:00
Iris Johnson 86607d0fdc Handle sliced bits as clock inputs (fixes #2542) 2021-01-14 16:36:21 -06:00
Pepijn de Vos e789a00557 add buffer option to spice backend 2021-01-13 17:24:28 +01:00
whitequark f14074d2c2 cxxrtl: don't crash generating debug information for unused wires. 2020-12-22 06:51:38 +00:00
whitequark 7378194169 cxxrtl: split processes into sync and case nodes.
Similar to the treatment of black boxes, splitting processes into two
scheduling nodes adds sufficient freedom so that netlists with
well-behaved processes (e.g. those emitted by nMigen) can immediately
converge.

Because processes are not emitted into edge-triggered regions, this
approach has comparable performance to -O5 (without -noproc), which
is substantially slower than -O6.
2020-12-22 03:48:09 +00:00
whitequark b2221c1077 cxxrtl: completely rewrite netlist layout code.
The exact shape of C++ code emitted by CXXRTL has a critical effect
on performance, both compile-time and runtime. CXXRTL's performance
greatly improved when it started localizing and inlining wires, not
only because this assists the optimizer and register allocator, but
also because inlining code into edge-triggered regions cuts the time
spent in eval() by at least a factor of two.

However, the logic of netlist layout has always been ad-hoc, fragile,
and very hard to understand and modify. After commit ece25a45, which
introduced outlining, the same logic started being applied to two
distinct netlists at once instead of one, which barely worked.

This commit does four major changes:
  * There is now a single unambiguous source of truth (per subgraph)
    for the layout of any emitted wire.
  * Netlist layout is now done entirely during analysis using well
    known graph algorithms; no graph operations happen when emitting.
  * Netlist layout now happens completely separately for eval() and
    debug_eval() subgraphs.
  * Unreachable (within subgraph scope) netlist nodes are now neither
    emitted nor considered for wire inlining decisions.
The netlist layout code should also now closely match the described
semantics.

As a part of this large cleanup, it includes many miscellaneous
improvements:
  * The "bare minimum" debug level introduced in commit dd6a761d was
    split into two levels; -g1 now emits debug information *only* for
    inputs and state wires, and -g2 now emits debug information for
    all public members. The old behavior matches -g2. This is done
    to avoid bloat on low optimization levels.
  * Debug aliases and inlined connections are now handled separately,
    and complex RHS never interferes with inlined connections.
  * Aliases to outlined wires now carry a pointer to the outline.
  * Cell sync outputs can now be emitted in debug_eval().
  * Black box debug information now includes comb/sync driver flags.
  * The comment emitted for inlined cells is now accurate.
  * Debug information statistics now has less noise.
  * Netlist layout code is now much better documented.

Due to more precise inlining decisions, unmodified (i.e. with no
Yosys script being used) netlists now have much more logic inlined
into edge-triggered regions. On Minerva SoC SRAM, this improves
runtime by 20-25% across compilers and optimization levels.

Due to more precise reachability analysis, much less C++ code is now
emitted, especially at the maximum debug level. On Minerva SoC SRAM,
this improves clang compile time by 30-50% depending on options.
gcc is not affected.
2020-12-22 03:48:09 +00:00
whitequark e825cf9d73 cxxrtl: simplify logic choosing wire type. NFCI. 2020-12-21 07:24:52 +00:00
whitequark 6f42b26cea cxxrtl: clarify node use-def construction. NFCI. 2020-12-21 07:24:52 +00:00
whitequark 406f866659 cxxrtl: fix typo. 2020-12-21 07:24:52 +00:00
whitequark b9721bedf0 cxxrtl: speed up bit repeats (sign extends, etc).
On Minerva SoC SRAM, depending on the compiler, this change improves
overall time by 4-7%.
2020-12-21 02:20:34 +00:00
whitequark 40ca9d038b cxxrtl: speed up commits on clang.
On Minerva SoC SRAM compiled with clang-11, this change cuts commit
time in half (!) and overall time by 20%. When compiled with gcc-10,
there is no difference.
2020-12-21 02:20:30 +00:00
whitequark 3d3ea5099d cxxrtl: use `static inline` instead of `inline` in the C API.
In C, non-static inline functions require an implementation elsewhere
(even though the body is right there in the header). It is basically
never desirable to use those as opposed to static inline ones.
2020-12-20 14:48:16 +00:00
whitequark d889a3df35 cxxrtl: print names of cells inlined in connections. 2020-12-15 11:02:38 +00:00
whitequark f75bc6c7aa cxxrtl: disable optimization of debug_items().
Implementing outlining has greatly increased the amount of debug
information in a typical build, and consequently exposed performance
issues in C++ compilers, which are similar for both GCC and Clang;
the compile time of Minerva SoC SRAM increased almost twofold.

Although one would expect the slowdown to be caused by the increased
use of templates in `debug_eval()`, it is actually almost entirely
attributable to optimizations and codegen for `debug_items()`.

Fortunately, it is neither possible nor desirable to optimize
`debug_items()`: in most cases it is called exactly once, and its
body is a linear sequence of calls with unique arguments.

This commit turns off optimizations for `debug_items()` on GCC and
Clang, improving -Os compile time of Minerva SoC SRAM by ~40% (!)
2020-12-15 11:02:38 +00:00
whitequark 4d40595d64 cxxrtl: make alias analysis outlining-aware.
Before this commit, if a sequence of wires assigned in a chain would
terminate on a cell, none of the wires would get marked as aliases,
and typically all of the public wires would get outlined. The reason
for this behavior is that alias analysis predates outlining and in
fact runs before it.

After this commit, alias analysis runs after outlining and considers
outlined wires valid aliasees. More importantly, if the chained wires
contain any valid aliasees, then all of the wires are aliased to
the one that is topologically deepest.

Aliased wires incur virtually no overhead for the VCD writer, unlike
outlined wires that would otherwise take their place. On Minerva SoC
SRAM, size of the full VCD dump is reduced by ~65%, and throughput
is increased by ~55%.
2020-12-15 11:02:38 +00:00
whitequark dd6a761db0 cxxrtl: add a "bare minimum" debug information level.
Useful to reduce overhead when no debug capabilities are necessary
except for access to design state.
2020-12-14 01:27:56 +00:00
whitequark ece25a45d4 cxxrtl: implement debug information outlining.
Aggressive wire localization and inlining is necessary for CXXRTL to
achieve high performance. However, that comes with a cost: reduced
debug information coverage. Previously, as a workaround, the `-Og`
option could have been used to guarantee complete coverage, at a cost
of a significant performance penalty.

This commit introduces debug information outlining. The main eval()
function is compiled with the user-specified optimization settings.
In tandem, an auxiliary debug_eval() function, compiled from the same
netlist, can be used to reconstruct the values of localized/inlined
signals on demand. To the extent that it is possible, debug_eval()
reuses the results of computations performed by eval(), only filling
in the missing values.

Benchmarking a representative design (Minerva SoC SRAM) shows that:
  * Switching from `-O4`/`-Og` to `-O6` reduces runtime by ~40%.
  * Switching from `-g1` to `-g2`, both used with `-O6`, increases
    compile time by ~25%.
  * Although `-g2` increases the resident size of generated modules,
    this has no effect on runtime.

Because the impact of `-g2` is minimal and the benefits of having
unconditional 100% debug information coverage (and the performance
improvement as well) are major, this commit removes `-Og` and changes
the defaults to `-O6 -g2`.

We'll have our cake and eat it too!
2020-12-14 01:27:27 +00:00
whitequark 3b5a1314cd cxxrtl: rename "elision" to "inlining". NFC.
"Elision" in this context is an unusual and not very descriptive term
whereas "inlining" is common and straightforward. Also, introducing
"inlining" makes it easier to introduce its dual under the obvious
name "outlining".
2020-12-13 15:34:00 +00:00
whitequark 57759c3d1f cxxrtl: fix outdated comment. NFC. 2020-12-13 15:33:58 +00:00
whitequark ac1a78923a cxxrtl: use IdString::isPublic(). NFC. 2020-12-13 15:33:55 +00:00
whitequark e4aa8bc96b cxxrtl: don't overwrite buffered inputs.
Before this commit, a cell's input was always assigned like:

    p_cell.p_input = (value...);

If `p_input` is buffered (e.g. if the design is built at -O0), this
is not correct. (In practice, this breaks clocking.) Unfortunately,
the incorrect design was compiled without diagnostics because wire<>
was move-assignable and also implicitly constructible from value<>.

After this commit, cell inputs are no longer incorrectly assumed to
always be unbuffered, and wires are not assignable from values.
2020-12-11 23:32:06 +00:00
whitequark e89f6ae819 cxxrtl: allow customizing the root module path in the C API. 2020-12-03 01:58:02 +00:00
whitequark 3e13cfe53d
Merge pull request #2468 from whitequark/cxxrtl-assert
cxxrtl: use CXXRTL_ASSERT for RTL contract violations instead of assert
2020-12-02 23:36:22 +00:00
whitequark 3cb109f54b
Merge pull request #2469 from whitequark/cxxrtl-no-clk
cxxrtl: fix crashes caused by a floating or constant clock input
2020-12-02 23:36:03 +00:00
whitequark 7067f0d788 cxxrtl: fix crashes caused by a floating or constant clock input.
E.g. in:

    module test;
        wire clk = 0;
        reg data;
        always @(posedge clk)
            data <= 0;
    endmodule
2020-12-02 21:43:25 +00:00
whitequark aa0a15a42c cxxrtl: use CXXRTL_ASSERT for RTL contract violations instead of assert.
RTL contract violations and C++ contract violations are different:
the former depend on the netlist and will never violate memory safety
whereas the latter may. When loading a CXXRTL simulation into another
process, RTL contract violations should generally not crash it, while
C++ contract violations should.
2020-12-02 19:41:00 +00:00
whitequark 5beab5bc17 cxxrtl: provide a way to perform unobtrusive power-on reset.
Although it is always possible to destroy and recreate the design to
simulate a power-on reset, this has two drawbacks:
  * Black boxes are also destroyed and recreated, which causes them
    to reacquire their resources, which might be costly and/or erase
    important state.
  * Pointers into the design are invalidated and have to be acquired
    again, which is costly and might be very inconvenient if they are
    captured elsewhere (especially through the C API).
2020-12-02 08:25:27 +00:00
Miodrag Milanovic 7b093dca10 Add verilog backend option for simple_lhs 2020-11-25 18:21:41 +01:00
Miodrag Milanovic addc493e8d generate only simple assignments in verilog backend 2020-11-25 17:43:28 +01:00
Miodrag Milanović b8d3f13307
Merge pull request #2295 from epfl-vlsc/firrtl_blackbox_generic_parameters
Add firrtl backend support for generic parameters in blackbox components
2020-11-24 07:50:17 +01:00
Sahand Kashani 930a6ae7db Formatting fixes 2020-11-23 10:55:09 +01:00
William Woodruff c7cf9415f8
backends/blif: Remove unused vector of strings (#2420)
* backends/blif: Remove unused vector of strings

For reasons that are unclear to me, this was being used to store every
result of `cstr` before returning them. The vector was never accessed otherwise,
resulting in a huge unnecessary memory sink when emitting to BLIF.

* backends/blif: Remove CSTR macro

* backends/blif: Actually call str()
2020-11-16 09:31:48 +01:00
whitequark 65083e9520 cxxrtl: run `hierarchy -auto-top` if no top module is present.
In most cases, a CXXRTL simulation would use a top module, either
because this module serves as an entry point to the CXXRTL C API,
or because the outputs of a top module are unbuffered, improving
performance. Taking this into account, the CXXRTL backend now runs
`hierarchy -auto-top` if there is no top module. For the few cases
where this behavior is unwanted, it now accepts a `-nohierarchy`
option.

Fixes #2373.
2020-11-02 19:18:56 +00:00
whitequark 2ba05f5c31 cxxrtl: don't assert on non-constant $meminit inputs.
Fixes #2129.
2020-11-01 15:57:20 +00:00
whitequark cdf4ce9871 cxxrtl: don't assert on wires with multiple drivers.
Fixes #2374.
2020-11-01 12:49:30 +00:00
Marcelina Kościelnicka 2d340cd355 btor: Use Mem helper. 2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka f272c8b407 smt2: Use Mem helper. 2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka ec483b7c3b verilog_backend: Use Mem helper. 2020-10-21 17:51:20 +02:00
Jakob Wenzel 54166ae0c5 smtbmc: escape identifiers in verilog testbench 2020-10-06 11:27:14 +02:00
N. Engelhardt 8f1d53e66f write_verilog: emit intermediate wire for constant values in sensitivity list 2020-09-28 18:11:18 +02:00
N. Engelhardt ed5790382a
Merge pull request #2372 from nakengelhardt/name_is_public
add IdString::isPublic()
2020-09-21 15:18:06 +02:00
N. Engelhardt 3238190797 use the new isPublic() in a few places 2020-09-14 12:43:18 +02:00
Miodrag Milanović da3002e580
Merge pull request #2369 from Xiretza/gitignores
Add missing gitignores for test artifacts
2020-09-10 13:37:49 +02:00
whitequark 691418e13a cxxrtl: expose driver kind in debug information.
This can be useful to determine whether the wire should be a part of
a design checkpoint, whether it can be used to override design state,
and whether driving it may cause a conflict.
2020-09-02 18:00:12 +00:00
whitequark c7b2f07edf cxxrtl: improve handling of FFs with async inputs (other than CLK).
Before this commit, the meaning of "sync def" included some flip-flop
cells but not others. There was no actual reason for this; it was
just poorly defined.

After this commit, a "sync def" means that a wire holds design state
because it is connected directly to a flip-flop output, and may never
be unbuffered. This is not affected by presence of async inputs.
2020-09-02 18:00:12 +00:00
whitequark b025ee0aa6 cxxrtl: expose port direction in debug information.
This can be useful to distinguish e.g. a combinatorially driven wire
with type `CXXRTL_VALUE` from a module input with the same type, as
well as general introspection.
2020-09-02 17:19:11 +00:00
whitequark 8d6e5c6391 cxxrtl: fix typo in comment. NFC. 2020-09-02 15:23:49 +00:00
whitequark d880f6eda2 cxxrtl: fix inaccuracy in CXXRTL_ALIAS documentation. NFC.
Nodes driven by a constant value have type CXXRTL_VALUE and their
`next` pointer set to NULL. (This is already documented.)
2020-09-02 15:23:47 +00:00
Xiretza 6224fd9055
Add missing gitignores for test artifacts 2020-08-31 19:43:51 +02:00
whitequark c1fff52477
write_smt2: fix SMT-LIB tutorial URL 2020-08-29 20:02:35 +00:00
whitequark 00e7dec7f5 Replace "ILANG" with "RTLIL" everywhere.
The only difference between "RTLIL" and "ILANG" is that the latter is
the text representation of the former, as opposed to the in-memory
graph representation. This distinction serves no purpose but confuses
people: it is not obvious that the ILANG backend writes RTLIL graphs.

Passes `write_ilang` and `read_ilang` are provided as aliases to
`write_rtlil` and `read_rtlil` for compatibility.
2020-08-26 17:29:32 +00:00
Noah Moroze 91682d189e Ensure smt2 comments are associated with accessors 2020-08-20 16:00:05 -04:00
Xiretza 928fd40c2e Respect \A_SIGNED for $shift
This reflects the behaviour of $shr/$shl, which sign-extend their A
operands to the size of their output, then do a logical shift (shift in
0-bits).
2020-08-18 19:36:24 +02:00
Andy Knowles 5829d16fcd
cxxrtl.h: Fix incorrect CarryOut in alu() 2020-08-12 21:04:34 +02:00
Andy Knowles 1227c3681b cxxrtl.h: Fix incorrect CarryOut in alu when Bits % 32 != 0 && Invert == False 2020-08-12 11:32:57 +02:00
Sahand Kashani 5157f5623e Add support for real-valued parameters + preserve type of parameters
This commit adds support for real-valued parameters in blackboxes. Additionally,
parameters now retain their types are no longer all encoded as strings.

There is a caveat with this implementation due to my limited knowledge of yosys,
more specifically to how yosys encodes bitwidths of parameter values. The example
below can motivate the implementation choice I took. Suppose a verilog component
is declared with the following parameters:

            parameter signed [26:0] test_signed;
            parameter        [26:0] test_unsigned;
            parameter signed [40:0] test_signed_large;

If you instantiate it as follows:

            defparam <inst_name> .test_signed = 49;
            defparam <inst_name> .test_unsigned = 40'd35;
            defparam <inst_name> .test_signed_large = 40'd12;

If you peek in the RTLIL::Const structure corresponding to these params, you
realize that parameter "test_signed" is being considered as a 32-bit value
since it's declared as "49" without a width specifier, even though the parameter
is defined to have a maximum width of 27 bits.

A similar issue occurs for parameter "test_unsigned" where it is supposed to take
a maximum bit width of 27 bits, but if the user supplies a 40-bit value as above,
then yosys considers the value to be 40 bits.

I suppose this is due to the type being defined by the RHS rather than the definition.
Regardless of this, I emit the same widths as what the user specifies on the RHS when
generating firrtl IR.
2020-08-06 00:49:55 +02:00
Marcelina Kościelnicka 8fd43515c5 verilog_backend: Add handling for all FF types. 2020-07-30 18:22:36 +02:00
Sahand Kashani 2c6cc27af1 Add firrtl backend support for generic parameters in blackbox components
Previous blackbox components were just emitted with their interface ports,
but their generic parameters were never emitted and it was therefore
impossible to customize them.

This commit adds support for blackbox generic parameters, though support
is only provided for INTEGER and STRING parameters. Other types of
parameters such as DOUBLEs, ..., would result in undefined behavior here.

This allows the emission of custom extmodule instances such as the following:

extmodule fourteennm_lcell_comb_<instName>:
  input cin: UInt<1>
  output combout: UInt<1>
  output cout: UInt<1>
  input dataa: UInt<1>
  input datab: UInt<1>
  input datac: UInt<1>
  input datad: UInt<1>
  input datae: UInt<1>
  input dataf: UInt<1>
  input datag: UInt<1>
  input datah: UInt<1>
  input sharein: UInt<1>
  output shareout: UInt<1>
  output sumout: UInt<1>
  defname = fourteennm_lcell_comb
  parameter extended_lut = "off"
  parameter lut_mask = "b0001001000010010000100100001001000010010000100100001001000010010"
  parameter shared_arith = "off"
2020-07-23 15:20:45 +02:00
Alberto Gonzalez 42fb75c570
smtio: Emit `mode: start` options before `set-logic` command and any other options after it.
Refer to the SMT-LIB specification, section 4.1.7.  According to the spec, some options can only be specified in `start` mode.  Once the solver sees `set-logic`, it moves to `assert` mode.
2020-07-20 22:09:44 +00:00
Alberto Gonzalez 654864658f
smtio: Add support for parsing `yosys-smt2-solver-option` info statements. 2020-07-20 21:54:56 +00:00
Alberto Gonzalez f037985337
smt2: Add `-solver-option` option. 2020-07-20 21:54:56 +00:00
Claire Wolf a207cb362c Only allow "sat" and "unsat" smt solver responses in yosys-smtbmc
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-07-20 19:35:32 +02:00
clairexen f3d7e9a1df
Merge pull request #2273 from whitequark/write-verilog-always-star-initial
verilog_backend: in non-SV mode, add a trigger for `always @*`
2020-07-16 18:30:50 +02:00
clairexen c49344b262
Merge pull request #2272 from whitequark/write-verilog-sv
verilog_backend: add `-sv` option, make `-o <filename>.sv` work
2020-07-16 18:28:24 +02:00
whitequark 128522f173 verilog_backend: in non-SV mode, add a trigger for `always @*`.
This commit only affects translation of RTLIL processes (for which
there is limited support).

Due to the event-driven nature of Verilog, processes like

    reg x;
    always @*
        x <= 1;

may never execute. This can be fixed in SystemVerilog code by using
`always_comb` instead of `always @*`, but in Verilog-2001 the options
are limited. This commit implements the following workaround:

    reg init = 0;
    reg x;
    always @* begin
        if (init) begin end
        x <= 1;
    end

Fixes #2271.
2020-07-16 11:30:14 +00:00
whitequark d9f680b236 verilog_backend: add `-sv` option, make `-o <filename>.sv` work.
See #2271.
2020-07-16 10:44:08 +00:00
whitequark a5cf000377 cxxrtl: fix typo. NFC. 2020-07-14 16:10:30 +00:00
whitequark 5349a922e4 cxxrtl: expose eval() and commit() via the C API. 2020-07-12 23:34:18 +00:00
whitequark ab59e33b2b cxxrtl: add missing extern "C".
This bug was hidden if a header was generated.
2020-07-09 17:52:52 +00:00
whitequark a746c4b605 cxxrtl: update help text. 2020-06-26 08:30:44 +00:00
clairexen c7d71f436d
Merge pull request #2168 from whitequark/assert-unused-exprs
Use (and ignore) the expression provided to log_assert in NDEBUG builds
2020-06-25 18:21:51 +02:00
Marcelina Kościelnicka cb9a8ad0f2 cxxrtl: Add support for the new FF types. 2020-06-24 02:15:08 +02:00
whitequark 2ffdb74fb1 Use (and ignore) the expression provided to log_assert in NDEBUG builds.
This avoids warnings in NDEBUG builds emitted when a variable is only
used in log_assert, but is always defined.
2020-06-19 15:48:58 +00:00
whitequark ede4b10da8
Merge pull request #2173 from whitequark/use-cxx11-final-override
Use C++11 final/override/[[noreturn]]
2020-06-19 06:15:33 +00:00
whitequark 962a2f3bff cxxrtl: add .get() and .set() accessors on value<> and wire<>.
For several reasons:
  * They're more convenient than accessing .data.
  * They accommodate variably-sized types like size_t transparently.
  * They statically ensure that no out of range conversions happen.

For now these are only provided for unsigned integers, but eventually
they should be provided for signed integers too. (Annoyingly this
affects conversions to/from `char` at the moment.)

Fixes #2127.
2020-06-19 02:31:35 +00:00
whitequark 7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
whitequark 8344846787
Merge pull request #2167 from whitequark/cxxrtl-fix-ndebug
cxxrtl: don't compute vital values in log_assert()
2020-06-18 16:57:51 +00:00
whitequark 3c4e974d7b cxxrtl: don't compute vital values in log_assert().
This breaks NDEBUG builds.

Fixes #2166.
2020-06-17 19:27:47 +00:00
whitequark c4f20f744b
Merge pull request #2163 from jfng/cxxrtl-blackbox-debuginfo
cxxrtl: restrict the debug info of a blackbox to its ports.
2020-06-17 06:07:41 +00:00
whitequark eaf66037a5
Merge pull request #2160 from whitequark/cxxrtl-fix-warning
cxxrtl: avoid unused variable warning for transparent $memrd ports
2020-06-17 06:06:58 +00:00
Jean-François Nguyen 8d98c3861d cxxrtl: restrict the debug info of a blackbox to its ports. 2020-06-16 15:30:56 +02:00
whitequark 334ec5fa0a
Merge pull request #2159 from MerryMage/cxxrtl-mul
cxxrtl: Implement chunk-wise multiplication
2020-06-15 06:08:17 +00:00
whitequark 8d70f7abf9 cxxrtl: avoid unused variable warning for transparent $memrd ports. NFC. 2020-06-15 06:00:16 +00:00
MerryMage f7ae9b0851 cxxrtl: Implement chunk-wise multiplication 2020-06-15 05:54:57 +01:00
whitequark 9d0f1aa222
Merge pull request #2158 from miek/sshr-sign-extension
cxxrtl: fix sshr sign-extension.
2020-06-15 01:37:05 +00:00
Mike Walters 66a2de2912 cxxrtl: fix sshr sign-extension. 2020-06-15 01:01:49 +01:00
whitequark 971a765155
Merge pull request #2151 from whitequark/cxxrtl-fix-rzext
cxxrtl: fix rzext()
2020-06-13 22:18:35 +00:00
whitequark dc6961f3d4
Merge pull request #2145 from whitequark/cxxrtl-splitnets
cxxrtl: handle multipart signals
2020-06-13 04:23:22 +00:00
whitequark 107911dbec cxxrtl: always inline internal cells and slice/concat operations.
This can result in massive reduction in runtime, up to 50% depending
on workload. Currently people are using `-mllvm -inline-threshold=`
as a workaround (with clang++), but this solution is more portable.
2020-06-13 01:52:06 +00:00
whitequark 6cf02ed94f cxxrtl: fix rzext().
This was a correctness issue, but one of the consequences is that it
resulted in jumps in generated machine code where there should have
been none. As a side effect of fixing the bug, Minerva SoC became 10%
faster.
2020-06-13 00:49:44 +00:00
whitequark b793e4753b cxxrtl: elide $pmux cells.
On Minerva, this improves runtime by around 10%, mostly by ensuring
that the logic driving FFs is packed into edge conditionals.
2020-06-12 02:40:30 +00:00
whitequark d5ecd4a570 cxxrtl: annotate port direction as comments. 2020-06-12 00:35:18 +00:00
whitequark 29bd81d662 cxxrtl: unbuffer output wires of toplevel module.
Without unbuffering output wires of, at least, toplevel modules, it
is not possible to have most designs that rely on IO via toplevel
ports (as opposed to using exclusively blackboxes) converge within
one delta cycle. That seriously impairs the performance of CXXRTL.

This commit avoids unbuffering outputs of all modules solely so that
in future, CXXRTL could gain fully separate compilation, and not for
any present technical reason.
2020-06-12 00:31:57 +00:00
whitequark cd7bf115b6 cxxrtl: simplify unbuffering of input wires.
This also fixes an edge case with (*keep*) input ports.
2020-06-12 00:31:57 +00:00
whitequark 8d712b1095 cxxrtl: handle multipart signals.
This avoids losing design visibility when using the `splitnets` pass.
2020-06-11 19:34:35 +00:00
whitequark fa04b19670 cxxrtl: expose RTLIL::{Wire,Memory}->start_offset in debug info. 2020-06-11 12:43:17 +00:00
whitequark 8a4841d786
Merge pull request #2141 from whitequark/cxxrtl-cxx11
cxxrtl: various compiler compatibility fixes
2020-06-10 17:10:15 +00:00
whitequark 6021ff727d cxxrtl: restore C++11 compatibility.
This is necessary to be able to build CXXRTL models via yosys-config.
2020-06-10 15:57:07 +00:00
whitequark cde99e696a cxxrtl: fix a few gcc warnings. 2020-06-10 15:57:07 +00:00
whitequark 574f5cb5b2 Fix formatting. NFC. 2020-06-10 15:48:40 +00:00
whitequark 0955a603c8 cxxrtl: disambiguate values/wires and their aliases in debug info.
With this change, it is easier to see which signals carry state (only
wire<>s appear as `reg` in VCD files) and to construct a minimal
checkpoint (CXXRTL_WIRE debug items represent the canonical smallest
set of state required to fully reconstruct the simulation).
2020-06-10 14:39:45 +00:00
whitequark 5467fe563a cxxrtl: allow unbuffering without localizing.
Although logically two separate steps, these were treated as one for
historic reasons. Splitting the two makes it possible to have designs
that are only 2× slower than fastest possible (and are without extra
delta cycles) that allow probing all public wires.
2020-06-09 21:50:09 +00:00
whitequark 970ec34e70 cxxrtl: order -On levels as localize, elide instead of the reverse.
Historically, elision was implemented before localization, so levels
with elision are lower than corresponding levels with localization.
This is unfortunate for two reasons:
  1. Elision is a logical subset of localization, since it equals to
     not giving a name to a temporary.
  2. "Localize" currently actually means "unbuffer and localize",
     and it would be useful to split those steps (at least for
     public wires) for improved design visibility.
2020-06-09 20:55:40 +00:00
whitequark ba11060e59 cxxrtl: factor out -noproc/-noflatten from -O.
Although these options can be thought of as optimizations, they are
essentially orthogonal to the core of -O, which is managing signal
buffering and scope. Going from -O4 to -O2 means going from limited
to complete design visibility, yet in both cases proc and flatten
are desirable.
2020-06-09 20:18:07 +00:00
whitequark bbfe55a8d0 cxxrtl: fix two buggy split_by functions. 2020-06-09 11:05:35 +00:00
whitequark 74e3ac2449
Merge pull request #2126 from whitequark/cxxrtl-non-ext-logic-ops
cxxrtl: ignore cell input signedness when it is irrelevant
2020-06-09 09:54:09 +00:00
whitequark ef4e159447 cxxrtl: ignore cell input signedness when it is irrelevant.
Before this commit, Verilog expressions like `x && 1` would result in
references to `logic_and_us` in generated CXXRTL code, which would
not compile. After this commit, since cells like that actually behave
the same regardless of signedness attributes, the signedness is
ignored, which also reduces the template instantiation pressure.
2020-06-09 07:26:13 +00:00
whitequark 4e7d837747 cxxrtl: add missing namespace.
Fixes #2124.
2020-06-09 06:26:43 +00:00
whitequark 53688a24b5 cxxrtl: fix format of hdlnames.
The CXXRTL code that handled the `hdlname` attribute implemented
outdated semantics.
2020-06-08 20:19:41 +00:00
whitequark 467152d79f cxxrtl: don't check immutable values for changes in VCD writer.
This commit changes the VCD writer such that for all signals that
have `debug_item.type == VALUE && debug_item.next == nullptr`, it
would only sample the value once.

Commit f2d7a187 added more debug information by including constant
wires, and decreased the performance of VCD writer proportionally
because the constant wires were still repeatedly sampled; this commit
eliminates the performance hit.
2020-06-08 17:38:11 +00:00
whitequark f2d7a18756 cxxrtl: emit debug information for constant wires.
Constant wires can represent a significant chunk of the design in
generic designs or after optimization. Emitting them in VCD files
significantly improves usability because gtkwave removes all traces
that are not present in the VCD file after reload, and iterative
development suffers if switching a varying signal to a constant
disrupts the workflow.
2020-06-08 17:29:08 +00:00
whitequark d5c07e5b6f cxxrtl: track aliases in VCD writer.
This commit changes the VCD writer such that for all signals that
share `debug_item.curr`, it would only emit a single VCD identifier,
and sample the value once.

Commit 9b39c6f7 added redundancy to debug information by including
alias wires, and increased the size of VCD files proportionally; this
commit eliminates the redundancy from VCD files so that their size
is the same as before.
2020-06-08 17:10:45 +00:00
whitequark 9b39c6f744 cxxrtl: emit debug information for alias wires.
Alias wires can represent a significant chunk of the design in highly
hierarchical designs; in Minerva SRAM, there are 273 member wires and
527 alias wires. Showing them in every hierarchy level significantly
improves usability.
2020-06-08 17:09:49 +00:00
whitequark 8262997c4e cxxrtl: fix typo in comment. NFC. 2020-06-08 12:50:35 +00:00
whitequark fb3704c896 cxxrtl: minor debug-related improvements. 2020-06-08 12:50:35 +00:00
whitequark ff5500f11a cxxrtl: rename cxxrtl.cc→cxxrtl_backend.cc.
To avoid confusion with the C++ source files that are a part of
the simulation itself and not a part of Yosys build.
2020-06-07 03:48:40 +00:00
whitequark 31f6c96b1f cxxrtl: add a C API for writing VCD dumps.
This C API is fully featured.
2020-06-07 03:48:00 +00:00
whitequark 68362a9053 cxxrtl: only write VCD values that were actually updated.
On a representative design (Minerva SoC) this reduces VCD file size
by ~20× and runtime by ~3×.
2020-06-07 03:48:00 +00:00
whitequark 9c36102669 cxxrtl: add a VCD writer using debug information. 2020-06-07 03:48:00 +00:00
whitequark c399359ed6 cxxrtl: add a C API for driving and introspecting designs.
Compared to the C++ API, the C API currently has two limitations:
  1. Memories cannot be updated in a race-free way.
  2. Black boxes cannot be implemented in C.
2020-06-06 21:12:55 +00:00
whitequark f6e16e7f4c cxxrtl: generate debug information for non-localized public wires.
Debug information describes values, wires, and memories with a simple
C-compatible layout. It can be emitted on demand into a map, which
has no runtime cost when it is unused, and allows late bound designs.

The `hdlname` attribute is used as the lookup key such that original
names, as emitted by the frontend, can be used for debugging and
introspection.
2020-06-06 21:12:55 +00:00
whitequark 784bfec67c
Merge pull request #2110 from BracketMaster/master
MacOS has even stricter stack limits in catalina.
2020-06-06 12:23:06 +00:00
whitequark bd2ecc2dd3
Merge pull request #2113 from whitequark/cxxrtl-fix-sshr
cxxrtl: fix implementation of $sshr cell
2020-06-05 10:24:25 +00:00
N. Engelhardt 9669e0c7d5
Merge pull request #2109 from nakengelhardt/btor_internal_names
btor backend: make not printing internal names default
2020-06-05 11:36:08 +02:00
whitequark 025663adff cxxrtl: fix implementation of $sshr cell.
Fixes #2111.
2020-06-05 02:04:46 +00:00
Yehowshua Immanuel da0778350b
more reasonable numbers for memory 2020-06-04 17:00:04 -04:00
Yehowshua Immanuel 5d29a9f633
MacOS has even stricter stack limits in catalina.
Invoking sby in macOS Catalina fails because of bizarre stack limits in Catalina.
2020-06-04 14:01:56 -04:00
Eddie Hung 69850204c4
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve
abc9: -dff improvements
2020-06-04 08:15:25 -07:00
N. Engelhardt 82798ae575 btor backend: make not printing internal names default 2020-06-04 16:24:16 +02:00
Claire Wolf 5e8a9c61cd Add printf format attributes to btorf/infof helper functions
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-06-04 15:53:28 +02:00
N. Engelhardt 8ceb6686e0 btor backend: add option to not include internal names 2020-06-04 14:00:52 +02:00
whitequark 3bffd09d64
Merge pull request #2006 from jersey99/signed-in-rtlil-wire
Preserve 'signed'-ness of a verilog wire through RTLIL
2020-06-04 11:23:06 +00:00
Eddie Hung 45cd323055
Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixes
abc9: fixes around handling combinatorial loops
2020-06-03 17:35:46 -07:00
clairexen ea46ed81f9
Merge pull request #2018 from boqwxp/qbfsat-timeout
smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, and CVC4.
2020-05-30 15:04:51 +02:00
Alberto Gonzalez ea30465107
smtbmc: Remove superfluous `yosys-smt2-timeout` file macro.
Co-Authored-By: clairexen <claire@symbioticeda.com>
2020-05-29 21:33:00 +00:00
clairexen 94c1035389
Merge pull request #1885 from Xiretza/mod-rem-cells
Fix modulo/remainder semantics
2020-05-29 16:37:23 +02:00
clairexen 1c8d5a08a0
Merge pull request #2016 from boqwxp/qbfsat-yices
qbfsat: Add `-solver` option and allow choice of Z3 or Yices, making Yices the default.
2020-05-29 16:21:45 +02:00
Xiretza edd8ff2c07
Add flooring division operator
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $divfloor cell provides this flooring division.

This commit also fixes the handling of $div in opt_expr, which was
previously optimized as if it was $divfloor.
2020-05-28 22:59:04 +02:00
Xiretza 17163cf43a
Add flooring modulo operator
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $modfloor cell provides this flooring modulo (also known as "remainder"
in several languages, but this name is ambiguous).

This commit also fixes the handling of $mod in opt_expr, which was
previously optimized as if it was $modfloor.
2020-05-28 22:59:03 +02:00
whitequark 736ccb2ad5
Merge pull request #2031 from epfl-vlsc/master
Add extmodule support to firrtl backend
2020-05-28 09:59:17 +00:00
whitequark 2974183855
Merge pull request #2063 from boqwxp/techmapped-firrtl
firrtl: Accept techmapped cell types in FIRRTL backend.
2020-05-28 09:42:58 +00:00
whitequark 0bf6b164be cxxrtl: make logging a little bit nicer. 2020-05-26 21:37:32 +00:00
whitequark e9c07e2bda cxxrtl: add missing parts of commit 281c9685. 2020-05-26 21:34:20 +00:00
Eddie Hung 1826370b3a xaiger: promote abc9_keep wires 2020-05-25 16:40:30 -07:00
Alberto Gonzalez 9847a4eea8
smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, and CVC4. 2020-05-25 20:39:30 +00:00
Alberto Gonzalez 54570a3978
qbfsat: Move SMT2 info statements back to the top of the file. 2020-05-25 20:38:29 +00:00
Alberto Gonzalez 903456c267
qbfsat: Add `-solver` option and allow choice of Z3 or Yices, making Yices the default.
Ensures that "BV" is the logic whenever solving an exists-forall problem with Yices, moves the "(set-logic ...)" directive above any non-info line, sets the `ef-max-iters` parameter to a very high number when using Yices in exists-forall mode so as not to prematurely abandon difficult problems, and does not provide the incompatible "--incremental" Yices argument when in exists-forall mode.
2020-05-25 20:38:29 +00:00
Eddie Hung 9e6c288e5a xaiger: cleanup 2020-05-25 08:43:33 -07:00
Eddie Hung d64df21630 xaiger: do not derive cells 2020-05-24 08:17:30 -07:00
whitequark 281c96856a cxxrtl: get rid of -O5 aka `opt_clean -purge` optimization level.
This isn't actually necessary anymore after scheduling was improved,
and `clean -purge` disrupts the mapping between wires in the input
RTLIL netlist and the output CXXRTL code.
2020-05-22 19:08:30 +00:00
N. Engelhardt 7c4e580f8f
Merge pull request #2054 from boqwxp/fix-smtbmc
smtbmc: Fix return status handling.
2020-05-20 08:55:36 +02:00
Alberto Gonzalez 1053032a81
smtbmc: Fix typo in error message.
Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
2020-05-19 16:13:44 +00:00
Alberto Gonzalez 049e4caceb
firrtl: Accept techmapped cell types in FIRRTL backend. 2020-05-17 10:03:11 +00:00
Eddie Hung 67fc0c3698 abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_
instead of moving them to $__ prefix
2020-05-14 16:44:35 -07:00
Eddie Hung 97a0a04314 abc9_ops/xaiger: further reducing Module::derive() calls by ...
replacing _all_ (* abc9_box *) instantiations with their derived types
2020-05-14 10:33:57 -07:00
Eddie Hung e79127fceb Cleanup; reduce Module::derive() calls 2020-05-14 10:33:57 -07:00
Eddie Hung e357b40e7a xaiger: no longer use nonstandard even/odd to designate +ve/-ve polarity 2020-05-14 10:33:56 -07:00
Eddie Hung 722540dbf9 abc9: not enough to techmap_fail on (* init=1 *), hide them using $__ 2020-05-14 10:33:56 -07:00
Eddie Hung 63246a5c0e Revert "Merge pull request #1917 from YosysHQ/eddie/abc9_delay_check"
This reverts commit 759283fa65, reversing
changes made to f41c7ccfff.
2020-05-14 10:33:56 -07:00
Eddie Hung 4c6647a469 xaiger: always sort input/output bits by port id
redundant for normal design, but necessary for holes
2020-05-14 10:33:56 -07:00
Eddie Hung ec4bbb1444 abc9: generate $abc9_holes design instead of <name>$holes 2020-05-14 10:33:56 -07:00
Eddie Hung 6f4f795953 aiger/xaiger: use odd for negedge clk, even for posedge
Since abc9 doesn't like negative mergeability values
2020-05-14 10:33:56 -07:00
Eddie Hung f975cf39cb xaiger: update help text 2020-05-14 10:33:56 -07:00
Eddie Hung 90cd49995b xaiger: do not treat (* init=1'bx *) as 1'b0 2020-05-14 10:33:56 -07:00
Eddie Hung 77f3abcdc3 xaiger: when -dff use (* init *) for initial state 2020-05-14 10:33:56 -07:00
Eddie Hung 95763c8d18 abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxes 2020-05-14 10:33:56 -07:00
Eddie Hung ffa52738fb xaiger: output $_DFF_[NP]_ with mergeability if -dff option 2020-05-14 10:33:56 -07:00
Alberto Gonzalez 299ab76a09
smtbmc: Fix return status handling. 2020-05-14 17:07:59 +00:00
Xiretza d86fc791f9
Reorder cases to avoid fall-through warning
log_assert(false) never returns and thus can't fall through, but gcc
doesn't seem to think that far. Making it the last case avoids the
problem entirely.
2020-05-07 13:39:34 +02:00
Xiretza 695150b037
Add YS_FALLTHROUGH macro to mark case fall-through
C++17 introduced [[fallthrough]], GCC and clang had their own vendored
attributes before that. MSVC doesn't seem to have such a warning at all.
2020-05-07 13:39:34 +02:00
Sahand Kashani 1688a62500 Formatting fixes 2020-05-06 21:15:32 +02:00
Sahand Kashani 1f1b64b880 Add extmodule support to firrtl backend
The current firrtl backend emits blackboxes as standard modules
with an empty body, but this causes the firrtl compiler to
optimize out entire circuits due to the absence of any drivers.

Yosys already tags blackboxes with a (*blackbox*) attribute, so this
commit just propagates this change to firrtl's syntax for blackboxes.
2020-05-06 01:01:14 +02:00
Eddie Hung a0afa1787e aiger: fixes for ports that have start_offset != 0 2020-05-02 10:00:32 -07:00
Vamsi K Vytla 5f9cd2e2f6 Preserve 'signed'-ness of a verilog wire through RTLIL
As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now:

RTLIL::wire holds an is_signed field.
This is exported in JSON backend
This is exported via dump_rtlil command
This is read in via ilang_parser
2020-04-27 09:44:24 -07:00
David Shah 1b93dda037 cxxrtl: Round up constant width
Signed-off-by: David Shah <dave@ds0.me>
2020-04-25 10:42:21 +01:00
whitequark a0e658d412 cxxrtl: use `cxxrtl_` prefix rather than `cxxrtl.`
The former prefix does not need to be escaped in Verilog, unlike
the latter, and the Yosys convention is to use the former.
2020-04-24 18:35:53 +00:00
whitequark f88378ae61 cxxrtl: improve printing of narrow memories. 2020-04-24 05:50:36 +00:00
whitequark 3738391bdd cxxrtl: fix handling of parametric modules with large parameters.
These have a `$paramod$` prefix, not `$paramod\\`.
2020-04-24 05:44:39 +00:00
Asu dc77563a6a cxxrtl: keep the memory write queue sorted on insertion.
Strategically inserting the pending memory write in memory::update to keep the
queue sorted allows us to skip the queue sort in memory::commit.

The Minerva SRAM SoC runs ~7% faster as a result.
2020-04-22 20:53:12 +02:00
Claire Wolf 95c74b319b
Merge pull request #1979 from whitequark/cxxrtl-go-faster
cxxrtl: Gas gas gas! I'm gonna step on the gas! Tonight I'll fly!
2020-04-22 16:50:45 +02:00
whitequark 93288b8eae cxxrtl: run edge detectors only once in eval().
As a result, Minerva SRAM SoC runs ~15% faster.
2020-04-22 12:47:28 +00:00
whitequark 1d5b6ac253 cxxrtl: add an unsupported knob for manipulating clock trees.
This is quite possibly the worst way to implement this, but it does
work for a subset of well-behaved designs, and can be used to measure
how much performance is lost simulating the inactive edge of a clock.

It should be replaced with a clock tree analyzer generating safe
code once it is clear how should such a thing look like.
2020-04-22 01:15:27 +00:00
whitequark 5f17e0ced5 cxxrtl: use log_id() where appropriate. NFC. 2020-04-21 23:42:56 +00:00
whitequark d22a8d157d cxxrtl: add (*cxxrtl.{comb,sync}*) annotations on black box outputs.
If the annotations are not used, this commit does not alter semantics
at all, other than removing elision of outputs of black box cells.
(Elision of such outputs is expected to be too rare to have any
noticeable benefit, and the implementation was somewhat of a hack.)

The (* cxxrtl.comb *) annotation alters the semantics of the output
of the black box it is applied to such that, if the black box
converges immediately, no additional delta cycle is necessary to
propagate the computed combinatorial value upwards in hierarchy.

The (* cxxrtl.sync *) annotation alters the semantics of the output
of the black box it is applied to such as to remove any uses of
the black box by the wires connected to this output, and break false
feedback arcs arising from conservative modeling of dependencies of
the black box.

Although currently these attributes are only recognized on black
boxes, if separate compilation is added in the future, it could also
emit and consume them.
2020-04-21 22:08:36 +00:00
whitequark 164b0746d2 cxxrtl: s/sync_{wire,type}/edge_{wire,type}/. NFC.
The attribute for this is called (* cxxrtl.edge *), and there is
a planned attribute (* cxxrtl.sync *) that would cause blackbox
cell outputs to be added to sync defs rather than comb defs.
Rename the edge detector related stuff to avoid confusion.
2020-04-21 18:46:36 +00:00
Marcelina Kościelnicka 02f1c7b9af write_json: dump default parameter values
Fixes #1823.

This will allow nextpnr to reuse the default value information already
present in yosys cells_sim.v and avoid duplicating (and probably
desyncing) this information.
2020-04-21 19:09:00 +02:00
Marcelina Kościelnicka 06a344efcb ilang, ast: Store parameter order and default value information.
Fixes #1819, #1820.
2020-04-21 19:09:00 +02:00
Claire Wolf a6f9e28680
Merge pull request #1971 from YosysHQ/claire/edifkeep
Ignore conflicting keep attributes, unless asked not to
2020-04-21 19:04:55 +02:00
whitequark 4aa0f450f5 cxxrtl: use one delta cycle for immediately converging netlists.
If it is statically known that eval() will converge in one delta
cycle (that is, the second commit() will always return `false`)
because the design contains no feedback or buffered wires, then
there is no need to run the second delta cycle at all.

After this commit, the case where eval() always converges immediately
is detected and the second delta cycle is omitted. As a result,
Minerva SRAM SoC runs ~25% faster.
2020-04-21 16:14:45 +00:00
whitequark 7f5313e6c3 cxxrtl: add -O6, a shortcut for running `proc; flatten`.
People judge a compiler backend by the first impression, and
the metric they judge it for is speed. -O6 does severely impact
debuggability, but it provides equally massive gains in performance,
so use it by default.
2020-04-21 15:33:12 +00:00
whitequark 06985c3afd cxxrtl: unbuffer module input wires.
Module input wires are never set by the module, so it is unnecessary
to buffer them. Although important for all inputs, this is especially
critical for clocks, since after this commit, hierarchy levels no
longer add delta cycles. As a result, Minerva SRAM SoC runs ~73%
faster when flattened, and ~264% (!!) faster when hierarchical.
2020-04-21 15:27:19 +00:00
whitequark 12c5e9275c cxxrtl: simplify generated edge detection logic.
This commit changes the way edge detectors are represented in
generated code from a variable that is set in commit() and reset in
eval() to a function that considers .curr and .next of the clock
wire. Behavior remains the same. Besides being simpler to generate
and providing more opportunities for optimization, this commit paves
way for unbuffering module inputs.
2020-04-21 13:59:42 +00:00
whitequark 757cbb3c80 cxxrtl: localize wires with multiple comb drivers, too.
Before this commit, any wire that was not driven by an output port of
exactly one comb cell would not be localized, even if there were no
feedback arcs through that wire. This would cause the wire to become
buffered and require (often quite a few) extraneous delta cycles
during evaluation. To alleviate this problem, -O5 was running
`splitnets -driver`.

However, this solution was mistaken. Because `splitnets -driver`
followed by `opt_clean -purge` would produce more nets with multiple
drivers, it would have to be iterated to fixpoint. Moreover, even if
this was done, it would not be sufficient because `opt_clean -purge`
does not currently remove wires with the `\init` attribute (and it
is not desirable to remove such wires, since they correspond to
registers and may be useful for debugging).

The proper solution is to consider the condition in which a wire
may be localized. Specifically, if there are no feedback arcs through
this wire, and no part of the wire is driven by an output of a sync
cell, then the wire holds no state and is localizable.

After this commit, the original condition for not localizing a wire
is replaced by a check for any sync cell driving it. This makes it
unnecessary to run `splitnets -driver` in the majority of cases
to get a design with no buffered wires, and -O5 no longer includes
that pass. As a result, Minerva SRAM SoC no longer has any buffered
wires, and runs ~27% faster.

In addition, this commit prepares the flow graph for introduction
of sync outputs of black boxes.

Co-authored-by: Jean-François Nguyen <jf@lambdaconcept.com>
2020-04-21 13:36:50 +00:00
whitequark f24fb4ae82 cxxrtl: detect buffered comb wires, not just feedback wires.
Any buffered combinatorial wires (including, as a subset, feedback
wires) will prevent the design from always converging in one delta
cycle. Before this commit, only feedback wires were detected. After
this commit, any buffered combinatorial wires, including feedback
wires, are detected.

Co-authored-by: Jean-François Nguyen <jf@lambdaconcept.com>
2020-04-21 13:36:50 +00:00
Claire Wolf 27506d2aeb Improve net priorities in EDIF back-end
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-21 12:35:25 +02:00
whitequark abc8f1fcb6
Merge pull request #1961 from whitequark/paramod-original-name
ast, rpc: record original name of $paramod\* as \hdlname attribute
2020-04-21 01:43:20 +00:00
Claire Wolf ee5067e864 Ignore conflicting keep attributes, unless asked not to. Fixes #1733
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-20 16:00:37 +02:00
whitequark bf0f96b847 cxxrtl: provide attributes to black box factories, too.
Both parameters and attributes are necessary because the parameters
have to be the same between every instantiation of the cell, but
attributes may well vary. For example, for an UART PHY, the type
of the PHY (tty, pty, socket) would be a parameter, but configuration
of the implementation specified by the type (socket address) would
be an attribute.
2020-04-19 16:30:54 +00:00
whitequark 63d2a30857 cxxrtl: add templated black box support. 2020-04-18 08:04:57 +00:00
whitequark ab4297c326 cxxrtl: make eval() and commit() inline in blackboxes.
This change is a preparation for template blackboxes. It has no
effect on current generated code.
2020-04-18 04:38:50 +00:00
whitequark 2b88d9a3fe cxxrtl: add simple black box support.
This commit adds support for replacing RTLIL modules with CXXRTL
black boxes. Black box port widths may not depend on the parameters
with which it is instantiated (yet); the parameters may only be used
to change the behavior of the black box.
2020-04-18 04:35:10 +00:00
whitequark 8bc3cd30dc cxxrtl: use ID::X instead of ID(X). NFC. 2020-04-18 04:35:10 +00:00
whitequark 41421f5dca ast, rpc: record original name of $paramod\* as \hdlname attribute.
The $paramod name mangling is not invertible (the \ character, which
separates the module name from the parameters, is valid in the module
name itself), which does not stop people from trying to invert it.

This commit makes it easy to invert the name mangling by storing
the original name explicitly, and fixes the firrtl backend to use
the newly introduced attribute.
2020-04-18 03:47:28 +00:00
whitequark e7ad209b15 cxxrtl: correctly handle `sync always` rules.
Fixes #1948.
2020-04-17 09:43:13 +00:00
whitequark b4b2345a10
Merge pull request #1947 from whitequark/cxxrtl-usability
cxxrtl: minor documentation and usability improvements
2020-04-16 21:28:13 +00:00
Claire Wolf 7a434cdd7b
Merge pull request #1797 from epfl-vlsc/firrtl_backend_fileinfo
Keep file information when emitting firrtl
2020-04-16 18:50:43 +02:00
whitequark 06c0338f2c cxxrtl: make ROMs writable, document memory::operator[].
There is no practical benefit from using `const memory` for ROMs;
it uses an std::vector internally, which prevents contemporary
compilers from constant-propagating ROM contents. (It is not clear
whether they are permitted to do so.)

However, there is a major benefit from using non-const `memory` for
ROMs, which is the ability to dynamically fill the ROM for each
individual simulation.
2020-04-16 16:45:54 +00:00
whitequark 9043632dcc cxxrtl: fix misleading example, caution about race conditions.
Fixes #1944.
2020-04-16 16:45:54 +00:00
whitequark 58e89cd368 cxxrtl: remove inaccurate comment. NFC. 2020-04-16 16:45:54 +00:00
N. Engelhardt 0b7a5879e5
Merge pull request #1830 from boqwxp/qbfsat
Add `qbfsat` command to integrate exists-forall solving and specialization
2020-04-15 17:33:50 +02:00
Marcelina Kościelnicka 3611e7c864 json: Update format documentation.
Fixes #1693.
2020-04-15 16:12:14 +02:00
David Shah 3b85b7c57a cxxrtl: Fix handling of unclocked memory read ports
Signed-off-by: David Shah <dave@ds0.me>
2020-04-14 20:39:13 +01:00
whitequark d8f2a1fda0
Merge pull request #1922 from whitequark/write_cxxrtl-disconnected-outputs
write_cxxrtl: ignore disconnected module ports
2020-04-14 14:37:48 +00:00
whitequark 7025881a5e
Merge pull request #1921 from whitequark/write_cxxrtl-separate-compilation
write_cxxrtl: enable separate compilation
2020-04-14 13:53:52 +00:00
whitequark 0d0bf9c4a2 write_cxxrtl: ignore disconnected module ports.
E.g. port `q` in `submod x(.p(p), .q());`.

Fixes #1920.
2020-04-14 12:36:20 +00:00
whitequark 9c64d37a4c write_verilog: fix precondition check. 2020-04-14 12:12:50 +00:00
whitequark 102fb5424f write_cxxrtl: enable separate compilation.
This commit makes it possible to use several cxxrtl-generated files
in one application, as well as compiling cxxrtl-generated code as
a separate compilation unit.
2020-04-14 12:07:58 +00:00
Eddie Hung 0808318d55 xaiger: add check for $__ABC9_DELAY model 2020-04-13 19:11:23 -07:00
Miodrag Milanovic 0d789c5a3b Support custom PROGRAM_PREFIX 2020-04-10 10:38:40 +02:00
Sahand Kashani 959a00a46f Fix indentation 2020-04-09 21:16:02 +02:00
whitequark 4737f426ff write_cxxrtl: add basic documentation. 2020-04-09 04:08:36 +00:00
whitequark 753e34007d write_cxxrtl: add support for $dlatch and $dlatchsr cells.
Also, fix codegen for $dffe and $adff.
2020-04-09 04:08:36 +00:00
whitequark 711df56ad0 write_cxxrtl: add support for $sr cell.
Also, fix the semantics of SET/CLR inputs of the $dffsr cell, and
fix the scheduling of async FF cells to consider ARST/SET/CLR->Q
as a forward combinatorial arc.
2020-04-09 04:08:36 +00:00
whitequark 9534b51277 write_cxxrtl: add support for $slice and $concat cells. 2020-04-09 04:08:36 +00:00
whitequark 01e6850bd3 write_cxxrtl: improve writable memory handling.
This commit reduces space and time overhead for writable memories
to O(write port count) in both cases; implements handling for write
port priorities; and simplifies runtime representation of memories.
2020-04-09 04:08:36 +00:00
whitequark fb0270b752 write_cxxrtl: add support for hierarchical designs.
Hierarchical design simulations are generally much slower, but this
comes with a major increase in flexibility:
 1. Since the `flatten` pass currently does not support flattening
    of designs with processes, this is the only way to simulate such
    designs with cxxrtl.
 2. Support for hierarchy paves way for simulation black boxes,
    which are necessary for e.g. replacing PHYs with C++ code that
    integrates with the host system.
2020-04-09 04:08:36 +00:00
whitequark 3376dcf37c write_cxxrtl: avoid undefined behavior on out-of-bounds memory access.
After this commit, if NDEBUG is not defined, out-of-bounds accesses
cause assertion failures for reads and writes. If NDEBUG is defined,
out-of-bounds reads return zeroes, and out-of-bounds writes are
ignored.

This commit also adds support for memories that start with a non-zero
index (`Memory::start_offset` in RTLIL).
2020-04-09 04:08:36 +00:00
whitequark 5157691f0e write_cxxrtl: statically schedule comb logic and localize wires.
This results in further massive gains in performance, modest decrease
in compile time, and, for designs without feedback arcs, makes it
possible to run eval() once per clock edge in certain conditions.
2020-04-09 04:08:36 +00:00
whitequark d6d7273421 write_cxxrtl: elide wires for results of comb cells used once.
This results in massive gains in performance, equally massive
reduction in compile time, and improved readability.
2020-04-09 04:08:36 +00:00
whitequark d20e971725 write_cxxrtl: new backend.
This commit adds a basic implementation that isn't very performant
but implements most of the planned features.
2020-04-09 04:08:36 +00:00
Sahand Kashani ac388859e3 Remove dependency on ilang backend since we no longer use it 2020-04-08 23:59:22 +02:00
Sahand Kashani 9edf8869c1 Merge branch 'master' of github.com:YosysHQ/yosys into firrtl_backend_fileinfo 2020-04-08 23:50:37 +02:00
Sahand Kashani 820e3d1dad Remove unnecessary pruning of double-quoting
In the past I was calling the ILANG_BACKEND::dump_const() to dump
values to an output stream. When these values were strings, the
function used to add quotes around them. The firrtl compiler, in turn,
escaped these quotes and the result was double-quoted strings which
were hard to read.

However I'm now calling design_entity->get_src_attribute() directly
and there is no additional quote being put around it, so we can
safely remove the unnecessary call to str.erase() here.
2020-04-08 23:20:56 +02:00
Alberto Gonzalez 437afa1f0c
Updated `yosys-smtbmc` to optionally dump raw bit strings, and fixed hole value recovery using that mode. 2020-04-04 22:13:25 +00:00
Eddie Hung 956ecd48f7 kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
Eddie Hung dde3dfd72e Update backends/btor/btor.cc; credit @boqwxp
Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
2020-04-02 07:14:08 -07:00
Eddie Hung fdafb74eb7 kernel: use more ID::* 2020-04-02 07:14:08 -07:00
Claire Wolf d1fc4321f0
Merge pull request #1770 from YosysHQ/claire/btor_symbols
Improve write_btor symbol handling
2020-04-02 15:38:47 +02:00
Claire Wolf 104c004e6d
Merge pull request #1765 from YosysHQ/claire/btor_info
Add info-file and cover features to write_btor
2020-04-02 15:38:27 +02:00
Alberto Gonzalez c23c2c59c1
Update `RTLIL::id2cstr()` usage to `log_id`. 2020-04-01 06:53:28 +00:00
Alberto Gonzalez cdb14652be
Clean up pseudo-private member usage in `backends/intersynth/intersynth.cc`. 2020-04-01 06:32:09 +00:00
Alberto Gonzalez 24ef73904f
Clean up pseudo-private member usage in `backends/blif/blif.cc`. 2020-04-01 05:50:48 +00:00
Alberto Gonzalez f657fed24c
Clean up pseudo-private member usage in `backends/verilog/verilog_backend.cc`. 2020-04-01 05:25:10 +00:00
Alberto Gonzalez 68c0e3562e
Clean up pseudo-private member usage in `backends/spice/spice.cc`. 2020-04-01 04:56:52 +00:00
Alberto Gonzalez 057976c323
Clean up pseudo-private member usage in `backends/edif/edif.cc`. 2020-04-01 04:37:07 +00:00
Alberto Gonzalez 68fef4ca7f
Clean up pseudo-private member usage in `backends/ilang/ilang_backend.cc`. 2020-04-01 03:08:39 +00:00
Alberto Gonzalez d72cb8ea2a
Do not change solver output parsing for non-exists-forall problems. 2020-03-26 23:00:00 +00:00
Alberto Gonzalez 5accf08ef9
Skip reading stdout from the solver that if it isn't a line reading only "sat", "unsat", or "unknown". 2020-03-26 01:21:01 +00:00
Sahand Kashani 6c2b220af5 Remove use of auto for simple types + simplify src attribute computation 2020-03-24 21:07:08 +01:00
Claire Wolf c9555c9ade Revert part of 0fda8308 from #1746 that broke other smtbmc flows
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-03-24 17:33:46 +01:00
Sahand Kashani 018116e478 Refactor to directly call ILANG_BACKEND::dump_const() + directly lookup src attribute 2020-03-24 10:55:21 +01:00
Teguh Hofstee b08932cb81 fix typo in `write_smt2` help 2020-03-23 02:14:26 -07:00
Sahand Kashani f48fb26c0f Indentation conventions 2020-03-23 09:01:17 +01:00
Sahand Kashani-Akhavan 566e08485a
Const parameter in function (backends/firrtl/firrtl.cc)
Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
2020-03-23 08:56:28 +01:00
Sahand Kashani 21492914a2 Strip quotes around fileinfo strings
Yosys puts quotes around the string that represents the fileinfo whereas
firrtl does not. So when firrtl sees quotes, it escapes them with an extra
backslash which makes it hard to read afterwards.
2020-03-21 15:57:53 +01:00
Sahand Kashani c0b2a9af2e Add fileinfo to firrtl backend for assignments and non-instance cells 2020-03-21 12:54:23 +01:00
Sahand Kashani 3e04e29dec Refactor fileinfo emission characters to single location 2020-03-20 18:31:12 +01:00
Sahand Kashani ed9f8bfe6e Add fileinfo to firrtl backend for instances 2020-03-19 16:24:18 +01:00
Sahand Kashani 59236314f8 Add fileinfo to firrtl backend for modules and wires 2020-03-19 14:59:05 +01:00
Sahand Kashani bdce9c28c2 Add fileinfo to firrtl backend for top-level circuit 2020-03-19 00:14:27 +01:00
N. Engelhardt 020f6d167a
Merge pull request #1768 from boqwxp/smt2_cleanup
Clean up pseudo-private member usage in `backends/smt2/smt2.cc`.
2020-03-16 13:49:10 +01:00
N. Engelhardt a2e340de43
Merge pull request #1746 from boqwxp/optimization
Add support for optimizing exists-forall problems.
2020-03-16 12:23:14 +01:00
Claire Wolf bf018b184d Improve write_btor symbol handling
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-03-14 15:49:43 +01:00
Alberto Gonzalez 07f0874779 Clean up pseudo-private member usage in `backends/smt2/smt2.cc`. 2020-03-13 21:49:12 +00:00
Alberto Gonzalez 0fda8308bc Add support for optimizing exists-forall problems.
Modifies smt2 backend to recognize `$anyconst` etc. assigned to a wire with the `maximize` or `minimize` attribute and emit `; yosys-smt2-maximize` or `; yosys-smt2-minimize` directives as appropriate.
Modifies `backends/smt2/smtbmc.py` and `smtio.py` to recognize those directives and emit a `(maximize ...)` or `(minimize ...)` command at the end of `smt_forall_assert()`, as described in the paper "νZ - An Optimizing SMT Solver" by Nikolaj Bjørner et al.
Adds an example `examples/smtbmc/demo9.v` to show how it can be used.
2020-03-13 17:10:29 +00:00
Miodrag Milanovic 746629f18d remove include where not used 2020-03-13 14:55:53 +01:00
Claire Wolf 29e2b2dc05 Add info-file and cover features to write_btor
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-03-13 13:46:32 +01:00
Eddie Hung 3be7784d0e xaiger: remove some unnecessary operations ...
... since they can not be triggered by (* keep *) anymore
(but could still be triggered by (* abc9_scc *) !?!)
2020-03-06 10:51:47 -08:00
Eddie Hung 91a7a74ac4 abc9: (* keep *) wires to be PO only, not PI as well; fix scc handling 2020-03-06 10:20:30 -08:00
Eddie Hung 6bb3d9f9c0 Make TimingInfo::TimingInfo(SigBit) constructor explicit 2020-02-27 10:17:29 -08:00
Eddie Hung 5ff60d2057 write_xaiger: add comment about arrival times of flop outputs 2020-02-27 10:17:29 -08:00
Eddie Hung 1ef1ca812b Get rid of (* abc9_{arrival,required} *) entirely 2020-02-27 10:17:29 -08:00
Eddie Hung e22fee6cdd abc9_ops: ignore (* abc9_flop *) if not '-dff' 2020-02-27 10:17:29 -08:00
Eddie Hung 12d70ca8fb xilinx: improve specify functionality 2020-02-27 10:17:29 -08:00
Eddie Hung 760096e8d2
Merge pull request #1703 from YosysHQ/eddie/specify_improve
Improve specify parser
2020-02-21 09:15:17 -08:00
Eddie Hung f9f86fd758 Revert "abc9: fix abc9_arrival for flops"
This reverts commit f7c0dbecee.
2020-02-14 16:08:04 -08:00
Eddie Hung b523ecf2f4 specify: system timing checks to accept min:typ:max triple 2020-02-13 12:42:15 -08:00
Eddie Hung f5cc8cfa79 write_xaiger: default value for abc9_init 2020-02-13 12:37:17 -08:00
Eddie Hung f7c0dbecee abc9: fix abc9_arrival for flops 2020-02-13 12:34:09 -08:00
R. Ou 20ce4118da json: Change compat mode to directly emit ints <= 32 bits
This increases compatibility with certain older parsers in some cases
that worked before commit 15fae357 but do not work with the current
compat-int mode
2020-02-09 01:01:18 -08:00
whitequark 6f67dd8df5
Merge pull request #1683 from whitequark/write_verilog-memattrs
write_verilog: dump $mem cell attributes
2020-02-07 02:54:04 +00:00
Marcin Kościelnicki 8f559b070a edif: more resilience to mismatched port connection sizes.
Fixes #1653.
2020-02-06 18:45:03 +01:00
whitequark e95a8ba763 write_verilog: dump $mem cell attributes.
The Verilog backend already dumps attributes on RTLIL::Memory objects
but not on `$mem` cells.
2020-02-06 16:22:42 +00:00
Eddie Hung 0671ae7d79
Merge pull request #1661 from YosysHQ/eddie/abc9_required
abc9: add support for required times
2020-02-05 18:59:40 +01:00
Marcin Kościelnicki 00fba62711 json: remove the 32-bit parameter special case
Before, the rules for encoding parameters in JSON were as follows:

- if the parameter is not a string:

  - if it is exactly 32 bits long and there are no z or x bits, emit it
    as an int
  - otherwise, emit it as a string made of 0/1/x/z characters

- if the parameter is a string:

  - if it contains only 0/1/x/z characters, append a space at the end
    to distinguish it from a non-string
  - otherwise, emit it directly

However, this caused a problem in the json11 parser used in nextpnr:
yosys emits unsigned ints, and nextpnr parses them as signed, using
the value of INT_MIN for values that overflow the signed int range.
This caused destruction of LUT5 initialization values.  Since both
nextpnr and yosys parser can also accept 32-bit parameters in the
same encoding as other widths, let's just remove that special case.
The old behavior is still left behind a `-compat-int` flag, in case
someone relies on it.
2020-02-01 16:16:26 +01:00
Claire Wolf 50d70288d0 Preserve wires with keep attribute in EDIF back-end
Signed-off-by: Claire Wolf <clifford@clifford.at>
2020-01-29 14:07:11 +01:00
Eddie Hung 48f3f5213e
Merge pull request #1619 from YosysHQ/eddie/abc9_refactor
Refactor `abc9` pass
2020-01-27 13:29:15 -08:00
Eddie Hung f2576c096c Merge branch 'eddie/abc9_refactor' into eddie/abc9_required 2020-01-27 12:29:28 -08:00
Claire Wolf 485f31f681 Improve yosys-smtbmc "solver not found" handling
Signed-off-by: Claire Wolf <clifford@clifford.at>
2020-01-27 17:48:56 +01:00
Eddie Hung 3d9737c1bd Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-21 16:27:40 -08:00
Eddie Hung cd8f55a911 write_xaiger: fix for (* keep *) on flop output 2020-01-21 09:43:04 -08:00
Claire Wolf 30642e9570
Merge pull request #1629 from YosysHQ/mwk/edif-z
edif: Just ignore connections to 'z
2020-01-21 18:35:15 +01:00
Eddie Hung 38aa248385 Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required 2020-01-15 11:26:11 -08:00
Eddie Hung d6da9c0c0f write_xaiger: skip abc9_flop only if abc_box_seq present 2020-01-15 11:25:20 -08:00
Eddie Hung 485e08e436 abc9_ops: cope with (* abc9_flop *) in place of (* abc9_box_id *) 2020-01-14 16:33:41 -08:00
Eddie Hung 48984a7605 Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required 2020-01-14 16:32:46 -08:00
Eddie Hung 1c41dc6b95 write_xaiger: do not export flop inputs as POs 2020-01-14 16:17:27 -08:00
Eddie Hung 0e4285ca0d abc9_ops: generate flop box ids, add abc9_required to FD* cells 2020-01-14 15:05:49 -08:00
Eddie Hung 588a713b54 Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required 2020-01-14 14:28:07 -08:00