9 Commits

Author	SHA1	Message	Date
Miodrag Milanovic	ff9f1fb86e	Start unification effort for machxo2 and ecp5	2023-03-20 09:58:41 +01:00
Marcelina Kościelnicka	15b0d717ed	iopadmap: Add native support for negative-polarity output enable.	2021-11-09 15:40:16 +01:00
William D. Jones	4e9def23de	machxo2: Tristate is active-low.	2021-02-23 17:39:58 +01:00
William D. Jones	8348c45e4f	machxo2: Fix naming of TRELLIS_IO ports to match PIO pins in routing graph.	2021-02-23 17:39:58 +01:00
William D. Jones	c76f361b56	machxo2: synth_machxo2 now maps ports to FACADE_IO.	2021-02-23 17:39:58 +01:00
William D. Jones	427fed23ee	machxo2: Improve LUT4 techmap. Use same output port name for LUT4 as Lattice.	2021-02-23 17:39:58 +01:00
William D. Jones	84937e9689	machxo2: Add dff.ys test, fix another cells_map.v typo.	2021-02-23 17:39:58 +01:00
William D. Jones	044393b990	machxo2: Fix more oversights in machxo2 models. logic.ys test passes.	2021-02-23 17:39:58 +01:00
William D. Jones	88c8f81260	machxo2: Create basic techlibs and synth_machxo2 pass.	2021-02-23 17:39:58 +01:00