Martin Povišer
fed2720999
synth_lattice: Optimize flip-flop memories better
...
After `memory_map` maps memories to flip-flops we need to let `opt`
remove undef muxes, otherwise we block enable/reset signal inference by
`opt_dff` which is in detriment to QoR.
2023-11-07 16:29:56 +01:00
Martin Povišer
ee3a4ce14d
synth_lattice: Merge NOT gates on DFF control signals
...
`dfflegalize` will emit NOT gates to drive control signals on flip-flops
when mapping to supported flip-flop polarities. Typically in a design
this will produce a number of NOT gates driven by the same signal. For
one reason or another ABC doesn't fully cancel this redundancy during
LUT mapping. Insert an explicit `opt_merge` pass to improve synthesis
QoR.
2023-11-07 16:21:39 +01:00
Lofty
b8b47f7c6c
Revert "ice40, ecp5: enable ABC9 by default"
2023-11-03 14:52:52 +00:00
Lofty
32082477b5
ice40, ecp5: enable ABC9 by default
2023-11-03 08:52:54 +00:00
Lofty
294844137b
gowin: fix abc9 attributes and specify blocks
2023-10-04 00:16:10 +01:00
Martin Povišer
54be4aca90
Merge pull request #3924 from andyfox-rushc/master
...
multpass -- create Booth Encoded multipliers for
2023-09-18 16:46:59 +02:00
Jannis Harder
78ff40d1b2
Run `future` as part of `prep`
2023-09-13 11:32:36 +02:00
Miodrag Milanovic
27ac912709
Support import of $future_ff
2023-09-13 11:32:36 +02:00
Miodrag Milanovic
54050a8c16
Basic support for tag primitives
2023-09-13 11:32:36 +02:00
andyfox-rushc
0fa412502c
mult -> booth in synth.cc, to turn on use synth -booth
2023-09-08 16:44:59 -07:00
andyfox-rushc
1d92ea8001
Support for turning on mult pass from generic synth command
2023-09-08 16:16:24 -07:00
Miodrag Milanovic
72bec94ef4
Add missing file for XO3D
2023-09-01 10:15:51 +02:00
Miodrag Milanovic
792cf8326e
defult nowidelut for xo2/3/3d
2023-08-29 10:08:55 +02:00
Miodrag Milanovic
b168ff99d0
fix generated blackboxes for ecp5
2023-08-28 16:26:26 +02:00
Miodrag Milanovic
0756285710
enable more primitives supported with nextpnr
2023-08-25 11:45:25 +02:00
Miodrag Milanovic
3b9ebfa672
Addressed code review comments
2023-08-25 11:10:20 +02:00
Miodrag Milanovic
541c1ab567
add script for blackbox extraction
2023-08-23 11:51:00 +02:00
Miodrag Milanovic
75fd706487
delete machxo2 since it is now supported in lattice
2023-08-23 10:54:17 +02:00
Miodrag Milanovic
e3c15f003e
Create synth_lattice
2023-08-23 10:53:21 +02:00
Miodrag Milanovic
a8809989c4
ecp5_gsr -> lattice_gsr, change opt_lut_ins to accept lattice as tech
2023-08-22 10:50:11 +02:00
Charlotte
d130f7fca2
tests: use /usr/bin/env for bash.
2023-08-12 11:59:39 +10:00
Charlotte
f9d38253c5
ast: add `PRIORITY` to `$print` cells
2023-08-11 04:46:52 +02:00
Charlotte
4e94f62116
simlib: blackbox `$print` cell
...
It's possible to `generate` the appropriate always blocks per the
triggers, but unlikely to be worth parsing the RTLIL \FORMAT parameter.
2023-08-11 04:46:52 +02:00
Patrick Urban
61387d78b7
gatemate: Prevent implicit declaration of `ram_{we,en}`
2023-06-05 19:08:44 +02:00
Patrick Urban
2004a9ff4a
gatemate: Add CC_FIFO_40K simulation model
2023-05-30 09:06:23 +02:00
Patrick Urban
c244a7161b
gatemate: Fix SDP read behavior
2023-05-30 09:05:43 +02:00
Lofty
fb7af093a8
intel_alm: re-enable 8x40-bit M10K support
2023-05-29 06:42:03 +01:00
Lofty
cac1bc6fbe
intel_alm: enable M10K initialisation
2023-05-25 18:56:34 +01:00
Lofty
00b0e850db
intel_alm: re-enable carry chains for ABC9
2023-05-25 18:28:10 +01:00
Miodrag Milanović
7aab324e85
Merge pull request #3737 from yrabbit/all-primitives-script
...
gowin: Add all the primitives.
2023-05-09 11:13:51 +02:00
Ralf Fuest
30f1d10948
gowin: Fix X output of $alu techmap
2023-05-01 17:56:41 +02:00
YRabbit
a1dd794ff8
gowin: Add all the primitives.
...
Use selected data (names, ports and parameters) from vendor file for
GW1N series primitives.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2023-04-22 17:10:53 +10:00
Miodrag Milanović
b377a39b73
Merge pull request #3727 from YosysHQ/micko/pll_bram
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MachXO2: Add PLL and EBR related primitives
2023-04-14 09:34:30 +02:00
gatecat
e56dad56c4
fabulous: Add support for LUT6s
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Signed-off-by: gatecat <gatecat@ds0.me>
2023-04-12 18:42:09 +02:00
YRabbit
f9a6c0fcbd
gowin: Add serialization/deserialization primitives
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Primitives are added to convert parallel signals to serial and vice versa.
IDES4, IDES8, IDES10, IDES16, IVIDEO, OSER4, OSER8, OSER10, OSER16, OVIDEO.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2023-04-12 09:59:57 +01:00
Miodrag Milanovic
ee3162c58d
Add PLL and EBR related primitives
2023-04-10 12:39:09 +02:00
gatecat
266f81816b
ecp5: Remove TRELLIS_SLICE and add TRELLIS_COMB model
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Signed-off-by: gatecat <gatecat@ds0.me>
2023-04-06 10:18:48 +01:00
Miodrag Milanovic
9e9fae1966
Add more DFF types
2023-04-06 09:10:14 +02:00
Miodrag Milanovic
d5a405d3b4
Added proper simulation model for CCU2D
2023-04-06 09:10:14 +02:00
Miodrag Milanovic
6e4c1675e7
Generate TRELLIS_DPR16X4 for lutram
2023-04-06 09:10:14 +02:00
Miodrag Milanovic
6e12da3956
machxo2: Initial support for carry chains (CCU2D)
2023-04-06 09:10:14 +02:00
Miodrag Milanovic
f35bdaa527
Update Xilinx cell definitions, fixes #3699
2023-03-23 09:44:36 +01:00
Miodrag Milanovic
ff9f1fb86e
Start unification effort for machxo2 and ecp5
2023-03-20 09:58:41 +01:00
Miodrag Milanovic
4d7e9e2e5d
Add additional iopad_external_pin attributes
2023-03-20 09:17:22 +01:00
Miodrag Milanovic
db367bd69e
Add iopad_external_pin to some basic io primitives
2023-03-20 09:17:22 +01:00
Miodrag Milanovic
10589c57bf
insert IO buffers for ECP5, off by default
2023-03-20 09:17:22 +01:00
Stefan Riesenberger
baa3659ea5
ice40: Fix path delay definitions
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Parallel connections do not allow matching different bit widths.
A full connection has to be used instead.
Allows iverilog to parse the simulation library with hardware path delays enabled.
2023-03-10 10:48:05 +01:00
N. Engelhardt
1a3ff0d926
Merge pull request #3688 from pu-cc/gatemate-reginit
2023-03-01 09:49:14 +01:00
Miodrag Milanović
bb28e48136
Merge pull request #3663 from uis246/master
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gowin: Add new types of oscillator
2023-02-28 06:56:01 +01:00
Miodrag Milanović
4ff9063145
Merge pull request #3652 from martell/elvds
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gowin: Add support for emulated differential output
2023-02-28 06:55:25 +01:00
gatecat
2ab3747cc9
fabulous: Add support for mapping carry chains
...
Signed-off-by: gatecat <gatecat@ds0.me>
2023-02-27 09:50:34 +01:00
Oliver Keszöcze
fc56978703
Check DREG attribute
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The DSP48E1 implementation checked the wrong attribute (i.e. CREG) to initialize the D input register. This PR fixes 3680
2023-02-17 17:54:41 +01:00
gatecat
25e7cb3bbb
fabulous: Add CLK to BRAM interface primitives
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Signed-off-by: gatecat <gatecat@ds0.me>
2023-02-16 12:55:53 +01:00
Patrick Urban
2c7ba0e752
gatemate: Enable register initialization
2023-02-15 17:29:01 +01:00
Patrick Urban
f37073050b
gatemate: Update CC_PLL parameters
2023-02-14 12:02:41 +01:00
Patrick Urban
6a7d5257cd
gatemate: Add CC_USR_RSTN primitive
2023-02-14 12:02:41 +01:00
Patrick Urban
4cb27b1a3a
gatemate: Ensure compatibility of LVDS ports with VHDL
2023-02-14 12:02:41 +01:00
uis
ea6f562d49
gowin: Add new types of oscillator
2023-02-06 21:34:32 +00:00
martell
dbc8b77222
gowin: Add support for emulated differential output
2023-01-29 20:48:43 -08:00
Miodrag Milanović
611f71c670
Merge pull request #3630 from yrabbit/gw1n4c-pll
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gowin: add a new type of PLL - PLLVR
2023-01-18 08:30:29 +01:00
Jannis Harder
5abaa59080
Merge pull request #3537 from jix/xprop
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New xprop pass
2023-01-11 16:26:04 +01:00
YRabbit
d6a1e022e1
gowin: add a new type of PLL - PLLVR
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This primitive is used in the GW1NS-4, GW1NS-4C, GW1NSR-4, GW1NSR-4C and
GW1NSER-4C chips.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2023-01-11 11:41:29 +10:00
gatecat
7bac1920b2
nexus: Fix BRAM write enable in PDP mode
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Signed-off-by: gatecat <gatecat@ds0.me>
2023-01-04 17:59:36 +01:00
Jannis Harder
7203ba7bc1
Add bitwise `$bweqx` and `$bwmux` cells
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The new bitwise case equality (`$bweqx`) and bitwise mux (`$bwmux`)
cells enable compact encoding and decoding of 3-valued logic signals
using multiple 2-valued signals.
2022-11-30 18:24:35 +01:00
Jannis Harder
99163fb822
simlib: Use optional SIMLIB_GLOBAL_CLOCK to define a global clock signal
2022-11-30 18:24:35 +01:00
Jannis Harder
605d127517
simlib: Silence iverilog warning for `$lut`
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iverilog complains about implicitly truncating LUT when connecting it to
the `$bmux` A input. This explicitly truncates it to avoid that warning
without changing the behaviour otherwise.
2022-11-30 18:24:35 +01:00
Jannis Harder
39ac113402
simlib: Fix wide $bmux and avoid iverilog warnings
2022-11-30 18:24:35 +01:00
Jannis Harder
b982ab4f59
satgen, simlib: Consistent x-propagation for `$pmux` cells
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This updates satgen and simlib to use a `$pmux` model where the output
is fully X when the S input is not all zero or one-hot with no x bits.
2022-11-30 18:24:35 +01:00
gatecat
b6467f0801
fabulous: Allow adding extra custom prims and map rules
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-11-17 13:34:58 +01:00
gatecat
f111bbdf40
fabulous: improvements to the pass
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-11-17 13:34:58 +01:00
gatecat
e3f9ff2679
fabulous: Unify and update primitives
...
Signed-off-by: gatecat <gatecat@ds0.me>
2022-11-17 13:34:58 +01:00
TaoBi22
12c22045b7
Introduce RegFile mappings
2022-11-17 13:34:58 +01:00
TaoBi22
2b07e01ea4
Replace synth call with components, reintroduce flags and correct vpr flag implementation
2022-11-17 13:34:58 +01:00
TaoBi22
df56178567
Reorder operations to load in primitive library before hierarchy pass
2022-11-17 13:34:58 +01:00
TaoBi22
da32f21b59
Add plib flag to specify custom primitive library path
2022-11-17 13:34:58 +01:00
TaoBi22
950dde3081
Remove flattening from FABulous pass
2022-11-17 13:34:58 +01:00
TaoBi22
8fdf4948a8
Remove ALL currently unused flags (some to be reintroduced later and passed through to synth)
2022-11-17 13:34:58 +01:00
TaoBi22
2e9480be24
Add synth_fabulous ScriptPass
2022-11-17 13:34:58 +01:00
Jannis Harder
aa7e7df19f
simlib: Simplify recently changed $mux model
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The use of a procedural continuous assignment introduced in #3526 was
unintended and is completely unnecessary for the actual change of that
PR.
2022-10-28 19:48:00 +02:00
Jannis Harder
408fc60c95
Merge pull request #3526 from jix/mux-simlib-eval
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Consistent $mux undef handling
2022-10-24 16:25:33 +02:00
Jannis Harder
c77b7343d0
Consistent $mux undef handling
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* Change simlib's $mux cell to use the ternary operator as $_MUX_
already does
* Stop opt_expr -keepdc from changing S=x to S=0
* Change const eval of $mux and $pmux to match the updated simlib
(fixes sim)
* The sat behavior of $mux already matches the updated simlib
The verilog frontend uses $mux for the ternary operators and this
changes all interpreations of the $mux cell (that I found) to match the
verilog simulation behavior for the ternary operator. For 'if' and
'case' expressions the frontend may also use $mux but uses $eqx if the
verilog simulation behavior is requested with the '-ifx' option.
For $pmux there is a remaining mismatch between the sat behavior and the
simlib behavior. Resolving this requires more discussion, as the $pmux
cell does not directly correspond to a specific verilog construct.
2022-10-24 12:03:01 +02:00
Jannis Harder
0f96ae5990
Add smtmap.v describing the smt2 backend's behavior for undef bits
...
Some builtin cells have an undefined (x) output even when all inputs are
defined. This is not natively supported by the formal backends which
will produce a fully defined value instead. This can lead to issues when
combining different backends in a formal flow. To work around these,
this adds a file containing verilog implementation of cells matching the
fully defined behavior implemented by the smt2 backend.
2022-10-20 15:48:18 +02:00
Miodrag Milanovic
1ecf6aee9b
Test fixes for latest iverilog
2022-09-21 15:46:43 +02:00
Tristan Gingold
1e0e3bd48e
sf2: add NOTES about using yosys for smartfusion2 and igloo2
2022-08-31 08:40:44 +02:00
Tristan Gingold
0f6cf8b8e4
sf2: add a test for $alu gate
2022-08-31 08:40:44 +02:00
Tristan Gingold
c25f3ff3df
sf2: suport $alu gate and ARI1 implementation
2022-08-31 08:40:44 +02:00
Tristan Gingold
13ccdd032d
synth_sf2: purge on last clean
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LiberoSoc don't like unused nets.
2022-08-31 08:40:44 +02:00
Tristan Gingold
39993a92d7
sf2/cells_sim.v: add XTLOSC, SYSRESET cells
2022-08-31 08:40:44 +02:00
Tristan Gingold
1c0119aa90
sf2/cells_sim.v: add IOSTD parameter to I/O cells
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This parameter is set by LiberoSoc IPs, so it is needed to avoid
errors when using those IPs.
2022-08-31 08:40:43 +02:00
Tristan Gingold
4543751a77
synth_sf2: add -discard-ffinit option to discard ff initial value
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sf2 ff have no initial values, but some IP cores use initial values.
In order to use those cores on sf2, it is required to discard the
initial value (to be carefully used).
2022-08-31 08:40:43 +02:00
KrystalDelusion
9465b2af95
Fitting help messages to 80 character width
...
Uses the regex below to search (using vscode):
^\t\tlog\("(.{10,}(?<!\\n)|.{81,}\\n)"\);
Finds any log messages double indented (which help messages are)
and checks if *either* there are is no newline character at the end,
*or* the number of characters before the newline is more than 80.
2022-08-24 10:40:57 +12:00
Jannis Harder
c0063288d6
Add the $anyinit cell and the formalff pass
...
These can be used to protect undefined flip-flop initialization values
from optimizations that are not sound for formal verification and can
help mapping all solver-provided values in witness traces for flows that
use different backends simultaneously.
2022-08-16 13:37:30 +02:00
Sean Anderson
8c05f14b58
Order ports with default assignments first
...
Although the current style is allowed by the standard, Icarus verilog
doesn't parse default assignments using an implicit net type:
techlibs/ice40/cells_sim.v:305: syntax error
techlibs/ice40/cells_sim.v:1: Errors in port declarations.
Fix this by making sure that ports with default assignments first on
their line.
Fixes: 46d3f03d2
("Add default assignments to other SB_* simulation models")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-09 23:42:24 -04:00
Marcelina Kościelnicka
8fab6ec023
nexus: Fix BRAM mapping.
2022-08-09 23:47:55 +02:00
Miodrag Milanović
86a4ba1758
Merge pull request #3397 from pepijndevos/patch-2
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Apicula now supports lutram
2022-07-06 09:50:52 +02:00
Miodrag Milanovic
4db820e9d4
Fix static initialization, fixes mingw build
2022-07-04 19:31:38 +02:00
Pepijn de Vos
de07eb11c1
Apicula now supports lutram
2022-07-03 12:45:03 +02:00
gatecat
38a24ec5cc
gatemate: Add LUT tree library script
...
Co-authored-by: Claire Xenia Wolf <claire@clairexen.net>
Signed-off-by: gatecat <gatecat@ds0.me>
2022-06-27 10:09:48 +01:00
gatecat
7c756c9959
gatemate: Add preliminary sim models for LUT tree structures
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-06-27 10:09:48 +01:00
Marcelina Kościelnicka
71dfbf33b2
Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}.
2022-06-02 23:16:12 +02:00
Patrick Urban
5d08688054
gatemate: Fix minor issues with `memory_libmap` ( #3343 )
2022-05-27 23:35:26 +02:00
Marcelina Kościelnicka
2a2dc12eb6
gatemate: Use `memory_libmap` pass.
2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
2dcb0797f0
machxo2: Use `memory_libmap` pass.
2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
9d11575856
efinix: Use `memory_libmap` pass.
2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
f4d1426229
anlogic: Use `memory_libmap` pass.
2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
d7dc2313b9
ice40: Use `memory_libmap` pass.
2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
3b2f95953c
xilinx: Use `memory_libmap` pass.
2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
e4d811561c
gowin: Use `memory_libmap` pass.
2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
0a8eaca322
nexus: Use `memory_libmap` pass.
2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
a04b025abf
ecp5: Use `memory_libmap` pass.
2022-05-18 17:32:56 +02:00
Rick Luiken
414dc25a96
Add missing parameters for ecp5
2022-04-25 15:31:41 +01:00
Tim Pambor
30bc0d26ea
gowin: Add oscillator primitives
2022-03-28 13:33:24 +02:00
Marcelina Kościelnicka
be9595e18f
xilinx: Add RAMB4* blackboxes
2022-03-21 13:11:52 +01:00
YRabbit
19b7633aca
gowin: add support for Double Data Rate primitives
...
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-03-14 23:14:21 +01:00
Lofty
9f7a55c99f
intel_alm: M10K write-enable is negative-true
2022-03-09 20:18:06 +00:00
YRabbit
22d9bbb308
gowin: Remove unnecessary attributes
...
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-02-24 05:38:33 +01:00
YRabbit
9b3cd4f0d8
gowin: Add support for true differential output
...
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-02-24 05:38:33 +01:00
Marcelina Kościelnicka
d0f4d0b153
ecp5: Do not use specify in generate in cells_sim.v.
2022-02-21 17:52:31 +01:00
Marcelina Kościelnicka
3a62fa0c97
gowin: Add remaining block RAM blackboxes.
2022-02-12 11:48:57 +01:00
Marcelina Kościelnicka
f61f2a4078
gowin: Fix LUT RAM inference, add more models.
2022-02-09 09:04:34 +01:00
Marcelina Kościelnicka
ac2bb70b52
ecp5: Fix DPR16X4 sim model.
2022-02-09 09:02:13 +01:00
Marcelina Kościelnicka
958c3a46ad
nexus: Fix arith_map CO signal.
...
Fixes #3187 .
2022-02-06 13:05:30 +01:00
Xing GUO
0520e99968
Fix the help message of synth_quicklogic.
2022-01-31 02:23:59 +08:00
Marcelina Kościelnicka
93508d58da
Add $bmux and $demux cells.
2022-01-28 23:34:41 +01:00
gatecat
f699c4ba58
nexus: Fix BB sim model
...
Signed-off-by: gatecat <gatecat@ds0.me>
2022-01-19 18:14:24 +00:00
Miodrag Milanovic
36482680d5
Removed dbits 8 since 9 will always be picked
2022-01-19 08:51:25 +01:00
Miodrag Milanović
4525e419f6
Merge pull request #3120 from Icenowy/anlogic-bram
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anlogic: support BRAM mapping
2022-01-19 08:49:58 +01:00
Lofty
d015c2b48a
intel_alm: disable 256x40 M10K mode
...
This BRAM mode uses both address ports, making it effectively single-port.
Since memory_bram can't presently map to single-port memories, remove it.
2021-12-22 00:42:33 +01:00
Icenowy Zheng
c2b7ad3b28
anlogic: support BRAM mapping
...
Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being
true dual port (or 18bit*512 when simple dual port), the other is
16bit*2K.
Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and
32Kbit BRAM with 8bit width are not support yet.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2021-12-17 20:28:22 +08:00
Lofty
a31c8a82be
intel_alm: preliminary Arria V support
2021-11-25 17:20:36 +01:00
Patrick Urban
cb41209095
synth_gatemate Revert cascade A/B port mixup
2021-11-13 21:53:25 +01:00
Patrick Urban
decdc743db
synth_gatemate: Remove iob_map invokation
2021-11-13 21:53:25 +01:00
Patrick Urban
0d871b6c49
synth_gatemate: Add block RAM cascade support
...
* add simulation model for block RAM cascade in 40K mode
* limit 20K_SDP and 40K_SDP to 40 and 80 bits (the only useful configurations)
2021-11-13 21:53:25 +01:00
Patrick Urban
285ec0547b
synth_gatemate: Remove obsolete iob_map
2021-11-13 21:53:25 +01:00
Patrick Urban
81964d6d6f
synth_gatemate: Update pass
...
* remove `write_edif` and `write_blif` options
* remove redundant `abc` call before muxcover
* update style
2021-11-13 21:53:25 +01:00
Patrick Urban
74aee88e81
synth_gatemate: Remove specify blocks
2021-11-13 21:53:25 +01:00
Patrick Urban
05f24adca9
synth_gatemate: Remove gatemate_bramopt pass
2021-11-13 21:53:25 +01:00
Patrick Urban
4bee908ae8
synth_gatemate: Revise block RAM read modes and initialization
...
* enable mixed read-width / write-width ports in SDP mode
* fix NO_CHANGE and WRITE_THROUGH behavior during read access
* remove redundant zero-initialization
* set A/B_WE bit during map (gatemate_bramopt pass could be removed later)
* differentiate "upper" and "lower" initialization for cascade mode
2021-11-13 21:53:25 +01:00
Patrick Urban
3f4ccdf2f5
synth_gatemate: Remove unsupported FF initialization
2021-11-13 21:53:25 +01:00
Patrick Urban
d592bd93b8
synth_gatemate: Rename multiplier factor parameters
2021-11-13 21:53:25 +01:00
Patrick Urban
6825de6343
synth_gatemate: Registers are uninitialized
2021-11-13 21:53:25 +01:00
Patrick Urban
0a72952d5f
synth_gatemate: Apply review remarks
...
* remove unused techmap models in `map_regs.v`
* replace RAM initilization loops with 320-bit-writes
* add script to test targets in top-level Makefile
* remove `MAXWIDTH` parameter and treat both vector widths individually in `mult_map.v`
* iterate over all modules in `gatemate_bramopt` pass
2021-11-13 21:53:25 +01:00
Patrick Urban
cfcc38582a
synth_gatemate: Apply review remarks
2021-11-13 21:53:25 +01:00
Patrick Urban
240d289fff
synth_gatemate: Initial implementation
...
Signed-off-by: Patrick Urban <patrick.urban@web.de>
2021-11-13 21:53:25 +01:00
Marcelina Kościelnicka
15b0d717ed
iopadmap: Add native support for negative-polarity output enable.
2021-11-09 15:40:16 +01:00
Pepijn de Vos
4bf8deacbb
synth_gowin: move splitnets to after iopadmap ( #2435 )
2021-11-07 18:00:18 +01:00
Pepijn de Vos
a3eec687e0
Remove noalu from synth_gowin json output as Apicula now supports it
2021-11-07 03:04:21 +01:00
Pepijn de Vos
0c7461fe5e
gowin: widelut support ( #3042 )
2021-11-06 16:09:30 +01:00
Marcelina Kościelnicka
e14302a3ea
ecp5: Add support for mapping aldff.
2021-10-27 16:18:05 +02:00
Claire Xenia Wolf
fe9689c136
Fixed Verific parser error in ice40 cell library
...
non-net output port 'Q' cannot be initialized at declaration in SystemVerilog mode
2021-10-19 12:33:18 +02:00
Olivier Galibert
6e78a80ff9
CycloneV: Add (passthrough) support for cyclonev_oscillator
2021-10-17 20:00:03 +02:00
Olivier Galibert
6253d4ec9e
CycloneV: Add (passthrough) support for cyclonev_hps_interface_mpu_general_purpose
2021-10-17 10:39:13 +02:00
Marcelina Kościelnicka
e7d89e653c
Hook up $aldff support in various passes.
2021-10-02 21:01:21 +02:00
Marcelina Kościelnicka
ec2b5548fe
Add $aldff and $aldffe: flip-flops with async load.
2021-10-02 18:12:52 +02:00
Eddie Hung
f03e2c30aa
abc9: replace cell type/parameters if derived type already processed ( #2991 )
...
* Add close bracket
* Add testcase
* Replace cell type/param if in unmap_design
* Improve abc9_box error message too
* Update comment as per review
2021-09-09 10:05:55 -07:00
kittennbfive
6de500ec08
[ECP5] fix wrong link for syn_* attributes description ( #2984 )
2021-08-29 11:45:23 +02:00
ECP5-PCIe
dfc453b246
Add DLLDELD
2021-08-22 18:48:44 +02:00
Pepijn de Vos
c2d358484f
Gowin: deal with active-low tristate ( #2971 )
...
* deal with active-low tristate
* remove empty port
* update sim models
* add expected lut1 to tests
2021-08-20 21:21:06 +02:00
Sylvain Munaut
3806b07303
ice40: Fix typo in SB_CARRY specify for LP/UltraPlus
...
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2021-08-17 14:33:30 +02:00
Marcelina Kościelnicka
fd79217763
Add v2 memory cells.
2021-08-11 13:34:10 +02:00
Maciej Dudek
cfddef5d7d
Fixes xc7 BRAM36s
...
UG473 from Xilinx states that 15 bit should always be set if RAMB isn't in cascade mode.
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
2021-07-30 16:17:22 +02:00
Marcelina Kościelnicka
54e75129e5
opt_lut: Allow more than one -dlogic per cell type.
...
Fixes #2061 .
2021-07-29 17:30:07 +02:00
Marcelina Kościelnicka
19720b970d
memory: Introduce $meminit_v2 cell, with EN input.
2021-07-28 23:18:38 +02:00
Marcelina Kościelnicka
726fabd65e
ice40: Fix LUT input indices in opt_lut -dlogic (again).
...
Fixes #2061 .
2021-07-10 21:30:01 +02:00
gatecat
2b8f1633ce
ecp5: Add DCSC blackbox
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-06 14:07:20 +01:00
Claire Xenia Wolf
06b99950ed
Fix icestorm links
...
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-06-09 12:39:12 +02:00
Claire Xenia Wolf
0ada13cbe2
Use HTTPS for website links, gatecat email
...
git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g ;
2021-06-09 12:16:56 +02:00
Claire Xenia Wolf
92e705cb51
Fix files with CRLF line endings
2021-06-09 12:16:33 +02:00
Claire Xenia Wolf
72787f52fc
Fixing old e-mail addresses and deadnames
...
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g ;
2021-06-08 00:39:36 +02:00
gatecat
34a08750fa
intel_alm: Fix illegal carry chains
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 22:37:06 +01:00
gatecat
eb106732d9
intel_alm: Add global buffer insertion
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 22:37:06 +01:00
gatecat
5dba138c87
intel_alm: Add IO buffer insertion
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 22:37:06 +01:00
Adam Greig
9e02786d39
Add missing parameters for MULT18X18D and ALU54B to ECP5 techlib.
2021-05-12 10:04:34 +01:00
Michael Christensen
67d6f3973b
Fix use of blif name in synth_xilinx command
2021-04-27 02:29:52 -07:00
Claire Xenia Wolf
46d3f03d27
Add default assignments to other SB_* simulation models
...
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-04-20 18:52:36 +02:00
Claire Xenia Wolf
8aee80040d
Add default assignments to SB_LUT4
...
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-04-20 12:46:21 +02:00
Lofty
dce037a62c
quicklogic: ABC9 synthesis
2021-04-17 20:54:58 +02:00
Stefan Riesenberger
a58571d0fe
sf2: fix name of AND modules
2021-04-09 16:46:05 +02:00
Eddie Hung
55dc5a4e4f
abc9: fix SCC issues ( #2694 )
...
* xilinx: add SCC test for DSP48E1
* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1
Have a test that checks it works through ABC9 when enabled
* abc9 to break SCCs using $__ABC9_SCC_BREAKER module
* Add test
* abc9_ops: remove refs to (* abc9_keep *) on wires
* abc9_ops: do not bypass cells in an SCC
* Add myself to CODEOWNERS for abc9*
* Fix compile
* abc9_ops: run -prep_hier before scc
* Fix tests
* Remove bug reference pending fix
* abc9: fix for -prep_hier -dff
* xaiger: restore PI handling
* abc9_ops: -prep_xaiger sigmap
* abc9_ops: -mark_scc -> -break_scc
* abc9: eliminate hard-coded abc9.box from tests
Also tidy up
* Address review
2021-03-29 22:01:57 -07:00
Lofty
f4298b057a
quicklogic: PolarPro 3 support
...
Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com>
Co-authored-by: Maciej Kurc <mkurc@antmicro.com>
Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com>
Co-authored-by: Lalit Sharma <lsharma@quicklogic.com>
Co-authored-by: kkumar23 <kkumar@quicklogic.com>
2021-03-18 13:28:16 +01:00
gatecat
cae905f551
Blackbox all whiteboxes after synthesis
...
This prevents issues like processes in whiteboxes triggering an error in
the JSON backend.
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-17 21:07:20 +00:00
Marcelina Kościelnicka
a3528649c8
memory_dff: Remove now-useless write port handling.
2021-03-08 20:16:29 +01:00
Marcelina Kościelnicka
cde73428b0
Fix syntax error in adff2dff.v
...
Fixes #2600 .
2021-02-24 01:07:34 +01:00
William D. Jones
ae07298a6b
machxo2: Switch to LUT4 sim model which propagates less undefined/don't care values.
2021-02-23 17:39:58 +01:00
William D. Jones
8f1a350f5e
machxo2: Add experimental status to help.
2021-02-23 17:39:58 +01:00
William D. Jones
e3974809ec
machxo2: Add DCCA and DCMA blackbox primitives.
2021-02-23 17:39:58 +01:00
William D. Jones
a1ea1430b6
machxo2: Fix reversed interpretation of REG_SD config bits.
2021-02-23 17:39:58 +01:00
William D. Jones
4e9def23de
machxo2: Tristate is active-low.
2021-02-23 17:39:58 +01:00
William D. Jones
8b14152506
machxo2: Fix typos in FACADE_FF sim model.
2021-02-23 17:39:58 +01:00
William D. Jones
8348c45e4f
machxo2: Fix naming of TRELLIS_IO ports to match PIO pins in routing graph.
2021-02-23 17:39:58 +01:00
William D. Jones
120404bfda
machxo2: Improve help_mode output in synth_machxo2.
2021-02-23 17:39:58 +01:00
William D. Jones
3674eb34d4
machxo2: Use attrmvcp pass to move LOC and src attributes from ports/wires to IO cells.
2021-02-23 17:39:58 +01:00
William D. Jones
124780ecd9
machxo2: Add missing OSCH oscillator primitive.
2021-02-23 17:39:58 +01:00
William D. Jones
597a54dbd0
machxo2: Add -noiopad option to synth_machxo2.
2021-02-23 17:39:58 +01:00
William D. Jones
3697f351d5
machxo2: Use correct INITVAL for LUT1 in FACADE_SLICE.
2021-02-23 17:39:58 +01:00
William D. Jones
f07b8eb606
machxo2: Fix cells_sim typo where OFX1 was multiply-driven.
2021-02-23 17:39:58 +01:00
William D. Jones
c76f361b56
machxo2: synth_machxo2 now maps ports to FACADE_IO.
2021-02-23 17:39:58 +01:00
William D. Jones
03cbf1327d
machxo2: Add initial value for Q in FACADE_FF.
2021-02-23 17:39:58 +01:00
William D. Jones
0364ded385
machxo2: Add FACADE_IO simulation model. More comments on models.
2021-02-23 17:39:58 +01:00
William D. Jones
1b703d3f03
machxo2: Add FACADE_SLICE simulation model.
2021-02-23 17:39:58 +01:00
William D. Jones
cc52eb53cd
machxo2: Improve FACADE_FF simulation model.
2021-02-23 17:39:58 +01:00
William D. Jones
427fed23ee
machxo2: Improve LUT4 techmap. Use same output port name for LUT4 as Lattice.
2021-02-23 17:39:58 +01:00
William D. Jones
84937e9689
machxo2: Add dff.ys test, fix another cells_map.v typo.
2021-02-23 17:39:58 +01:00
William D. Jones
044393b990
machxo2: Fix more oversights in machxo2 models. logic.ys test passes.
2021-02-23 17:39:58 +01:00
William D. Jones
b87f6a0906
machxo2: Fix typos. test/arch/run-test.sh passes.
2021-02-23 17:39:58 +01:00
William D. Jones
88c8f81260
machxo2: Create basic techlibs and synth_machxo2 pass.
2021-02-23 17:39:58 +01:00
gatecat
9f7cd10c98
Merge pull request #2585 from YosysHQ/dave/nexus-dotproduct
...
nexus: Add MULTADDSUB9X9WIDE sim model
2021-02-12 12:07:12 +00:00
Zachary Snow
fe74b0cd95
verilog: significant block scoping improvements
...
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-31 09:42:09 -05:00
Marcelina Kościelnicka
ea79e16bab
xilinx_dffopt: Don't crash on missing IS_*_INVERTED.
...
The presence of IS_*_INVERTED on FD* cells follows Vivado, which
apparently has been decided by a dice roll. Just assume false if the
parameter doesn't exist.
Fixes #2559 .
2021-01-27 00:32:00 +01:00
Marcelina Kościelnicka
cd6f0732f3
xilinx: Add FDRSE_1, FDCPE_1.
2021-01-27 00:32:00 +01:00
Tom Verbeure
87637e8359
Fix some trivial typos.
2021-01-03 23:52:59 -08:00
whitequark
b0d4c63957
Merge pull request #2480 from YosysHQ/dave/nexus-lram
...
nexus: Add LRAM inference
2021-01-01 09:49:00 +00:00
Marcelina Kościelnicka
f2932628fc
xilinx: Add some missing blackbox cells.
2020-12-21 05:34:26 +01:00
Marcelina Kościelnicka
5ffb676fa9
xilinx: Regenerate cells_xtra.v using Vivado 2020.2
2020-12-21 05:34:26 +01:00
Marcelina Kościelnicka
871fc34ad4
xilinx: Add FDDRCPE and FDDRRSE blackbox cells.
...
These are necessary primitives for proper DDR support on Virtex 2 and
Spartan 3.
2020-12-17 03:25:07 +01:00
David Shah
f5cc1224f9
nexus: Add MULTADDSUB9X9WIDE sim model
...
Signed-off-by: David Shah <dave@ds0.me>
2020-12-08 15:49:20 +00:00
David Shah
17812a1560
nexus: Add LRAM inference
...
Signed-off-by: David Shah <dave@ds0.me>
2020-12-07 13:27:17 +00:00
David Shah
264e924abb
nexus: More efficient CO mapping
...
Signed-off-by: David Shah <dave@ds0.me>
2020-12-02 17:08:39 +00:00
Pepijn de Vos
f155826a70
add -noalu and -json option for apicula
2020-11-30 11:43:12 +01:00
David Shah
9f241c9a42
nexus: DSP inference support
...
Signed-off-by: David Shah <dave@ds0.me>
2020-11-20 08:45:55 +00:00
Miodrag Milanović
c8d809897f
Merge pull request #2441 from YosysHQ/dave/nexus_dsp_sim
...
nexus: Add DSP simulation model
2020-11-18 12:22:05 +01:00
David Shah
923843b3fa
nexus: Add DSP simulation model
...
Signed-off-by: David Shah <dave@ds0.me>
2020-11-18 10:21:17 +00:00
Miodrag Milanovic
aa4d94f7d8
Fix duplicated parameter name typo
2020-11-18 10:03:57 +01:00
Konrad Beckmann
5b9a975eba
synth_gowin: Add rPLL blackbox
2020-11-11 17:06:54 +01:00
David Shah
6d63e58e46
nexus: Add make_transp to BRAMs
...
Signed-off-by: David Shah <dave@ds0.me>
2020-10-22 15:11:59 +01:00
clairexen
e919d0c125
Merge pull request #2405 from byuccl/fix_xilinx_cells
...
xilinx/cells_sim.v: Move signal declaration to before first use
2020-10-20 17:11:36 +02:00
Jeff Goeders
8be56960a2
Move signal declarations to before first use
...
Signed-off-by: Jeff Goeders <jeff.goeders@gmail.com>
2020-10-19 16:09:18 -06:00
David Shah
4d584d9319
synth_nexus: Initial implementation
...
Signed-off-by: David Shah <dave@ds0.me>
2020-10-15 08:52:15 +01:00
Eddie Hung
de79978372
xilinx: do not make DSP48E1 a whitebox for ABC9 by default ( #2325 )
...
* xilinx: eliminate SCCs from DSP48E1 model
* xilinx: add SCC test for DSP48E1
* Update techlibs/xilinx/cells_sim.v
* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1
Have a test that checks it works through ABC9 when enabled
2020-09-23 09:15:24 -07:00
Dan Ravensloft
028f96e536
intel_alm: better map wide but shallow multiplies
2020-08-28 23:44:16 +02:00
Dan Ravensloft
1a07b330f8
intel_alm: Add multiply signedness to cells
...
Quartus assumes unsigned multiplication by default, breaking signed
multiplies, so add an input signedness parameter to the MISTRAL_MUL*
cells to propagate to Quartus' <family>_mac cells.
2020-08-26 22:50:16 +02:00
Marcelina Kościelnicka
082cbcb4c7
synth_intel: Remove incomplete Arria 10 GX support.
...
The techmap rules for this target do not work in the first place (note
lack of >2-input LUT mappings), and if proper support is ever added,
it'd be better placed in the synth_intel_alm backend.
2020-08-21 01:46:06 +02:00
Dan Ravensloft
034b9ec716
intel: move Cyclone V support to intel_alm
2020-08-20 18:25:05 +02:00
clairexen
d9dd8bc748
Merge pull request #2347 from YosysHQ/mwk/techmap-shift-fixes
...
techmap/shift_shiftx: Remove the "shiftx2mux" special path.
2020-08-20 16:25:56 +02:00
clairexen
1cdb533fa5
Merge pull request #2319 from YosysHQ/mwk/techmap-celltype-pattern
...
techmap: Add support for [] wildcards in techmap_celltype.
2020-08-20 16:18:40 +02:00
Marcelina Kościelnicka
50d532f01c
techmap/shift_shiftx: Remove the "shiftx2mux" special path.
...
Our techmap rules for $shift and $shiftx cells contained a special path
that aimed to decompose the shift LSB-first instead of MSB-first in
select cases that come up in pmux lowering. This path was needlessly
overcomplicated and contained bugs.
Instead of doing that, just switch over the main path to iterate
LSB-first (except for the specially-handled MSB for signed shifts
and overflow handling). This also makes the code consistent with
shl/shr/sshl/sshr cells, which are already decomposed LSB-first.
Fixes #2346 .
2020-08-20 12:44:09 +02:00
Xiretza
928fd40c2e
Respect \A_SIGNED for $shift
...
This reflects the behaviour of $shr/$shl, which sign-extend their A
operands to the size of their output, then do a logical shift (shift in
0-bits).
2020-08-18 19:36:24 +02:00
Dan Ravensloft
3b534a203a
intel_alm: fix typo in MISTRAL_MUL27X27 cell name
2020-08-13 17:08:50 +02:00
Dan Ravensloft
97daf612cb
intel_alm: add more megafunctions. NFC.
2020-08-12 18:39:22 +02:00
Marcelina Kościelnicka
9a4f420b4b
Replace opt_rmdff with opt_dff.
2020-08-07 13:21:03 +02:00
Marcelina Kościelnicka
522788f016
techmap: Add support for [] wildcards in techmap_celltype.
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Fixes #1826 .
2020-08-02 22:46:48 +02:00
Marcelina Kościelnicka
6cd135a5eb
opt_expr: Remove -clkinv option, make it the default.
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Adds -noclkinv option just in case the old behavior was actually useful
to someone.
2020-07-31 00:08:15 +02:00
Marcelina Kościelnicka
cf60699884
synth_ice40: Use opt_dff.
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The main part is converting ice40_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the mux patterns on
its own.
The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.
2020-07-30 22:26:20 +02:00
Marcelina Kościelnicka
8501342fc5
synth_xilinx: Use opt_dff.
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The main part is converting xilinx_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the patterns on its
own.
The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.
2020-07-30 22:26:09 +02:00
Dan Ravensloft
a2fb84fd0c
intel_alm: direct M10K instantiation
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This reverts commit a3a90f6377
.
2020-07-27 15:39:06 +02:00
Dan Ravensloft
62311b7ec0
intel_alm: increase abc9 -W
2020-07-26 23:56:54 +02:00
clairexen
02583ad504
Merge pull request #2294 from Ravenslofty/intel_alm_timings
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intel_alm: add additional ABC9 timings
2020-07-23 18:21:20 +02:00
Dan Ravensloft
4d9d90079c
intel_alm: add additional ABC9 timings
2020-07-23 11:57:07 +01:00
Keith Rothman
819f1d8c20
Remove EXPLICIT_CARRY logic.
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The symbiflow-arch-defs tool chain no longer needs the EXPLICIT_CARRY
within yosys itself.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2020-07-23 00:56:09 +02:00
Marcelina Kościelnicka
1b95b0e570
sf2: Emit CLKINT even if -clkbuf not passed
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This restores pre #2229 behavior.
2020-07-17 15:01:47 +02:00