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1230 Commits

Author SHA1 Message Date
Tobias Faller 760a2c1343 Fixed missing goto statement in passes/techmap/abc.cc 2021-01-12 16:17:51 +01:00
Zachary Snow 0d8e5d965f Sign extend port connections where necessary 
- Signed cell outputs are sign extended when bound to larger wires
- Signed connections are sign extended when bound to larger cell inputs
- Sign extension is performed in hierarchy and flatten phases
- genrtlil indirects signed constants through signed wires
- Other phases producing RTLIL may need to be updated to preserve
  signedness information
- Resolves #1418
- Resolves #2265
 2020-12-18 20:33:14 -07:00
Miodrag Milanovic 829b5cca60 Expose abc and data paths as globals 2020-11-06 14:17:15 +01:00
Ethan Mahintorabi 5c36e7757c This patch adds support for defining the ABC location at runtime instead of at compile time. This is helpful in build systems like bazel which do not have stable locations for binaries or directories during the compilation phase. 
This change should be backwards compatible with the existing behavior.
 2020-10-28 19:00:06 -07:00
whitequark 2d10d59d93
Merge pull request #2356 from whitequark/flatten-techmap-no-tpl_driven-sigmap 
flatten, techmap: don't canonicalize tpl driven bits via sigmap
 2020-08-27 11:28:31 +00:00
whitequark 702f7c0253
Merge pull request #2358 from whitequark/rename-ilang-to-rtlil 
Replace "ILANG" with "RTLIL" everywhere
 2020-08-27 11:24:06 +00:00
Marcelina Kościelnicka 880df4c897 dfflegalize: Fix decision tree for adffe. 
When an adffe is being legalized, and is not natively supported,
prioritize unmapping to adff over converting to dffsre if dffsre is not
natively supported itself.

Fixes #2361.
 2020-08-27 13:17:42 +02:00
whitequark 00e7dec7f5 Replace "ILANG" with "RTLIL" everywhere. 
The only difference between "RTLIL" and "ILANG" is that the latter is
the text representation of the former, as opposed to the in-memory
graph representation. This distinction serves no purpose but confuses
people: it is not obvious that the ILANG backend writes RTLIL graphs.

Passes `write_ilang` and `read_ilang` are provided as aliases to
`write_rtlil` and `read_rtlil` for compatibility.
 2020-08-26 17:29:32 +00:00
whitequark 9f0892159e flatten, techmap: don't canonicalize tpl driven bits via sigmap. 
For connection `assign a = b;`, `sigmap(a)` returns `b`. This is
exactly the opposite of the desired canonicalization for driven bits.
Consider the following code:

    module foo(inout a, b);
      assign a = b;
    endmodule
    module bar(output c);
      foo f(c, 1'b0);
    endmodule

Before this commit, the inout ports would be swapped after flattening
(and cause a crash while attempting to drive a constant value).

This issue was introduced in 9f772eb9.

Fixes #2183.
 2020-08-26 16:29:42 +00:00
clairexen 6a68b8ed54
Merge pull request #2328 from YosysHQ/mwk/opt_dff-cleanup 
Remove passes redundant with opt_dff
 2020-08-20 16:21:58 +02:00
clairexen faf8e19511
Merge pull request #2327 from YosysHQ/mwk/techmap-constmap-fix 
techmap.CONSTMAP: Handle outputs before inputs.
 2020-08-20 16:21:09 +02:00
clairexen 1cdb533fa5
Merge pull request #2319 from YosysHQ/mwk/techmap-celltype-pattern 
techmap: Add support for [] wildcards in techmap_celltype.
 2020-08-20 16:18:40 +02:00
Marcelina Kościelnicka 54a0c083a1 Remove now-redundant dff2dffe pass. 2020-08-07 13:21:34 +02:00
Marcelina Kościelnicka 5693386a4e Remove now-redundant dff2dffs pass. 2020-08-07 13:21:34 +02:00
Marcelina Kościelnicka 9a4f420b4b Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00
Marcelina Kościelnicka b4a4cb081d techmap.CONSTMAP: Handle outputs before inputs. 
Fixes #2321.
 2020-08-05 12:28:18 +02:00
Marcelina Kościelnicka 522788f016 techmap: Add support for [] wildcards in techmap_celltype. 
Fixes #1826.
 2020-08-02 22:46:48 +02:00
Marcelina Kościelnicka 18ad56ef41 Add dffunmap pass. 
To be used with backends that cannot deal with fancy FF types (like blif
or smt).
 2020-07-31 00:59:51 +02:00
Marcelina Kościelnicka 7b1a4fc1e6 techmap: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka 9e72be3ae8 shregmap: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka 522f367db3 abc: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka 336b8c7786 dffinit: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka 1c8483b7dd zinit: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka e98382f6e2 dfflegalize: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka dc07ae9677 techmap: Add _TECHMAP_CELLNAME_ special parameter. 
This parameter will resolve to the name of the cell being mapped.  The
first user of this parameter will be synth_intel_alm's Quartus output,
which requires a unique (and preferably descriptive) name passed as
a cell parameter for the memory cells.
 2020-07-21 15:00:54 +02:00
Marcelina Kościelnicka 240351c44e dfflegalize: Gather init values from all wires. 
Skipping non-selected wires is unsound in an obvious way.
 2020-07-12 17:39:13 +02:00
Marcelina Kościelnicka 7ed9d18907 dfflibmap: Refactor to use dfflegalize internally. 2020-07-09 18:51:03 +02:00
Marcelina Kościelnicka 32d2cc8c28 clkbufmap: improve input pad handling. 
- allow inserting only the input pad cell
- do not insert the usual buffer if the input pad already acts as a
  buffer
 2020-07-09 18:48:01 +02:00
Marcelina Kościelnicka e9c2c1b717 dfflegalize: Add special support for const-D latches. 
Those can be created by `opt_dff` when optimizing `$adff` with const
clock, or with D == Q.  Make dfflegalize do the opposite transform
when such dlatches would be otherwise unimplementable.
 2020-07-09 18:11:32 +02:00
Marcelina Kościelnicka 943147b768 dfflegalize: typo fix 2020-07-07 15:00:52 +02:00
Marcelina Kościelnicka af54b8bc61 Naming fixes. 2020-07-05 22:21:59 +02:00
Marcelina Kościelnicka f3f55ae7c2 dfflegalize: Prefer mapping dff to sdff before adff 
This ensures that, when both sync and async FFs are available and abc9
is involved, the sync FFs will be used, and will thus remain available
for sequential synthesis.
 2020-07-05 12:01:43 +02:00
Eddie Hung 27a9d1b6e6 abc9: only techmap (* abc9_flop *) modules 2020-07-04 19:45:10 +02:00
Eddie Hung 0ba79feb6f abc9: techmap from user design to allow abc9_flop modules to be composed 
from other primitives
 2020-07-04 19:45:10 +02:00
Rupert Swarbrick a9b61080a4 Add newlines to help text for dfflegalize 
I think these were probably missed by accident. Spotted because GCC
spits out lots of messages like this:

passes/techmap/dfflegalize.cc:114:7: warning: zero-length gnu_printf format string [-Wformat-zero-length]
  114 |   log("");
      |       ^~

(because we tell GCC that the first argument to log() looks like a
printf control string in log.h, and a zero length such string triggers
a warning).
 2020-07-03 12:30:12 +02:00
Marcelina Kościelnicka e3564b4502 Add dfflegalize pass. 2020-07-01 01:57:15 +02:00
whitequark a97c13f0ca techmap: don't drop attributes on replaced cells. 
This was introduced in 76c4ee4ea5.

Fixes #2204.
 2020-06-29 23:14:13 +00:00
clairexen c7d71f436d
Merge pull request #2168 from whitequark/assert-unused-exprs 
Use (and ignore) the expression provided to log_assert in NDEBUG builds
 2020-06-25 18:21:51 +02:00
Marcelina Kościelnicka 8f12c5b063 simplemap: Fix $dffsre mapping. 2020-06-23 23:16:43 +02:00
Marcelina Kościelnicka 88e7f90663 Update dff2dffe, dff2dffs, zinit to new FF types. 2020-06-23 18:24:53 +02:00
Marcelina Kościelnicka 832acc8648 Add new FF types to simplemap. 2020-06-23 15:40:02 +02:00
whitequark 118e4caa37 Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug(). 2020-06-19 15:48:58 +00:00
whitequark 7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
Anonymous Maarten 60fb9cabcf msvc does not support designated initializers in structs 2020-06-17 16:20:52 +02:00
whitequark 98e1080345 flatten: accept processes. 2020-06-09 09:56:23 +00:00
whitequark fbb346ea91 flatten: preserve original object names via hdlname attribute. 2020-06-08 20:19:41 +00:00
whitequark 8d821dbbdb flatten: only prepend $flatten once per wire. 2020-06-08 20:19:41 +00:00
whitequark a1814b732f flatten: make hygienic. 
Before this commit, `flatten` matched the template objects with
the newly created objects solely by their name. Because of this,
it could be confused by code such as:

    module bar();
      $dff a();
    endmodule

    module foo();
      bar b();
      $dff \b.a ();
    endmodule

After this commit, `flatten` avoids every possible case of name
collision.

Fixes #2106.
 2020-06-08 19:30:21 +00:00
clairexen fbd0d8d5f0
Merge pull request #2105 from whitequark/split-flatten-off-techmap 
Split `flatten` from `techmap` and simplify it
 2020-06-08 15:27:15 +02:00
Eddie Hung 69850204c4
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve 
abc9: -dff improvements
 2020-06-04 08:15:25 -07:00
whitequark 5a5a9b4ffe flatten: clean up log messages. 2020-06-04 12:22:59 +00:00
whitequark d731fe054b flatten: topologically sort modules. 2020-06-04 12:22:59 +00:00
Eddie Hung 45cd323055
Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixes 
abc9: fixes around handling combinatorial loops
 2020-06-03 17:35:46 -07:00
whitequark 6268bdfe6f flatten: simplify. 
`flatten` cannot derive modules in most cases because that would just
yield processes, and it does not support `-autoproc`; in practice
`flatten` has to be preceded by a call to `hierarchy`, which makes
deriving unnecessary.
 2020-06-04 00:02:12 +00:00
whitequark d3e2100306 flatten: simplify. NFC. 
Remove redundant sigmaps.
 2020-06-04 00:02:12 +00:00
whitequark 66255dab4e flatten: simplify. 
Flattening does not benefit from topologically sorting cells within
a module when processing them.
 2020-06-04 00:02:12 +00:00
whitequark 5d2b6d1394 flatten: simplify. NFC. 
Flatten is non-recursive and doesn't need to keep track of handled
cells.
 2020-06-04 00:02:12 +00:00
whitequark 3c3fa774e5 flatten: simplify. NFC. 
Flattening always does "non-recursive" mapping.
 2020-06-04 00:02:12 +00:00
whitequark e561a3a76f flatten: simplify. NFC. 
The `celltypeMap` always maps `x` to `{x}`.
 2020-06-04 00:02:12 +00:00
whitequark 6783876807 flatten: simplify. NFC. 
The `design` and `map` designs are always the same when flattening.
 2020-06-04 00:02:12 +00:00
whitequark 9338ff66b9 RTLIL: factor out RTLIL::Module::addMemory. NFC. 2020-06-04 00:02:12 +00:00
whitequark ebbbe2156e flatten: rename techmap-related stuff. NFC. 2020-06-04 00:02:12 +00:00
whitequark 76c4ee4ea5 techmap, flatten: remove dead options. 
After splitting the passes, some options can never be activated,
and most conditions involving them become dead. Remove them, and also
all of the newly dead code.
 2020-06-04 00:02:12 +00:00
whitequark 6ac54a74fe flatten: split from techmap. 
Although the two passes started out very similar, they diverged over
time and now have little in common. Moreover, `techmap` is extremely
complex while `flatten` does not have to be, and this complexity
interferes with improving `flatten`.
 2020-06-03 15:34:03 +00:00
whitequark fb5b070e7e techmap: remove dead variable. NFC. 2020-06-03 01:44:06 +00:00
whitequark 0a74368bfc techmap: use C++11 default member initializers. NFC. 2020-06-02 23:43:20 +00:00
whitequark f3e86bb32a techmap: simplify. 
`rewrite_filename` is already called in `Frontend::extra_args`.
 2020-06-02 23:43:20 +00:00
whitequark 68d747f767 techmap: use +/techmap.v instead of an ad-hoc code generator. 2020-06-02 23:43:20 +00:00
clairexen ff785cdb46
Merge pull request #1862 from boqwxp/cleanup_techmap 
Clean up `passes/techmap/techmap.cc`
 2020-05-31 20:40:48 +02:00
Eddie Hung 08d9703ecb abc9_ops: fix comment 2020-05-30 09:01:03 -07:00
Eddie Hung ea4374a223 abc9_ops: update messaging (credit to @Xiretza for spotting) 2020-05-30 08:57:48 -07:00
Eddie Hung b17e8495b8 abc9_ops: optimise to not derive unless attribute exists 2020-05-29 17:33:10 -07:00
Eddie Hung d3b53bc495 abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_ 2020-05-29 17:17:40 -07:00
Eddie Hung 00c5ceb1f2 abc9_ops: -prep_xaiger exclude (* abc9_keep *) wires from toposort 2020-05-25 16:40:53 -07:00
Eddie Hung 7bad23f19c abc9_ops: -reintegrate to preserve flop names 2020-05-25 08:43:33 -07:00
Eddie Hung 4f0f321169 abc9_ops: update comment 2020-05-21 21:39:13 -07:00
Eddie Hung 67fc0c3698 abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_ 
instead of moving them to $__ prefix
 2020-05-14 16:44:35 -07:00
Alberto Gonzalez e173291649
techmap: Replace naughty `const_cast<>()`s. 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-05-14 20:06:55 +00:00
Alberto Gonzalez 97fd304cbe
techmap: Replace pseudo-private member usage with the range accessor function and some naughty `const_cast<>()`s. 2020-05-14 20:06:55 +00:00
Eddie Hung 36bb201dd9
techmap: sort celltypeMap as it determines techmap order 2020-05-14 20:06:55 +00:00
Alberto Gonzalez ce62d0751a
Replace `std::set`s using custom comparators with `pool`. 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-05-14 20:06:55 +00:00
Eddie Hung dabeb1e8a1
techmap: prefix special wires with backslash for use as IdString 2020-05-14 20:06:55 +00:00
Alberto Gonzalez bd54d67ad4
Further clean up `passes/techmap/techmap.cc`. 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-05-14 20:06:54 +00:00
Alberto Gonzalez 982562ff13
Use `emplace()` for more efficient insertion into various `dict`s. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez c658d9d59d
Build constant bits directly rather than constructing an object and copying its bits. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez f235f212ea
Replace `std::set` with `pool` for `cell_to_inbit` and `outbit_to_cell`. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez 6294621825
Use `emplace()` rather than `insert()`. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez dfcb936cd5
Clean up pseudo-private member usage and ensure range iteration uses references where possible to avoid unnecessary copies. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez a4755c50c3
Clean up extraneous buffer. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez 7857782575
Replace `std::map` with `dict` for `unique_bit_id`. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez 6d64d768b0
Replace `std::map` with `dict` for `port_new2old_map`, `port_connmap`, and `cellbits_to_tplbits`. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez 5cb4ae4666
Replace `std::map` with `dict` for `connbits_map`, `cell_to_inbit`, and `outbit_to_cell`. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez c43017fc08
Replace `std::map` with `dict` for `TechmapWires` type. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez 644e55b3d3
Replace `std::map` with `dict` for `celltypeMap`. 2020-05-14 20:06:53 +00:00
Alberto Gonzalez 67f4046c05
Replace `std::set` with `pool` for `handled_cells` and `techmap_wire_names`. 2020-05-14 20:06:53 +00:00
Alberto Gonzalez 64c16f8c13
Replace `std::map` with `dict` for `positional_ports`. 2020-05-14 20:06:53 +00:00
Alberto Gonzalez 2fb4931e5b
Add specialized `hash()` for type `dict` and use a `dict` instead of a `std::map` for `techmap_cache` and `techmap_do_cache`. 2020-05-14 20:06:53 +00:00
Alberto Gonzalez 437f3fb342
Replace `std::map` with `dict` for `simplemap_mappers`. 2020-05-14 20:06:53 +00:00
Alberto Gonzalez 99b586b283
Use `nullptr` instead of `NULL` in `passes/techmap/techmap.cc`. 2020-05-14 20:06:53 +00:00
Alberto Gonzalez 5f7f213c7f
Replace `std::string` and `RTLIL::IdString` with `IdString` in `passes/techmap/techmap.cc`. 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-05-14 20:06:53 +00:00