Clifford Wolf
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129984e115
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Fix handling of Verilog ~& and ~| operators
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2017-06-01 12:43:21 +02:00 |
Clifford Wolf
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e91548b33e
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Add support for localparam in module header
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2017-04-30 17:20:30 +02:00 |
Clifford Wolf
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5b3b5ffc8c
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Allow $anyconst, etc. in non-formal SV mode
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2017-03-01 10:47:05 +01:00 |
Clifford Wolf
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5f1d0b1024
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Add $live and $fair cell types, add support for s_eventually keyword
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2017-02-25 10:36:39 +01:00 |
Clifford Wolf
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00dba4c197
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Add support for SystemVerilog unique, unique0, and priority case
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2017-02-23 16:33:19 +01:00 |
Clifford Wolf
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34d4e72132
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Added SystemVerilog support for ++ and --
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2017-02-23 11:21:33 +01:00 |
Clifford Wolf
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848062088c
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Add checker support to verilog front-end
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2017-02-09 13:51:44 +01:00 |
Clifford Wolf
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ef4a28e112
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Add SV "rand" and "const rand" support
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2017-02-08 14:38:15 +01:00 |
Clifford Wolf
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6abf79eb28
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Further improve cover() support
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2017-02-04 17:02:13 +01:00 |
Clifford Wolf
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3928482a3c
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Add $cover cell type and SVA cover() support
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2017-02-04 14:14:26 +01:00 |
Clifford Wolf
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fea528280b
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Add "enum" and "typedef" lexer support
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2017-01-17 17:33:52 +01:00 |
Clifford Wolf
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70d7a02cae
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Added support for hierarchical defparams
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2016-11-15 13:35:19 +01:00 |
Clifford Wolf
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bdc316db50
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Added $anyseq cell type
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2016-10-14 15:24:03 +02:00 |
Clifford Wolf
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6f41e5277d
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Removed $aconst cell type
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2016-08-30 19:09:56 +02:00 |
Clifford Wolf
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eae390ae17
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Removed $predict again
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2016-08-28 21:35:33 +02:00 |
Clifford Wolf
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1276c87a56
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Added read_verilog -norestrict -assume-asserts
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2016-08-26 23:35:27 +02:00 |
Clifford Wolf
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4be4969bae
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Improved verilog parser errors
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2016-08-25 11:44:37 +02:00 |
Clifford Wolf
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7f755dec75
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Fixed bug in parsing real constants
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2016-08-06 13:16:23 +02:00 |
Clifford Wolf
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4056312987
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Added $anyconst and $aconst
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2016-07-27 15:41:22 +02:00 |
Clifford Wolf
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5b944ef11b
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Fixed a verilog parser memory leak
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2016-07-25 16:37:58 +02:00 |
Clifford Wolf
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7a67add95d
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Fixed parsing of empty positional cell ports
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2016-07-25 12:48:03 +02:00 |
Clifford Wolf
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9aae1d1e8f
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No tristate warning message for "read_verilog -lib"
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2016-07-23 11:56:53 +02:00 |
Clifford Wolf
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5c166e76e5
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Added $initstate cell type and vlog function
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2016-07-21 14:23:22 +02:00 |
Clifford Wolf
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d7763634b6
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After reading the SV spec, using non-standard predict() instead of expect()
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2016-07-21 13:34:33 +02:00 |
Clifford Wolf
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721f1f5ecf
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Added basic support for $expect cells
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2016-07-13 16:56:17 +02:00 |
Ruben Undheim
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545bcb37e8
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Allow defining input ports as "input logic" in SystemVerilog
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2016-06-20 20:16:37 +02:00 |
Ruben Undheim
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178ff3e7f6
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Added support for SystemVerilog packages with localparam definitions
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2016-06-18 10:53:55 +02:00 |
Clifford Wolf
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5a09fa4553
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Fixed handling of parameters and const functions in casex/casez pattern
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2016-04-21 15:31:54 +02:00 |
Clifford Wolf
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33c10350b2
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Fixed Verilog parser fix and more similar improvements
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2016-03-15 12:22:31 +01:00 |
Andrew Becker
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81d4e9e7c1
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Use left-recursive rule for cell_port_list in Verilog parser.
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2016-03-15 12:03:40 +01:00 |
Clifford Wolf
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34f2b84fb6
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Fixed handling of parameters and localparams in functions
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2015-11-11 10:54:35 +01:00 |
Clifford Wolf
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5308c1e02a
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Fixed bug in verilog parser
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2015-10-15 15:19:23 +02:00 |
Clifford Wolf
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ba4cce9f19
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Added support for "parameter" and "localparam" in global context
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2015-10-07 14:59:08 +02:00 |
Clifford Wolf
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a3a13cce32
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Fixed detection of "task foo(bar);" syntax error
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2015-09-22 21:34:21 +02:00 |
Clifford Wolf
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e4ef000b70
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Adjust makefiles to work with out-of-tree builds
This is based on work done by Larry Doolittle
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2015-08-12 15:04:44 +02:00 |
Clifford Wolf
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6c84341f22
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Fixed trailing whitespaces
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2015-07-02 11:14:30 +02:00 |
Clifford Wolf
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1f1deda888
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Added non-std verilog assume() statement
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2015-02-26 18:47:39 +01:00 |
Clifford Wolf
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dc1a0f06fc
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Parser support for complex delay expressions
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2015-02-20 10:21:36 +01:00 |
Clifford Wolf
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e0e6d130cd
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YosysJS stuff
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2015-02-19 13:36:54 +01:00 |
Clifford Wolf
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4f68a77e3f
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Improved read_verilog support for empty behavioral statements
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2015-02-10 12:17:29 +01:00 |
Clifford Wolf
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1282a113da
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Fixed supply0/supply1 with many wires
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2014-12-11 13:56:20 +01:00 |
Clifford Wolf
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87333f3ae2
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Added warning for use of 'z' constants in HDL
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2014-11-14 19:59:50 +01:00 |
Clifford Wolf
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4e5350b409
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Fixed parsing of nested verilog concatenation and replicate
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2014-11-12 19:10:35 +01:00 |
Clifford Wolf
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a21481b338
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Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..."
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2014-10-30 14:01:02 +01:00 |
Clifford Wolf
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f9c096eeda
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Added support for task and function args in parentheses
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2014-10-27 13:21:57 +01:00 |
William Speirs
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fad0b0c506
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Updated lexers & parsers to include prefixes
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2014-10-15 00:48:19 +02:00 |