Miodrag Milanovic
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3ebfa3fb84
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Make sure cell names are unique for wide operators
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2021-12-03 09:49:05 +01:00 |
Miodrag Milanovic
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15a35f5584
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No need to alocate more memory than used
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2021-11-10 10:50:44 +01:00 |
Claire Xenia Wolf
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2ea757da51
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Add "verific -cfg" command
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
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2021-11-01 10:41:51 +01:00 |
Claire Xenia Wolf
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83118bfb9e
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Fix verific gclk handling for async-load FFs
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
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2021-10-31 17:12:29 +01:00 |
Miodrag Milanovic
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f7cc388bb5
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Enable async load dff emit by default in Verific
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2021-10-27 15:56:56 +02:00 |
Miodrag Milanovic
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32673edfea
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Revert "Compile option for enabling async load verific support"
This reverts commit b8624ad2ae .
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2021-10-27 15:55:43 +02:00 |
Miodrag Milanovic
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b8624ad2ae
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Compile option for enabling async load verific support
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2021-10-25 09:04:43 +02:00 |
Claire Xenia Wolf
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90b440f870
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Fix verific.cc PRIM_DLATCH handling
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
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2021-10-21 12:13:35 +02:00 |
Claire Xenia Wolf
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16a177560f
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Initial Verific impoter support for {PRIM,WIDE_OPER}_DLATCH{,RS}
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
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2021-10-21 05:42:47 +02:00 |
Miodrag Milanovic
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17269ae59b
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Option to disable verific VHDL support
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2021-10-20 10:02:58 +02:00 |
Miodrag Milanovic
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1aa6896966
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Support PRIM_BUFIF1 primitive
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2021-10-14 13:04:32 +02:00 |
Claire Xen
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2d3c79458d
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Merge pull request #3039 from YosysHQ/claire/verific_aldff
Add support for $aldff flip-flops to verific importer
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2021-10-11 10:01:56 +02:00 |
Claire Xenia Wolf
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c8074769b0
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Add Verific adffe/dffsre/aldffe FIXMEs
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
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2021-10-11 10:00:20 +02:00 |
Miodrag Milanovic
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93fbc9fba4
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Import module attributes from Verific
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2021-10-10 10:01:45 +02:00 |
Claire Xenia Wolf
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34f1df8435
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Fixes and add comments for open FIXME items
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
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2021-10-08 17:24:45 +02:00 |
Claire Xenia Wolf
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1602a03864
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Add support for $aldff flip-flops to verific importer
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
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2021-10-08 16:21:25 +02:00 |
Miodrag Milanovic
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abc5700628
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verific set db_infer_set_reset_registers
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2021-10-04 16:48:33 +02:00 |
Miodrag Milanovic
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c3d4bb4cc9
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update required verific version
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2021-09-02 14:59:16 +02:00 |
Miodrag Milanovic
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b59c427348
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Make Verific extensions optional
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2021-08-20 10:19:04 +02:00 |
Miodrag Milanovic
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be04d8834e
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Require latest verific
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2021-08-02 10:29:58 +02:00 |
Miodrag Milanovic
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987fca5297
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Update to latest verific
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2021-07-21 09:46:53 +02:00 |
Miodrag Milanovic
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7a5ac90985
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Update to latest Verific with extensions for initial assertions
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2021-07-09 09:02:27 +02:00 |
Miodrag Milanovic
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0dbb05a75e
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Add additional help
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2021-07-05 09:16:54 +02:00 |
Miodrag Milanovic
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c0d8da20d5
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Support command files in Verific
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2021-06-16 11:21:44 +02:00 |
Claire Xenia Wolf
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72787f52fc
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Fixing old e-mail addresses and deadnames
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
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2021-06-08 00:39:36 +02:00 |
Claire Xen
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6c56c083f8
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Update README
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2021-03-04 16:43:30 +01:00 |
Claire Xen
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27d7741540
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Merge pull request #2574 from dh73/master
Accept disable case for SVA liveness properties.
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2021-02-15 17:49:11 +01:00 |
Miodrag Milanovic
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13c2fd7137
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Ganulate Verific support
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2021-02-12 10:08:43 +01:00 |
Diego H
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c96eb2fbd7
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Accept disable case for SVA liveness properties.
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2021-02-04 15:35:35 -06:00 |
Miodrag Milanovic
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d99c032c27
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Require latest Verific build
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2021-01-30 09:23:46 +01:00 |
Claire Xenia Wolf
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acad7a6e40
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Switch verific bindings from Symbiotic EDA flavored Verific to YosysHQ flavored Verific
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
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2021-01-20 20:48:10 +01:00 |
Miodrag Milanovic
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1c4a18f66f
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Bump required Verific version
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2020-12-02 15:18:04 +01:00 |
Miodrag Milanovic
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c228cb74d6
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Update verific version
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2020-10-30 08:32:59 +01:00 |
Miodrag Milanovic
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c8f052bbe0
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extend verific library API for formal apps and generators
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2020-10-12 14:56:15 +02:00 |
Miodrag Milanović
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1b7ed719a5
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Update required Verific version
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2020-10-05 13:27:27 +02:00 |
Miodrag Milanovic
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a44c5df259
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use sha1 for parameter list in case if they contain spaces
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2020-09-30 09:16:59 +02:00 |
Miodrag Milanovic
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44705102b5
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Better error for unsupported SVA sequence
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2020-09-18 17:08:00 +02:00 |
Miodrag Milanovic
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3f27a4ea68
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Use latest verific
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2020-09-02 10:22:25 +02:00 |
Miodrag Milanovic
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04d5692a85
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Reorder to prevent crash
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2020-08-31 12:22:26 +02:00 |
Miodrag Milanovic
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3af499c60f
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ast recognize lower case x and z and verific gives upper case
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2020-08-30 13:33:03 +02:00 |
Miodrag Milanovic
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2f93579bd1
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Do not check for 1 and 0 only
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2020-08-30 13:15:06 +02:00 |
Miodrag Milanovic
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b1e3bc059c
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Fix import of VHDL enums
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2020-08-30 12:25:23 +02:00 |
Miodrag Milanovic
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fe8226a22d
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Add formal apps and template generators
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2020-08-26 10:39:57 +02:00 |
Miodrag Milanovic
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cc02d58194
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Clear last error message
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2020-07-29 15:28:33 +02:00 |
clairexen
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3d8d98d709
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Merge pull request #2132 from YosysHQ/eddie/verific_initial
verific: rewrite initial assume/asserts prior to elaboration
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2020-07-02 17:50:22 +02:00 |
Miodrag Milanovic
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561890c4e8
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Update verific API version check
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2020-06-30 12:13:13 +02:00 |
Miodrag Milanovic
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b822beb1b2
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Fix crash in verific frontend
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2020-06-26 20:11:01 +02:00 |
clairexen
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c7d71f436d
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Merge pull request #2168 from whitequark/assert-unused-exprs
Use (and ignore) the expression provided to log_assert in NDEBUG builds
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2020-06-25 18:21:51 +02:00 |
Miodrag Milanovic
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4aec50a863
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optimization, all items should have same attributes
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2020-06-25 09:18:53 +02:00 |
Miodrag Milanovic
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f993d18755
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verific - import attributes for net buses as well
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2020-06-24 11:01:06 +02:00 |