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11969 Commits

Author SHA1 Message Date
KrystalDelusion 9465b2af95 Fitting help messages to 80 character width 
Uses the regex below to search (using vscode):
	^\t\tlog\("(.{10,}(?<!\\n)|.{81,}\\n)"\);

Finds any log messages double indented (which help messages are)
and checks if *either* there are is no newline character at the end,
*or* the number of characters before the newline is more than 80.
 2022-08-24 10:40:57 +12:00
Aki Van Ness 1433a63165
yosys: passes: cmds: show: added filename re-writing to `show -lib` 2022-08-22 06:04:54 -04:00
Archie 15a0697c70 Adding check for BLIF names command input plane size. 2022-08-21 23:18:20 -05:00
Archie db73f3c26b Merge branch 'master' of https://github.com/ALGCDG/yosys 2022-08-21 17:18:20 -05:00
github-actions[bot] 029c2785e8 Bump version 2022-08-19 00:19:27 +00:00
Jannis Harder f1c9399b66
Merge pull request #3450 from jix/write_aiger_nonff 
write_aiger: Fix non-$_FF_ FFs
 2022-08-18 16:50:56 +02:00
Jannis Harder 5142fb3b5c write_aiger: Fix non-$_FF_ FFs 
This broke while switching sby's formal flows to always use $_FF_'s.
 2022-08-18 13:56:22 +02:00
github-actions[bot] 1c36f4cc2c Bump version 2022-08-17 00:18:21 +00:00
Jannis Harder 556d008ed3
Merge pull request #3434 from jix/witness_flow 
Updated formal flow with new witness format
 2022-08-16 14:18:35 +02:00
Jannis Harder f7023d06a2 sim: -hdlname option to preserve flattened hierarchy in sim output 2022-08-16 13:37:30 +02:00
Jannis Harder 66f761a8c5 smtbmc: Set step range for --yw and dont skip steps for --check-witness 2022-08-16 13:37:30 +02:00
Jannis Harder 927af914f1 Update CEX minimization patches for abc 2022-08-16 13:37:30 +02:00
Jannis Harder 4ad13c647e clk2fflogic: Generate less unused logic when using verific 
Verific generates a lot of FFs with an unused async load and we cannot
always optimize that away before running clk2fflogic, so check for that
special case here.
 2022-08-16 13:37:30 +02:00
Jannis Harder 65145db7e7 rename: Add -witness mode 2022-08-16 13:37:30 +02:00
Jannis Harder b156fe903f yosys-witness: Add stats command 2022-08-16 13:37:30 +02:00
Jannis Harder 475267ac25 smtbmc: Add --check-witness mode 
This verifies that the given constraints force an assertion failure.
This is useful to debug witness trace conversion (and minimization).
 2022-08-16 13:37:30 +02:00
Jannis Harder efd5b86eb9 aiger: Add yosys-witness support 
Adds a new json based aiger map file and yosys-witness converters to us
this to convert between native and AIGER witness files.
 2022-08-16 13:37:30 +02:00
Jannis Harder f041e36c6e smtbmc: Add native json based witness format + smt2 backend support 
This adds a native json based witness trace format. By having a common
format that includes everything we support, and providing a conversion
utility (yosys-witness) we no longer need to implement every format for
every tool that deals with witness traces, avoiding a quadratic
opportunity to introduce subtle bugs.

Included:

  * smt2: New yosys-smt2-witness info lines containing full hierarchical
    paths without lossy escaping.
  * yosys-smtbmc --dump-yw trace.yw: Dump results in the new format.
  * yosys-smtbmc --yw trace.yw: Read new format as constraints.
  * yosys-witness: New tool to convert witness formats.
    Currently this can only display traces in a human-readable-only
    format and do a passthrough read/write of the new format.
  * ywio.py: Small python lib for reading and writing the new format.
    Used by yosys-smtbmc and yosys-witness to avoid duplication.
 2022-08-16 13:37:30 +02:00
Jannis Harder 96a1173598 btor: Support $anyinit cells 2022-08-16 13:37:30 +02:00
Jannis Harder 5893cae647 aiger: Support $anyinit cells 2022-08-16 13:37:30 +02:00
Jannis Harder 021c3c8da5 smt2: Support $anyinit cells 2022-08-16 13:37:30 +02:00
Jannis Harder a2f9ebe43a memory_map: Add -formal option 
This maps memories for a global clock based formal verification flow.
This implies -keepdc, uses $ff cells for ROMs and sets hdlname
attributes.
 2022-08-16 13:37:30 +02:00
Jannis Harder 0cdb14df41 setundef: Do not add anyseq / anyconst to unused memory port clocks 
Instead set those unused clocks to zero.
 2022-08-16 13:37:30 +02:00
Jannis Harder 428ad5b9fd wreduce: Keep more x-bits with -keepdc 2022-08-16 13:37:30 +02:00
Jannis Harder 95db5a9d38 formalff: New -setundef option 
Find FFs with undefined initialization values for which changing the
initialization does not change the observable behavior and initialize
them. For -ff2anyinit, this reduces the number of generated $anyinit
cells that drive wires with private names.
 2022-08-16 13:37:30 +02:00
Jannis Harder a5e1d3b997 formalff: Set new replaced_by_gclk attribute on removed dff's clks 
This attribute can be used by formal backends to indicate which clocks
were mapped to the global clock. Update the btor and smt2 backend which
already handle clock inputs to understand this attribute.
 2022-08-16 13:37:30 +02:00
Jannis Harder c0063288d6 Add the $anyinit cell and the formalff pass 
These can be used to protect undefined flip-flop initialization values
from optimizations that are not sound for formal verification and can
help mapping all solver-provided values in witness traces for flows that
use different backends simultaneously.
 2022-08-16 13:37:30 +02:00
github-actions[bot] c26b2bf543 Bump version 2022-08-12 00:16:29 +00:00
N. Engelhardt 6f439dc59a
Merge pull request #3425 from YosysHQ/lofty/stat-json 2022-08-11 17:00:54 +02:00
Lofty 59facfa98c stat: add option for machine-readable json output 2022-08-11 13:41:01 +01:00
N. Engelhardt 63fca0dbc2
Merge pull request #3277 from YosysHQ/lofty/rename-scramble_name 2022-08-11 12:06:04 +02:00
github-actions[bot] 91010449ff Bump version 2022-08-11 00:19:11 +00:00
Miodrag Milanović 0b0e01e211
Merge pull request #3443 from YosysHQ/micko/resetall_undefineall 
resetall does not affect text defines, but undefineall does
 2022-08-10 14:37:36 +02:00
Miodrag Milanovic b76c72056b set default_nettype to wire for resetall 2022-08-10 13:28:19 +02:00
Miodrag Milanovic 545a3417c8 resetall does not affect text defines, but undefineall does 2022-08-10 11:38:50 +02:00
N. Engelhardt 51f67e55f2
Merge pull request #3322 from Forty-Bot/default_assignment_first 2022-08-10 09:16:32 +02:00
Sean Anderson 8c05f14b58 Order ports with default assignments first 
Although the current style is allowed by the standard, Icarus verilog
doesn't parse default assignments using an implicit net type:

	techlibs/ice40/cells_sim.v:305: syntax error
	techlibs/ice40/cells_sim.v:1: Errors in port declarations.

Fix this by making sure that ports with default assignments first on
their line.

Fixes: 46d3f03d2 ("Add default assignments to other SB_* simulation models")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
 2022-08-09 23:42:24 -04:00
github-actions[bot] 035d99f3a8 Bump version 2022-08-10 00:16:23 +00:00
Marcelina Kościelnicka 8fab6ec023 nexus: Fix BRAM mapping. 2022-08-09 23:47:55 +02:00
Miodrag Milanović 594cfd1d4d
Merge pull request #3441 from YosysHQ/micko/smtio-utf-8 
Switched to utf-8 in smtio.py
 2022-08-09 15:12:15 +02:00
Miodrag Milanovic 4444d5cf68 Switched to utf-8 in smtio.py 2022-08-09 12:54:48 +02:00
Miodrag Milanovic 99f1c71582 properly encode string in rtlil 2022-08-09 12:45:32 +02:00
github-actions[bot] d2b4246a6d Bump version 2022-08-09 00:19:53 +00:00
Miodrag Milanović 6b4dbf6c36
Merge pull request #3439 from YosysHQ/micko/filepath_improve 
File path encoding improvements
 2022-08-08 21:11:34 +02:00
Miodrag Milanovic f4a1906721 support file locations containing spaces 2022-08-08 20:30:50 +02:00
Lofty a48dcd1d40 rename: add -scramble-name option to randomly rename selections 2022-08-08 16:03:28 +01:00
Miodrag Milanovic 6c65ca4e50 Encode filename unprintable chars 2022-08-08 16:13:33 +02:00
Miodrag Milanovic 2b1aeb44d9 verific - make filepath handling compatible with verilog frontend 2022-08-08 11:57:28 +02:00
github-actions[bot] 60a787fa50 Bump version 2022-08-04 00:18:16 +00:00
Miodrag Milanovic 733902c81e Next dev cycle 2022-08-03 13:57:14 +02:00