Clifford Wolf
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479be3cec7
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Fix handling of x-bits in EDIF back-end
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2017-07-11 17:38:19 +02:00 |
Clifford Wolf
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9557fd2a36
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Add attributes and parameter support to JSON front-end
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2017-07-10 13:17:38 +02:00 |
Clifford Wolf
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8a69759306
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Add techlibs/xilinx/lut2lut.v
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2017-07-10 12:09:05 +02:00 |
Clifford Wolf
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4b2d1fe688
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Add JSON front-end
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2017-07-08 16:40:40 +02:00 |
Clifford Wolf
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3c693b6561
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Change s/asserts/assertions/ in yosys-smtbmc log messages
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2017-07-07 11:52:25 +02:00 |
Clifford Wolf
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8f7404f82c
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Add "yosys-smtbmc --presat"
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2017-07-07 02:47:30 +02:00 |
Clifford Wolf
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5442554e6f
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Fix generation of multiple outputs for same AIG node in write_aiger
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2017-07-05 14:23:54 +02:00 |
Clifford Wolf
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37af6294bd
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Add write_table command
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2017-07-05 12:13:53 +02:00 |
Clifford Wolf
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28039c3063
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Add Verific Release information to log
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2017-07-04 20:01:30 +02:00 |
Clifford Wolf
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621787a9e0
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Fix some c++ clang compiler errors
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2017-07-03 19:38:30 +02:00 |
Clifford Wolf
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5c1c126374
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Apply minor coding style changes to coolrunner2 target
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2017-07-03 19:35:40 +02:00 |
Clifford Wolf
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6afee022ad
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Merge pull request #352 from rqou/master
Initial Coolrunner-II support
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2017-07-03 19:33:36 +02:00 |
Clifford Wolf
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3f863c607a
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Merge pull request #356 from set-soft/clean-test
Added the test outputs to the clean target
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2017-07-03 19:33:25 +02:00 |
Clifford Wolf
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d223292aa9
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Merge pull request #355 from set-soft/exclude_TBUF_merge
Excluded $_TBUF_ from opt_merge pass
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2017-07-03 19:31:59 +02:00 |
Salvador E. Tropea
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fb30511044
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Added the test outputs to the clean target
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2017-07-03 13:33:11 -03:00 |
Salvador E. Tropea
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ca23554528
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Excluded $_TBUF_ from opt_merge pass
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2017-07-03 13:21:20 -03:00 |
Clifford Wolf
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3e0948e16f
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Remove unneeded delays in smtbmc vlogtb
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2017-07-03 15:37:17 +02:00 |
Clifford Wolf
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287831dca3
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Include output ports with constant driver in AIGER output
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2017-07-03 14:53:17 +02:00 |
Clifford Wolf
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ea805af6f5
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Add "yosys-smtbmc --vlogtb-top"
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2017-07-01 18:19:23 +02:00 |
Clifford Wolf
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0a02cdb93b
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Fix and_or_buffer optimization in opt_expr for signed operators
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2017-07-01 16:05:26 +02:00 |
Clifford Wolf
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7d2fb6e2fc
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Fix smtbmc vlogtb bug in $anyseq handling
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2017-07-01 02:13:32 +02:00 |
Clifford Wolf
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0f217080cf
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Add "design -import"
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2017-06-30 19:18:52 +02:00 |
Clifford Wolf
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8952bd6f45
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Add chtype command
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2017-06-30 17:57:34 +02:00 |
Clifford Wolf
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18c030a8c9
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Add $tribuf to opt_merge blacklist
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2017-06-30 17:44:44 +02:00 |
Clifford Wolf
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5b95901a1e
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Merge pull request #353 from azonenberg/master
greenpak4_counters: Use more human-readable names for inferred counters
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2017-06-27 19:18:32 +02:00 |
Robert Ou
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b102c0e254
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coolrunner2: Add a few more primitives
These cannot be inferred yet, but add them to cells_sim.v for now
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2017-06-25 23:58:28 -07:00 |
Robert Ou
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36b75dfcb7
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coolrunner2: Initial mapping of latches
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2017-06-25 23:58:28 -07:00 |
Robert Ou
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4af5baab21
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coolrunner2: Initial mapping of DFFs
All DFFs map to either FDCP (matches Xilinx) or a custom FDCP_N
(negative-edge triggered)
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2017-06-25 23:58:28 -07:00 |
Robert Ou
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1eb5dee799
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coolrunner2: Remove redundant INVERT_PTC
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2017-06-25 23:58:28 -07:00 |
Robert Ou
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ffff001008
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coolrunner2: Remove debug prints
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2017-06-25 23:58:28 -07:00 |
Robert Ou
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5798105d47
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coolrunner2: Correctly handle $_NOT_ after $sop
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2017-06-25 23:58:28 -07:00 |
Robert Ou
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908ce3fdce
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coolrunner2: Also construct the XOR cell in the macrocell
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2017-06-25 23:58:28 -07:00 |
Robert Ou
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a64b56648d
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coolrunner2: Initial techmapping for $sop
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2017-06-25 23:58:22 -07:00 |
Andrew Zonenberg
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cbdddc3af9
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greenpak4_counters: Changed generation of primitive names so that the absorbed register's name is included
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2017-06-24 14:54:07 -07:00 |
Robert Ou
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6e0fb889fa
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coolrunner2: Initial commit
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2017-06-24 07:22:56 -07:00 |
Clifford Wolf
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155a80dfb7
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Fix handling of init values in "abc -dff" and "abc -clk"
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2017-06-20 15:32:23 +02:00 |
Clifford Wolf
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1f517d2b96
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Fix history namespace collision
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2017-06-20 05:26:12 +02:00 |
Clifford Wolf
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c0ca99483c
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Store command history when terminating with an error
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2017-06-20 04:41:58 +02:00 |
Clifford Wolf
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f6421c83a2
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Switched abc "clock domain not found" error to log_cmd_error()
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2017-06-20 04:22:34 +02:00 |
Clifford Wolf
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8f8baccfde
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Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand const reg"
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2017-06-07 12:30:24 +02:00 |
Clifford Wolf
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129984e115
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Fix handling of Verilog ~& and ~| operators
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2017-06-01 12:43:21 +02:00 |
Clifford Wolf
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0290b68a44
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Update ABC to hg rev efbf7f13ea9e
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2017-05-31 11:55:37 +02:00 |
Clifford Wolf
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e7a984a4df
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Add dff2ff.v techmap file
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2017-05-31 11:45:58 +02:00 |
Clifford Wolf
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c365e33fd7
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Fix AIGER back-end for multiple symbols per input/latch/output/property
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2017-05-30 19:09:11 +02:00 |
Clifford Wolf
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05df3dbee4
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Add "setundef -anyseq"
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2017-05-28 11:59:05 +02:00 |
Clifford Wolf
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9ed4c9d710
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Improve write_aiger handling of unconnected nets and constants
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2017-05-28 11:31:35 +02:00 |
Clifford Wolf
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d9201b85f3
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Change default smt2 solver to yices (Yices 2 has switched its license to GPL)
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2017-05-27 11:56:01 +02:00 |
Clifford Wolf
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fad52abf70
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Add aliases for common sets of gate types to "abc -g"
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2017-05-24 11:39:05 +02:00 |
Clifford Wolf
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dca3b3cd5f
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Add examples/osu035
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2017-05-23 18:38:20 +02:00 |
Clifford Wolf
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664ba4d80e
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Merge branch 'master' of github.com:cliffordwolf/yosys
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2017-05-23 18:24:27 +02:00 |