Eddie Hung
6d4f01c3fa
kernel: separate IdString::put_reference() out to help inlining
2020-04-02 07:14:08 -07:00
Eddie Hung
4a8cecf03e
kernel: IdString:in() to use perfect forwarding
2020-04-02 07:14:08 -07:00
Eddie Hung
164dd0f6b2
kernel: Use constids.inc for global/constant IdStrings
2020-04-02 07:14:08 -07:00
Eddie Hung
37f42fe102
Merge pull request #1845 from YosysHQ/eddie/kernel_speedup
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kernel: speedup by using more pass-by-const-ref
2020-04-02 07:13:33 -07:00
Eddie Hung
c90324662c
Merge pull request #1828 from YosysHQ/eddie/celltypes_speedup
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kernel: share a single CellTypes within a pass
2020-04-01 14:17:45 -07:00
Alberto Gonzalez
ae05795f54
Clean up pseudo-private member usage in `kernel/yosys.cc`.
2020-04-01 02:53:56 +00:00
Eddie Hung
348e892314
kernel: pass-by-value into Design::scratchpad_set_string() too
2020-03-27 12:21:09 -07:00
Rupert Swarbrick
044ca9dde4
Add support for SystemVerilog-style `define to Verilog frontend
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This patch should support things like
`define foo(a, b = 3, c) a+b+c
`foo(1, ,2)
which will evaluate to 1+3+2. It also spots mistakes like
`foo(1)
(the 3rd argument doesn't have a default value, so a call site is
required to set it).
Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.
Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.
Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
2020-03-27 16:08:26 +00:00
Eddie Hung
6ca7844cec
kernel: const Wire* overload -> Wire* !!!
2020-03-26 16:21:30 -07:00
Eddie Hung
f97b90e40b
kernel: Cell::set{Port,Param}() to pass by value, but use std::move
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Otherwise cell->setPort(ID::A, cell->getPort(ID::B)) could be invalid
2020-03-26 14:33:06 -07:00
Eddie Hung
7ad7f41bc5
kernel: share a single CellTypes within a pass
2020-03-18 12:21:40 -07:00
Eddie Hung
940640ac44
kernel: SigSpec copies to not trigger pack()
2020-03-18 11:51:00 -07:00
Eddie Hung
4555b5b819
kernel: more pass by const ref, more speedups
2020-03-18 11:21:53 -07:00
Eddie Hung
8b12e97153
kernel: speedup
2020-03-18 08:48:36 -07:00
Eddie Hung
8c45ea9f0e
kernel: use const reference for SigSet too
2020-03-17 10:22:33 -07:00
Eddie Hung
bc51e609cb
kernel: fix DeleteWireWorker
2020-03-17 10:22:16 -07:00
Claire Wolf
ed4fa19ba2
Update Copyright
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-03-16 16:28:25 +01:00
Waldir Pimenta
418c069561
License: bump year and add title
2020-03-14 16:46:07 +00:00
Miodrag Milanovic
395daf6ced
exclude clang from checking
2020-03-13 17:23:27 +01:00
Miodrag Milanovic
8f221118d2
Add YS_ prefix to macros, add explanation and apply to older version as well
2020-03-13 17:19:54 +01:00
Eddie Hung
432a09af80
kernel: SigSpec use more const& + overloads to prevent implicit SigSpec
2020-03-13 08:17:39 -07:00
Miodrag Milanovic
7c54e61979
Use boost xpressive for gcc 4.8
2020-03-13 14:58:35 +01:00
Eddie Hung
b567f03c26
kernel: optimise Module::remove(const pool<RTLIL::Wire*>()
2020-03-12 16:00:34 -07:00
Eddie Hung
a076052fe4
kernel: SigPool to use const& + overloads to prevent implicit SigSpec
2020-03-12 16:00:34 -07:00
jiegec
7b679eecb3
Fix compilation for emcc
2020-03-11 22:09:24 +08:00
David Shah
b8abf14376
Add ScriptPass::run_nocheck and use for abc9
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Signed-off-by: David Shah <dave@ds0.me>
2020-03-09 14:34:22 +00:00
Claire Wolf
b597f85b13
Merge pull request #1718 from boqwxp/precise_locations
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Closes #1717 . Add more precise Verilog source location information to AST and RTLIL nodes.
2020-03-03 08:38:32 -08:00
Eddie Hung
0f4c1906bb
Small fixes
2020-02-27 10:29:53 -08:00
Eddie Hung
78929e8c3d
Fixes for older compilers
2020-02-27 10:17:29 -08:00
Eddie Hung
6bb3d9f9c0
Make TimingInfo::TimingInfo(SigBit) constructor explicit
2020-02-27 10:17:29 -08:00
Eddie Hung
9dcf204dec
TimingInfo: index by (port_name,offset)
2020-02-27 10:17:29 -08:00
Eddie Hung
7c3b4b80ea
Fix spacing
2020-02-27 10:17:29 -08:00
Eddie Hung
1ef1ca812b
Get rid of (* abc9_{arrival,required} *) entirely
2020-02-27 10:17:29 -08:00
Eddie Hung
a6fec9fe60
abc9_ops: use TimingInfo for -prep_{lut,box} too
2020-02-27 10:17:29 -08:00
Eddie Hung
3ea5506f81
abc9_ops: use TimingInfo for -prep_{lut,box} too
2020-02-27 10:17:29 -08:00
Eddie Hung
cda4acb544
abc9_ops: add and use new TimingInfo struct
2020-02-27 10:17:29 -08:00
Miodrag Milanović
036c46de1e
Merge pull request #1705 from YosysHQ/logger_pass
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Logger pass
2020-02-26 13:32:49 +01:00
Miodrag Milanovic
1c569fe06a
Remove duplicate warning detection
2020-02-23 10:56:27 +01:00
Alberto Gonzalez
f0afd65035
Closes #1717 . Add more precise Verilog source location information to AST and RTLIL nodes.
2020-02-23 07:22:26 +00:00
Miodrag Milanovic
d079ab9d19
Handle expect no warnings together with expected
2020-02-22 10:52:46 +01:00
Miodrag Milanovic
70db8e9200
Prevent double error message
2020-02-17 16:46:34 +01:00
Miodrag Milanovic
5641b0248f
Option to expect no warnings
2020-02-17 15:36:06 +01:00
Miodrag Milanovic
be977cf7eb
No new error if already failing
2020-02-17 12:54:36 +01:00
Miodrag Milanovic
6b396e6455
remove whitespace
2020-02-14 13:12:05 +01:00
Miodrag Milanovic
31b7a9c312
Add expect option to logger command
2020-02-14 12:21:16 +01:00
Eddie Hung
b523ecf2f4
specify: system timing checks to accept min:typ:max triple
2020-02-13 12:42:15 -08:00
Claire Wolf
5f53ea2b5b
Merge pull request #1659 from YosysHQ/clifford/experimental
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Add log_experimental() and experimental() API and "yosys -x"
2020-01-29 15:25:03 +01:00
Eddie Hung
6d27d43727
Add and use SigSpec::reverse()
2020-01-28 10:37:16 -08:00
Claire Wolf
5c2508cef8
Improve logging use of experimental features
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Signed-off-by: Claire Wolf <clifford@clifford.at>
2020-01-28 17:51:50 +01:00
Claire Wolf
cef607c8b7
Add log_experimental() and experimental() API and "yosys -x"
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Signed-off-by: Claire Wolf <clifford@clifford.at>
2020-01-27 18:27:47 +01:00
Claire Wolf
de6006fbc8
Merge pull request #1613 from porglezomp-misc/version-flag-alias
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Add --version and -version as aliases for -V
2020-01-27 12:59:27 +01:00
Eddie Hung
ade57058f7
As before, only display MEM if Linux or FreeBSD
2020-01-14 11:38:48 -08:00
Eddie Hung
a901a5fb44
print_stats footer to return peak memory, option for including children
2020-01-14 11:25:23 -08:00
Eddie Hung
67c9c41f7e
Move abc9.* constpad entries to Abc9Pass::on_register()
2020-01-09 17:10:54 -08:00
Eddie Hung
dd718838bb
Merge remote-tracking branch 'origin/clifford/onpassreg' into eddie/abc9_scratchpad
2020-01-09 17:06:13 -08:00
Clifford Wolf
cd92a974f4
Add Pass::on_register() and Pass::on_shutdown()
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2020-01-09 21:36:34 +01:00
Eddie Hung
fbd9636e08
Add abc9.if.script.flow{,2} to constpad
2020-01-08 12:15:01 -08:00
Eddie Hung
a63e2508fc
Add RTLIL::constpad, init by yosys_setup(); use for abc9
2020-01-08 10:52:08 -08:00
Cassie Jones
b76b023584
Add --version and -version as aliases for -V
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The flag --version is commonly accepted by command line tools.
The code for the version flags added here matches the pattern used for
the help flag aliases, for consistency.
Fixes #1612
2020-01-05 03:19:02 -05:00
Clifford Wolf
3edb2e708b
Always create $shl, $shr, $sshl, $sshr cells with unsigned B inputs
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2020-01-02 18:58:45 +01:00
whitequark
e97e33d00d
kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.
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Before this commit, these cells would accept any \B_SIGNED and in
case of \B_SIGNED=1, would still treat the \B input as unsigned.
Also fix the Verilog frontend to never emit such constructs.
2019-12-04 11:59:36 +00:00
Eddie Hung
6bf7114bbd
Fix for SigSpec() == SigSpec(State::Sx, 0) to be true again
2019-10-04 16:45:36 -07:00
Eddie Hung
279fd22ddf
Add Const::{begin,end,empty}()
2019-10-04 15:00:57 -07:00
Eddie Hung
62c66406ad
log_dump() to support State enum
2019-10-02 17:49:07 -07:00
Eddie Hung
d963e8c2c6
Fix typo
2019-09-30 15:18:40 -07:00
Miodrag Milanović
0d27ffd4e6
Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in
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Open aig frontend as binary file
2019-09-30 17:49:23 +02:00
Eddie Hung
d5f0794a53
Merge pull request #1414 from hzeller/improve-replace-with-empty-map
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Avoid work in replace() if rules empty.
2019-09-29 19:35:23 -07:00
Miodrag Milanovic
3f70c1fd26
Open aig frontend as binary file
2019-09-29 13:22:11 +02:00
Henner Zeller
8c2b4f0a50
Avoid work in replace() if rules empty.
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This speeds up processing when number of bits are large but there
is actually nothing to replace. Adresses part of #1382 .
Signed-off-by: Henner Zeller <h.zeller@acm.org>
2019-09-29 00:17:40 -07:00
Miodrag Milanovic
d0493925ec
Support binary files for backends, fixes #1407
2019-09-28 09:36:18 +02:00
Miodrag Milanovic
435300f930
Make read/write gzip files on macos works, fixes #1357
2019-09-26 19:35:12 +02:00
Eddie Hung
9a84e4711c
Spacing
2019-09-13 16:30:44 -07:00
Eddie Hung
5473e597bf
Use template specialisation
2019-09-13 11:13:57 -07:00
Eddie Hung
95e80809a5
Revert "SigSet<Cell*> to use stable compare class"
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This reverts commit 4ea34aaacd
.
2019-09-13 09:49:15 -07:00
Eddie Hung
c487a8ff25
Grammar
2019-09-12 12:00:34 -07:00
Eddie Hung
c05a403dd1
static_assert to enforce this going forward
2019-09-12 11:45:17 -07:00
Eddie Hung
4ea34aaacd
SigSet<Cell*> to use stable compare class
2019-09-12 11:45:02 -07:00
Clifford Wolf
e9f3eb9760
Bump year in copyright notice
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-22 18:43:16 +02:00
Clifford Wolf
2a78a1fd00
Merge pull request #1283 from YosysHQ/clifford/fix1255
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Fix various NDEBUG compiler warnings
2019-08-17 15:07:16 +02:00
Eddie Hung
3b19c3657c
Move namespace alias
2019-08-16 19:37:11 +00:00
Eddie Hung
0b9ee4fbbf
Try this for gcc-4.8?
2019-08-15 16:20:54 -07:00
Eddie Hung
453a9429b6
Fix spacing
2019-08-15 14:54:41 -07:00
Eddie Hung
52355f5185
Use more ID::{A,B,Y,blackbox,whitebox}
2019-08-15 14:50:10 -07:00
Clifford Wolf
49301b733e
Merge branch 'master' into clifford/fix1255
2019-08-15 22:44:38 +02:00
Eddie Hung
4cfefae21e
More use of IdString::in()
2019-08-15 09:23:57 -07:00
Clifford Wolf
0c5db07cd6
Fix various NDEBUG compiler warnings, closes #1255
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-13 13:29:03 +02:00
Clifford Wolf
b25cf36856
Add YOSYS_NO_IDS_REFCNT configuration macro
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-11 12:23:16 +02:00
Clifford Wolf
390bf459fb
Use ID() in kernel/*, add simple ID:: hack (to be improved upon later)
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-11 11:39:46 +02:00
Clifford Wolf
8222c5735e
More improvements and cleanups in IdString subsystem
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- better use of "inline" keyword
- deprecate "sticky" IDs feature
- improve handling of empty ID
- add move constructor
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-11 11:39:46 +02:00
Clifford Wolf
b5534b66c8
Improve API of ID() macro
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-11 11:39:46 +02:00
Clifford Wolf
f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup
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Cleanup a few barnacles across codebase
2019-08-10 09:52:14 +02:00
Eddie Hung
6d77236f38
substr() -> compare()
2019-08-07 12:20:08 -07:00
Eddie Hung
71eff6f0de
RTLIL::S{0,1} -> State::S{0,1} for headers
2019-08-07 11:14:03 -07:00
Eddie Hung
7164996921
RTLIL::S{0,1} -> State::S{0,1}
2019-08-07 11:12:38 -07:00
Eddie Hung
e6d5147214
Merge remote-tracking branch 'origin/master' into eddie/cleanup
2019-08-07 11:11:50 -07:00
Eddie Hung
48d0f99406
stoi -> atoi
2019-08-07 11:09:17 -07:00
Clifford Wolf
9260e97aa2
Automatically prune init attributes in verific front-end, fixes #1237
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-07 15:31:49 +02:00
Clifford Wolf
e9a756aa7a
Merge pull request #1213 from YosysHQ/eddie/wreduce_add
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wreduce/opt_expr: improve width reduction for $add and $sub cells
2019-08-07 14:27:35 +02:00
Clifford Wolf
c5d56fbe2d
Merge pull request #1253 from YosysHQ/clifford/check
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Be less aggressive with running design->check()
2019-08-07 12:14:41 +02:00
Clifford Wolf
338f6765eb
Tweak default gate costs, cleanup "stat -tech cmos"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-07 10:25:51 +02:00