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923 Commits

Author SHA1 Message Date
Udi Finkelstein 73d426bc87 Modified errors into warnings 
No longer false warnings for memories and assertions
 2018-06-05 18:03:22 +03:00
Clifford Wolf 4372cf690d Add (* gclk *) attribute support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-01 13:25:42 +02:00
Clifford Wolf 9a946c207f Add comment to VIPER #13453 work-around 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-28 13:36:35 +02:00
Clifford Wolf 001c9f1d45 Fix Verific handling of single-bit anyseq/anyconst wires 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-25 15:41:45 +02:00
Clifford Wolf 251562a491 Fix VerificClocking for cases where Verific generates chains of PRIM_SVA_POSEDGE 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-24 18:13:38 +02:00
Clifford Wolf 4d645f0fce Fix verific handling of anyconst/anyseq attributes 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-24 17:07:06 +02:00
Jim Paris 4a229e5b95 Support SystemVerilog `` extension for macros 2018-05-17 00:09:56 -04:00
Jim Paris 872d8d49e9 Skip spaces around macro arguments 2018-05-17 00:06:49 -04:00
Clifford Wolf a7281930c5 Fix handling of anyconst/anyseq attrs in VHDL code via Verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-15 19:27:00 +02:00
Sergiusz Bazanski 7d076f071e Also interpret '&' in liberty functions 2018-05-12 20:55:31 +02:00
Clifford Wolf 24e6401617 Further improve handling of zero-length SVA consecutive repetition 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-05 14:32:04 +02:00
Clifford Wolf 3e67497ec2 Fix handling of zero-length SVA consecutive repetition 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-05 13:58:01 +02:00
Clifford Wolf a572b49538 Replace -ignore_redef with -[no]overwrite 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-03 15:25:59 +02:00
Dan Gisselquist e060375f23 Support more character literals 2018-05-03 12:35:01 +02:00
Clifford Wolf 2d7f3123f0 Add statement labels for immediate assertions 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-13 11:52:28 +02:00
Clifford Wolf 66ffc99695 Allow "property" in immediate assertions 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-12 14:28:28 +02:00
Clifford Wolf 617c60cea6 Add PRIM_HDL_ASSERTION support to Verific importer 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-07 18:38:42 +02:00
Clifford Wolf 0ac768f9df Fix handling of $global_clocking in Verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-06 21:23:47 +02:00
Clifford Wolf 5ea2c53604 Add read_verilog anyseq/anyconst/allseq/allconst attribute support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-06 14:35:11 +02:00
Clifford Wolf 278685b084 Add Verific anyseq/anyconst/allseq/allconst attribute support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-06 14:19:55 +02:00
Clifford Wolf ab8db2c168 Add "verific -autocover" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-06 14:10:57 +02:00
makaimann 0c404b1f63 Set RAM runtime flags for Verific frontend 2018-04-05 17:38:08 -07:00
Clifford Wolf 93985d91b1 Remove left-over log_ping debug commands.. oops. 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-31 14:23:57 +02:00
Udi Finkelstein 6378e2cd46 First draft of Verilog parser support for specify blocks and parameters. 
The only functionality of this code at the moment is to accept correct specify syntax and ignore it.
No part of the specify block is added to the AST
 2018-03-27 14:34:00 +02:00
Clifford Wolf 315d5e32bf Fix handling of unclocked immediate assertions in Verific front-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-26 13:04:10 +02:00
Clifford Wolf e7862d4f64 Update todo for more features to verificsva.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-16 15:48:48 +01:00
Clifford Wolf 38596ce68f Update todo for more features to verificsva.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-16 12:16:52 +01:00
Clifford Wolf 462e9f7bd4 Add todo for more features to verificsva.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-16 12:15:36 +01:00
Clifford Wolf 7cf9d88028 Improve import of memories via Verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-15 18:20:37 +01:00
Clifford Wolf bf402a806a Fix handling of SV compilation units in Verific front-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-14 20:22:11 +01:00
Udi Finkelstein 2b9c75f8e3 This PR should be the base for discussion, do not merge it yet! 
It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements.

What it DOES'T do:
Detect registers connected to output ports of instances.

Where it FAILS:
memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals.

You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
 2018-03-11 23:09:34 +02:00
Clifford Wolf 307c16a309 Fix SVA handling of NON_CONSECUTIVE_REPEAT and GOTO_REPEAT 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-10 16:24:01 +01:00
Clifford Wolf ce37b6d730 Fix variable name typo in verificsva.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-10 14:33:42 +01:00
Clifford Wolf da216937b1 Add support for trivial SVA sequences and properties 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-10 14:32:01 +01:00
Clifford Wolf a15208f301 Use Verific hier_tree component for elaboration 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-08 13:26:33 +01:00
Clifford Wolf a4bbfd2d15 Fix Verific handling of "assert property (..);" in always block 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-07 20:06:02 +01:00
Clifford Wolf 92d5f4db6f Add "verific -import -V" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-07 19:40:34 +01:00
Clifford Wolf 252627fc54 Set Verific db_preserve_user_nets flag 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-07 18:08:03 +01:00
Clifford Wolf dcc4a18d5a Update comment about supported SVA in verificsva.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-06 15:47:33 +01:00
Clifford Wolf 03b49654b1 Add SVA NON_CONSECUTIVE_REPEAT and GOTO_REPEAT support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-06 15:39:46 +01:00
Clifford Wolf 7bb83ae9f2 Add SVA first_match() support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-06 15:06:35 +01:00
Clifford Wolf 78f2cca2d9 Add SVA within support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-06 14:41:27 +01:00
Clifford Wolf 5555292ce2 Add support for SVA sequence intersect 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-06 14:26:57 +01:00
Clifford Wolf d86e875f0f Add get_fsm_accept_reject for parsing SVA properties 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-06 11:50:38 +01:00
Clifford Wolf 588ce0e34a Simplified SVA "until" handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-06 01:51:42 +01:00
Clifford Wolf 480e8e676a Add proper SVA seq.triggered support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-04 19:29:26 +01:00
Clifford Wolf 8dcf3d0c76 Add Verific SVA support for "seq and seq" expressions 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-04 15:08:21 +01:00
Clifford Wolf 9ab2498c55 Refactor Verific SVA importer property parser 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-04 14:29:48 +01:00
Clifford Wolf 261cf706f4 Add VerificClocking class and refactor Verific DFF handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-04 13:48:53 +01:00
Clifford Wolf 707ddb77bc Add SVA support for sequence OR 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-03 16:34:28 +01:00
Clifford Wolf cabc3c59e0 Fix handling of SVA "until seq.triggered" properties 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-02 18:17:10 +01:00
Clifford Wolf ab791e61b3 Update SVA cheat sheet in verificsva.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-02 16:05:56 +01:00
Clifford Wolf 4e5f1f59d6 Fix in Verific SVA importer handling of until_with 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-01 19:37:36 +01:00
Clifford Wolf 9a2a8cd97b Fixes and improvements in Verific SVA importer 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-01 11:40:43 +01:00
Clifford Wolf 3c49e3c5b3 Add $rose/$fell support to Verific bindings 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-01 10:12:15 +01:00
Clifford Wolf 5ac3ee858a Add support for PRIM_SVA_UNTIL to new SVA importer 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-28 15:32:17 +01:00
Clifford Wolf 8a1d6ccf0c Add DFSM generator to verific SVA importer 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-28 15:05:33 +01:00
Clifford Wolf 15902d495f Continue refactoring of Verific SVA importer code 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-28 11:45:04 +01:00
Clifford Wolf 25e33d7ab8 Major redesign of Verific SVA importer 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-27 20:33:15 +01:00
Clifford Wolf b6fbeb0969 Add handling of verific OPER_REDUCE_NOR 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-26 15:26:01 +01:00
Clifford Wolf 2aeb4d4e12 Add handling of verific OPER_SELECTOR and OPER_WIDE_SELECTOR 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-26 15:20:27 +01:00
Clifford Wolf 9cd9f5fc78 Add handling of verific OPER_NTO1MUX and OPER_WIDE_NTO1MUX 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-26 15:02:03 +01:00
Clifford Wolf d1cb5150aa Add "SVA syntax cheat sheet" comment to verificsva.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-26 14:31:58 +01:00
Clifford Wolf eb67a7532b Add $allconst and $allseq cell types 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-23 13:14:47 +01:00
Clifford Wolf 2521ed305e Add Verific SVA support for ranges in repetition operator 2018-02-22 12:37:30 +01:00
Clifford Wolf 6d12c83d36 Add support for SVA throughout via Verific 2018-02-21 13:09:47 +01:00
Clifford Wolf 5c6247dfa6 Add support for SVA sequence concatenation ranges via verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-18 16:35:06 +01:00
Clifford Wolf 9d963cd29c Add support for SVA until statements via Verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-18 14:57:52 +01:00
Clifford Wolf 5fa2aa2741 Move Verific SVA importer to extra C++ source file 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-18 13:52:49 +01:00
Clifford Wolf c4bf34f6ce Merge Verific SVA preprocessor and SVA importer 2018-02-18 13:28:08 +01:00
Clifford Wolf 68a829dbcd Merge branch 'master' of github.com:cliffordwolf/yosys 2018-02-16 14:22:11 +01:00
Clifford Wolf 2c95dfcb5b Improve handling of "bus" pins in liberty front-end (some files use bus.pin.direction) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-15 17:36:08 +01:00
Clifford Wolf bc8ab3ab44 Fix verific PRIM_SVA_AT handling in properties with PRIM_SVA_DISABLE_IFF 2018-02-15 15:26:37 +01:00
Clifford Wolf 6c00e064e2 Fix single-bit $stable handling in verific front-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-01 12:51:49 +01:00
Clifford Wolf 9af40faa0b Add Verific attribute handling for assert/assume/cover/live/fair cells 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-31 19:06:51 +01:00
Clifford Wolf 675f53abbb Fix permissions on verific vdb files 2018-01-28 18:52:01 +01:00
Clifford Wolf 1d8161b432 Fixed handling of synchronous and asynchronous assertion/assumption/cover in verific bindings 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-23 17:42:40 +01:00
Clifford Wolf a96c775a73 Add support for "yosys -E" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-07 16:36:13 +01:00
Clifford Wolf 26c4323d48
Merge pull request #479 from Fatsie/latch_without_data 
Some standard cell libraries include a latch with only set/reset.
 2018-01-05 23:00:28 +01:00
Clifford Wolf c80315cea4 Bugfix in hierarchy handling of blackbox module ports 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-05 13:28:45 +01:00
Staf Verhaegen 5126c6f22b Some standard cell libraries include a latch with only set/reset. 2018-01-03 21:36:02 +00:00
Clifford Wolf 34005348b6 Bugfix in verilog_defaults argument parser 2017-12-24 17:21:37 +01:00
Clifford Wolf ba90e08398 Add support for Verific PRIM_SVA_NOT properties 2017-12-10 01:10:03 +01:00
Clifford Wolf e4a4c0e10c Add Verific OPER_SVA_STABLE support 2017-12-10 00:59:44 +01:00
Clifford Wolf 27916105a9 Refactoring Verific SVA rewriter 2017-12-10 00:26:26 +01:00
Clifford Wolf 8364f509e3 Fix error handling for nested always/initial 2017-12-02 18:52:05 +01:00
Clifford Wolf 777f2881d8 Add Verilog "automatic" keyword (ignored in synthesis) 2017-11-23 08:51:38 +01:00
Clifford Wolf 5b6e52118c Accept real-valued delay values 2017-11-18 10:01:30 +01:00
William D. Jones abc5b4b8ce Accommodate Windows-style paths during include-file processing. 2017-11-14 16:16:24 -05:00
Clifford Wolf a8cf431d9c Remove vhdl2verilog 2017-10-25 14:50:22 +02:00
Clifford Wolf 0a31a0b3ae Remove all PSL support code from verific.cc 2017-10-20 13:14:04 +02:00
Clifford Wolf 1954c78ea7 Add "verific -vlog-libdir" 2017-10-13 20:23:19 +02:00
Clifford Wolf e7a3c47cc7 Add "verific -vlog-incdir" and "verific -vlog-define" 2017-10-13 20:12:51 +02:00
Clifford Wolf 05068af880 Update Verific README 2017-10-13 17:11:53 +02:00
Clifford Wolf bc5cc4e103 Add Verific fairness/liveness support 2017-10-12 12:00:09 +02:00
Clifford Wolf 12c10892e6 Merge branch 'master' of github.com:cliffordwolf/yosys 2017-10-10 15:16:45 +02:00
Clifford Wolf c10e96c9ec Start work on pre-processor for Verific SVA properties 2017-10-10 15:16:39 +02:00
Clifford Wolf bc80426d45 Remove some dead code 2017-10-10 12:00:48 +02:00
Clifford Wolf caa78388cd Allow $past, $stable, $rose, $fell in $global_clock blocks 2017-10-10 11:59:32 +02:00
Clifford Wolf fc3378916d Improve handling of Verific errors 2017-10-05 14:38:32 +02:00
Clifford Wolf ee56a887b6 Improve Verific error handling, check VHDL static asserts 2017-10-04 18:56:28 +02:00
Clifford Wolf b92ff2706e Fix nasty bug in Verific bindings 2017-10-04 17:23:42 +02:00
Clifford Wolf a381188b92 Merge branch 'pr_ast_const_funcs' of https://github.com/udif/yosys 2017-10-03 18:23:45 +02:00
Udi Finkelstein eb40278a16 Turned a few member functions into const, esp. dumpAst(), dumpVlog(). 2017-09-30 07:37:38 +03:00
Udi Finkelstein 72a08eca3d Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the textbook solution 
(Oreilly 'Flex & Bison' page 189)
 2017-09-30 06:39:07 +03:00
Clifford Wolf dbfd8460a9 Allow $size and $bits in verilog mode, actually check test case 2017-09-29 11:56:43 +02:00
Udi Finkelstein e951ac0dfb $size() now works correctly for all cases! 
It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.
 2017-09-26 20:34:24 +03:00
Udi Finkelstein 6ddc6a7af4 $size() seems to work now with or without the optional parameter. 
Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
 2017-09-26 19:18:25 +03:00
Udi Finkelstein 7e391ba904 enable $bits() and $size() functions only when the SystemVerilog flag is enabled for read_verilog 2017-09-26 09:19:56 +03:00
Udi Finkelstein 2dea42e903 Added $bits() for memories as well. 2017-09-26 09:11:25 +03:00
Udi Finkelstein 17f8b41605 $size() now works with memories as well! 2017-09-26 08:36:45 +03:00
Udi Finkelstein 64eb8f29ad Add $size() function. At the moment it works only on expressions, not on memories. 2017-09-26 06:25:42 +03:00
Clifford Wolf 30396270a2 Increase maximum LUT size in blifparse to 12 bits 2017-09-27 15:27:42 +02:00
Clifford Wolf 91d9c50bb3 Parse reals as string in JSON front-end 2017-09-26 14:37:03 +02:00
Clifford Wolf 2c04d883b1 Minor coding style fix 2017-09-26 13:50:14 +02:00
Clifford Wolf cb1d439d10 Merge branch 'master' of https://github.com/combinatorylogic/yosys into combinatorylogic-master 2017-09-26 13:48:13 +02:00
Clifford Wolf 2cc09161ff Fix ignoring of simulation timings so that invalid module parameters cause syntax errors 2017-09-26 01:52:59 +02:00
combinatorylogic 64ca0be971 Adding support for string macros and macros with arguments after include 2017-09-21 18:25:02 +01:00
Robert Ou 366ce87cff json: Parse inout correctly rather than as an output 2017-08-14 12:09:03 -07:00
Clifford Wolf 15073790bf Add merging of "past FFs" to verific importer 2017-07-29 00:10:38 +02:00
Clifford Wolf d4b9602cbd Add minimal support for PSL in VHDL via Verific 2017-07-28 17:39:49 +02:00
Clifford Wolf 5a828fff34 Improve Verific HDL language options 2017-07-28 15:32:54 +02:00
Clifford Wolf acd6cfaf67 Fix handling of non-user-declared Verific netbus 2017-07-28 11:31:27 +02:00
Clifford Wolf c1cfca8f54 Improve Verific SVA importer 2017-07-27 14:05:09 +02:00
Clifford Wolf 2336d5508b Add log_warning_noprefix() API, Use for Verific warnings and errors 2017-07-27 12:17:04 +02:00
Clifford Wolf d9641621d9 Add "verific -import -n" and "verific -import -nosva" 2017-07-27 11:54:45 +02:00
Clifford Wolf 90d8329f64 Improve Verific SVA import: negedge and $past 2017-07-27 11:40:07 +02:00
Clifford Wolf 147ff96ba3 Improve Verific SVA importer 2017-07-27 10:39:39 +02:00
Clifford Wolf 530040ba6f Improve Verific bindings (mostly related to SVA) 2017-07-26 18:00:01 +02:00
Clifford Wolf abd3b4e8e7 Improve "help verific" message 2017-07-25 15:13:22 +02:00
Clifford Wolf 6dbe1d4c92 Add "verific -extnets" 2017-07-25 14:53:11 +02:00
Clifford Wolf c97c92e4ec Improve "verific -all" handling 2017-07-25 13:33:25 +02:00
Clifford Wolf 41be530c4e Add "verific -import -d <dump_file" 2017-07-24 13:57:16 +02:00
Clifford Wolf 92d3aad670 Add "verific -import -flatten" and "verific -import -v" 2017-07-24 11:29:06 +02:00
Clifford Wolf 5be535517c Add "verific -import -k" 2017-07-22 16:16:44 +02:00
Clifford Wolf 2785aaffeb Improve docs for verific bindings, add simply sby example 2017-07-22 11:58:51 +02:00
Clifford Wolf 36cf18ac4c Fix "read_blif -wideports" handling of cells with wide ports 2017-07-21 16:21:12 +02:00
Clifford Wolf 26766da343 Add a paragraph about pre-defined macros to read_verilog help message 2017-07-21 14:34:53 +02:00
Clifford Wolf 9557fd2a36 Add attributes and parameter support to JSON front-end 2017-07-10 13:17:38 +02:00
Clifford Wolf 4b2d1fe688 Add JSON front-end 2017-07-08 16:40:40 +02:00
Clifford Wolf 28039c3063 Add Verific Release information to log 2017-07-04 20:01:30 +02:00
Clifford Wolf 8f8baccfde Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand const reg" 2017-06-07 12:30:24 +02:00
Clifford Wolf 129984e115 Fix handling of Verilog ~& and ~| operators 2017-06-01 12:43:21 +02:00
Clifford Wolf e91548b33e Add support for localparam in module header 2017-04-30 17:20:30 +02:00
Clifford Wolf f0db8ffdbc Add support for `resetall compiler directive 2017-04-26 16:09:41 +02:00
Clifford Wolf 088f9c9cab Fix verilog pre-processor for multi-level relative includes 2017-03-14 17:30:20 +01:00
Clifford Wolf 5b3b5ffc8c Allow $anyconst, etc. in non-formal SV mode 2017-03-01 10:47:05 +01:00
Clifford Wolf 5f1d0b1024 Add $live and $fair cell types, add support for s_eventually keyword 2017-02-25 10:36:39 +01:00
Clifford Wolf 00dba4c197 Add support for SystemVerilog unique, unique0, and priority case 2017-02-23 16:33:19 +01:00
Clifford Wolf 1e927a51d5 Preserve string parameters 2017-02-23 15:39:13 +01:00
Clifford Wolf 34d4e72132 Added SystemVerilog support for ++ and -- 2017-02-23 11:21:33 +01:00
Clifford Wolf 4fb8007171 Fix incorrect "incompatible re-declaration of wire" error in tasks/functions 2017-02-14 15:10:59 +01:00
Clifford Wolf cdb6ceb8c6 Add support for verific mem initialization 2017-02-11 15:57:36 +01:00
Clifford Wolf c449f4b86f Fix another stupid bug in the same line 2017-02-11 11:47:51 +01:00
Clifford Wolf fa4a7efe15 Add verific support for initialized variables 2017-02-11 11:40:18 +01:00
Clifford Wolf 0b7aac645c Improve handling of Verific warnings and error messages 2017-02-11 11:39:50 +01:00
Clifford Wolf eb7b18e897 Fix extremely stupid typo 2017-02-11 11:09:07 +01:00
Clifford Wolf 848062088c Add checker support to verilog front-end 2017-02-09 13:51:44 +01:00
Clifford Wolf 2ca8d483dd Add "rand" and "rand const" verific support 2017-02-09 12:53:46 +01:00
Clifford Wolf ef4a28e112 Add SV "rand" and "const rand" support 2017-02-08 14:38:15 +01:00
Clifford Wolf 1d1f56a361 Add PSL parser mode to verific front-end 2017-02-08 10:40:33 +01:00
Clifford Wolf 7e0b776a79 Add "read_blif -wideports" 2017-02-06 14:48:03 +01:00
Clifford Wolf 6abf79eb28 Further improve cover() support 2017-02-04 17:02:13 +01:00
Clifford Wolf 3928482a3c Add $cover cell type and SVA cover() support 2017-02-04 14:14:26 +01:00
Clifford Wolf 911c44d164 Add assert/assume support to verific front-end 2017-02-04 13:36:00 +01:00
Clifford Wolf fea528280b Add "enum" and "typedef" lexer support 2017-01-17 17:33:52 +01:00
Clifford Wolf 78f65f89ff Fix bug in AstNode::mem2reg_as_needed_pass2() 2017-01-15 13:52:50 +01:00
Clifford Wolf 2d32c6c4f6 Fixed handling of local memories in functions 2017-01-05 13:19:03 +01:00
Clifford Wolf 81a9ee2360 Added handling of local memories and error for local decls in unnamed blocks 2017-01-04 16:03:04 +01:00
Clifford Wolf dfb461fe52 Added Verilog $rtoi and $itor support 2017-01-03 17:40:58 +01:00
Clifford Wolf 3886669ab6 Added "verilog_defines" command 2016-12-15 17:49:28 +01:00
Clifford Wolf ecdc22b06c Added support for macros as include file names 2016-11-28 14:50:17 +01:00
Clifford Wolf c7f6fb6e17 Bugfix in "read_verilog -D NAME=VAL" handling 2016-11-28 14:45:05 +01:00
Clifford Wolf 70d7a02cae Added support for hierarchical defparams 2016-11-15 13:35:19 +01:00
Clifford Wolf a926a6afc2 Remember global declarations and defines accross read_verilog calls 2016-11-15 12:42:43 +01:00
Clifford Wolf 2874914bcb Fixed anonymous genblock object names 2016-11-04 07:46:30 +01:00
Clifford Wolf 56e2bb88ae Some fixes in handling of signed arrays 2016-11-01 23:17:43 +01:00
Clifford Wolf aa72262330 Added avail params to ilang format, check module params in 'hierarchy -check' 2016-10-22 11:05:49 +02:00
Clifford Wolf 042b67f024 No limit for length of lines in BLIF front-end 2016-10-19 12:44:58 +02:00
Clifford Wolf bdc316db50 Added $anyseq cell type 2016-10-14 15:24:03 +02:00
Clifford Wolf 53655d173b Added $global_clock verilog syntax support for creating $ff cells 2016-10-14 12:33:56 +02:00
Clifford Wolf 8ebba8a35f Added $ff and $_FF_ cell types 2016-10-12 01:18:39 +02:00
Clifford Wolf 8f5bf6de32 Added liberty parser support for types within cell decls 2016-09-23 13:53:23 +02:00
Clifford Wolf aaa99c35bd Added $past, $stable, $rose, $fell SVA functions 2016-09-19 01:30:07 +02:00
Clifford Wolf 13a03b84d4 Added support for bus interfaces to "read_liberty -lib" 2016-09-18 18:48:59 +02:00
Clifford Wolf ab18e9df7c Added assertpmux 2016-09-07 00:28:01 +02:00
Clifford Wolf d55a93b39f Bugfix in parsing of BLIF latch init values 2016-09-06 17:35:06 +02:00
Clifford Wolf 97583ab729 Avoid creation of bogus initial blocks for assert/assume in always @* 2016-09-06 17:34:42 +02:00
Clifford Wolf aa25a4cec6 Added $anyconst support to yosys-smtbmc 2016-08-30 19:27:42 +02:00
Clifford Wolf 6f41e5277d Removed $aconst cell type 2016-08-30 19:09:56 +02:00
Clifford Wolf eae390ae17 Removed $predict again 2016-08-28 21:35:33 +02:00
Clifford Wolf 1276c87a56 Added read_verilog -norestrict -assume-asserts 2016-08-26 23:35:27 +02:00
Clifford Wolf 4be4969bae Improved verilog parser errors 2016-08-25 11:44:37 +02:00
Clifford Wolf cd18235f30 Added SV "restrict" keyword 2016-08-24 15:30:08 +02:00
Clifford Wolf 450f6f59b4 Fixed bug with memories that do not have a down-to-zero data width 2016-08-22 14:27:46 +02:00
Clifford Wolf 82a4a0230f Another bugfix in mem2reg code 2016-08-21 13:23:58 +02:00
Clifford Wolf dbdd8927e7 Minor improvements to AstNode::dumpAst() and AstNode::dumpVlog() 2016-08-21 13:18:09 +02:00
Clifford Wolf fe9315b7a1 Fixed finish_addr handling in $readmemh/$readmemb 2016-08-20 13:47:46 +02:00
Clifford Wolf f6629b9c29 Optimize memory address port width in wreduce and memory_collect, not verilog front-end 2016-08-19 18:38:25 +02:00
Clifford Wolf e9fe57c75e Only allow posedge/negedge with 1 bit wide signals 2016-08-10 19:32:11 +02:00
Clifford Wolf 7f755dec75 Fixed bug in parsing real constants 2016-08-06 13:16:23 +02:00
Clifford Wolf 4056312987 Added $anyconst and $aconst 2016-07-27 15:41:22 +02:00
Clifford Wolf a7b0769623 Added "read_verilog -dump_rtlil" 2016-07-27 15:40:17 +02:00
Clifford Wolf 5b944ef11b Fixed a verilog parser memory leak 2016-07-25 16:37:58 +02:00
Clifford Wolf 7a67add95d Fixed parsing of empty positional cell ports 2016-07-25 12:48:03 +02:00
Clifford Wolf 9aae1d1e8f No tristate warning message for "read_verilog -lib" 2016-07-23 11:56:53 +02:00
Clifford Wolf 7fef5ff104 Using $initstate in "initial assume" and "initial assert" 2016-07-21 14:37:28 +02:00
Clifford Wolf 5c166e76e5 Added $initstate cell type and vlog function 2016-07-21 14:23:22 +02:00
Clifford Wolf d7763634b6 After reading the SV spec, using non-standard predict() instead of expect() 2016-07-21 13:34:33 +02:00
Clifford Wolf 721f1f5ecf Added basic support for $expect cells 2016-07-13 16:56:17 +02:00
Clifford Wolf 9a101dc1f7 Fixed mem assignment in left-hand-side concatenation 2016-07-08 14:31:06 +02:00
Ruben Undheim 545bcb37e8 Allow defining input ports as "input logic" in SystemVerilog 2016-06-20 20:16:37 +02:00
Clifford Wolf 9bca8ccd40 Merge branch 'sv_packages' of https://github.com/rubund/yosys 2016-06-19 15:48:40 +02:00
Ruben Undheim a8200a773f A few modifications after pull request comments 
- Renamed Design::packages to Design::verilog_packages
- No need to include ast.h in rtlil.h
 2016-06-18 14:23:38 +02:00
Clifford Wolf 9e28290b0f Added "read_blif -sop" 2016-06-18 12:33:13 +02:00
Ruben Undheim 178ff3e7f6 Added support for SystemVerilog packages with localparam definitions 2016-06-18 10:53:55 +02:00
Clifford Wolf 52bb1b968d Added $sop cell type and "abc -sop" 2016-06-17 13:50:09 +02:00
Clifford Wolf 766032c5f8 Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b} 2016-05-27 17:55:03 +02:00
Clifford Wolf ee071586c5 Fixed access-after-delete bug in mem2reg code 2016-05-27 17:25:33 +02:00
Clifford Wolf e9ceec26ff fixed typos in error messages 2016-05-27 16:37:36 +02:00
Clifford Wolf 060bf4819a Small improvements in Verilog front-end docs 2016-05-20 16:21:35 +02:00
Clifford Wolf 570014800a Include <cmath> in yosys.h 2016-05-08 10:50:39 +02:00
Clifford Wolf 779e2cc819 Added support for "active high" and "active low" latches in BLIF front-end 2016-04-22 18:02:55 +02:00
Clifford Wolf 0bc95f1e04 Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
Clifford Wolf 5a09fa4553 Fixed handling of parameters and const functions in casex/casez pattern 2016-04-21 15:31:54 +02:00
Clifford Wolf 5328a85149 Do not set "nosync" on task outputs, fixes #134 2016-03-24 12:16:47 +01:00
Clifford Wolf 4f0d4899ce Added support for $stop system task 2016-03-21 16:19:51 +01:00
Clifford Wolf e5d42ebb4d Added $display %m support, fixed mem leak in $display, fixes #128 2016-03-19 11:51:13 +01:00
Clifford Wolf ef4207d5ad Fixed localparam signdness, fixes #127 2016-03-18 12:15:00 +01:00
Clifford Wolf b6d08f39ba Set "nosync" attribute on internal task/function wires 2016-03-18 10:53:29 +01:00
Clifford Wolf 33c10350b2 Fixed Verilog parser fix and more similar improvements 2016-03-15 12:22:31 +01:00
Andrew Becker 81d4e9e7c1 Use left-recursive rule for cell_port_list in Verilog parser. 2016-03-15 12:03:40 +01:00
Clifford Wolf 35a6ad4cc1 Fixed typos in verilog_defaults help message 2016-03-10 11:14:51 +01:00
Clifford Wolf 22c549ab37 Fixed BLIF parser for empty port assignments 2016-02-24 09:16:43 +01:00
Clifford Wolf bcc873b805 Fixed some visual studio warnings 2016-02-13 17:31:24 +01:00
Clifford Wolf 7bd329afa0 Support for more Verific primitives (patch I got per email) 2016-02-13 08:19:30 +01:00
Clifford Wolf 6a27cbe5b1 Bugfix in Verific front-end 2016-02-03 08:59:57 +01:00
Clifford Wolf 4a3e1ded1e Updated verific build instructions 2016-02-02 19:50:17 +01:00
Clifford Wolf ba407da187 Added addBufGate module method 2016-02-02 11:26:07 +01:00
Rick Altherr 34969d4140 genrtlil: avoid converting SigSpec to set<SigBit> when going through removeSignalFromCaseTree() 2016-01-31 09:20:16 -08:00
Clifford Wolf 5e90a78466 Various improvements in BLIF front-end 2015-12-20 13:12:24 +01:00
Clifford Wolf 4a697accd4 Fixed oom bug in ilang parser 2015-11-29 20:30:32 +01:00
Clifford Wolf 32f5ee117c Fixed performance bug in ilang parser 2015-11-27 19:46:47 +01:00
Clifford Wolf ab2d8e5c8c Added PRIM_DLATCHRS support to verific front-end 2015-11-24 12:16:19 +01:00
Clifford Wolf c86fbae3d1 Fixed handling of re-declarations of wires in tasks and functions 2015-11-23 17:09:57 +01:00
Clifford Wolf 415e0a1b90 Fixed performance bug in Verific importer 2015-11-16 12:38:56 +01:00
Clifford Wolf b18f3a2974 Changes for Verific 3.16_484_32_151112 2015-11-12 19:28:14 +01:00
Clifford Wolf 7ae3d1b5a9 More bugfixes in handling of parameters in tasks and functions 2015-11-12 13:02:36 +01:00
Clifford Wolf 34f2b84fb6 Fixed handling of parameters and localparams in functions 2015-11-11 10:54:35 +01:00
Clifford Wolf 207736b4ee Import more std:: stuff into Yosys namespace 2015-10-25 19:30:49 +01:00
Clifford Wolf 5308c1e02a Fixed bug in verilog parser 2015-10-15 15:19:23 +02:00
Clifford Wolf f13e387321 SystemVerilog also has assume(), added implicit -D FORMAL 2015-10-13 14:21:20 +02:00
Clifford Wolf ba4cce9f19 Added support for "parameter" and "localparam" in global context 2015-10-07 14:59:08 +02:00
Clifford Wolf e51dcc83d0 Fixed complexity of assigning to vectors in constant functions 2015-10-01 12:15:35 +02:00
Clifford Wolf 9caeadf797 Fixed detection of unconditional $readmem[hb] 2015-09-30 15:46:51 +02:00
Clifford Wolf f9d7df0869 Bugfixes in $readmem[hb] 2015-09-25 13:49:48 +02:00
Clifford Wolf b2544cfcf7 Fixed segfault in AstNode::asReal 2015-09-25 12:38:01 +02:00
Clifford Wolf 924d9d6e86 Added read-enable to memory model 2015-09-25 12:23:11 +02:00
Clifford Wolf 1b8cb9940e Fixed AstNode::mkconst_bits() segfault on zero-sized constant 2015-09-24 11:21:20 +02:00
Clifford Wolf e2e092b144 Added read_verilog -nodpi 2015-09-23 08:23:38 +02:00
Clifford Wolf 089c1e176f Bugfix in handling of multi-dimensional memories 2015-09-23 07:56:17 +02:00
Clifford Wolf 559929e341 Warning for $display/$write outside initial block 2015-09-23 07:16:03 +02:00
Clifford Wolf b845b77f86 Fixed support for $write system task 2015-09-23 07:10:56 +02:00
Clifford Wolf a3a13cce32 Fixed detection of "task foo(bar);" syntax error 2015-09-22 21:34:21 +02:00
Clifford Wolf 6176f4d081 Fixed multi-level prefix resolving 2015-09-22 20:52:02 +02:00
Clifford Wolf 4b8200eb49 Fixed segfault on invalid verilog constant 1'b_ 2015-09-22 08:13:09 +02:00
Andrew Zonenberg c469f22144 Improvements to $display system task 2015-09-19 10:33:37 +02:00
Clifford Wolf 9db05d17fe Added AST_INITIAL checks for $finish and $display 2015-09-18 09:50:57 +02:00
Andrew Zonenberg 7141f65533 Initial implementation of $display() 2015-09-18 09:36:46 +02:00
Andrew Zonenberg e446e651cb Initial implementation of $finish() 2015-09-18 09:30:25 +02:00
Clifford Wolf b10ea0550d gcc-4.6 build fixes 2015-09-01 12:51:23 +02:00
Clifford Wolf eb38722e98 Fixed handling of memory read without address 2015-08-22 14:46:42 +02:00
Clifford Wolf a7ab9172f9 Small corrections to const2ast warning messages 2015-08-17 16:22:53 +02:00
Florian Zeitz 0491042849 Check base-n literals only contain valid digits 2015-08-17 15:37:33 +02:00
Florian Zeitz 64ccbf8510 Warn on literals exceeding the specified bit width 2015-08-17 15:27:35 +02:00
Larry Doolittle 6c00704a5e Another block of spelling fixes 
Smaller this time
 2015-08-14 23:27:05 +02:00
Larry Doolittle 022f570563 Keep gcc from complaining about uninitialized variables 2015-08-14 23:26:49 +02:00
Clifford Wolf 0350074819 Re-created command-reference-manual.tex, copied some doc fixes to online help 2015-08-14 11:27:19 +02:00
Clifford Wolf 84bf862f7c Spell check (by Larry Doolittle) 2015-08-14 10:56:05 +02:00
Clifford Wolf e4ef000b70 Adjust makefiles to work with out-of-tree builds 
This is based on work done by Larry Doolittle
 2015-08-12 15:04:44 +02:00
Clifford Wolf 45ee2ba3b8 Fixed handling of [a-fxz?] in decimal constants 2015-08-11 11:32:37 +02:00
Marcus Comstedt c836faae3e Add -noautowire option to verilog frontend 2015-08-01 12:16:54 +02:00
Clifford Wolf 8d6d5c30d9 Added WORDS parameter to $meminit 2015-07-31 10:40:09 +02:00
Clifford Wolf 4513ff1b85 Fixed nested mem2reg 2015-07-29 16:37:08 +02:00
Clifford Wolf 6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf 13983e8318 Fixed handling of parameters with reversed range 2015-06-08 14:03:06 +02:00
Clifford Wolf 99b8746d27 Fixed signedness of genvar expressions 2015-05-29 20:08:00 +02:00
Clifford Wolf 08a4af3cde Improvements in BLIF front-end 2015-05-24 08:03:21 +02:00
Clifford Wolf 6061b7bd58 bugfix in blif front-end 2015-05-18 11:15:49 +02:00
Clifford Wolf 3ecb2bf067 Improved .latch support in BLIF front-end 2015-05-17 18:58:24 +02:00
Clifford Wolf 2cc4e75914 Added read_blif command 2015-05-17 15:25:03 +02:00
Clifford Wolf e5116eeb77 Generalized blifparse API 2015-05-17 15:10:37 +02:00
Clifford Wolf 7dad017c9c abc/blifparse files reorganization 2015-05-17 14:44:28 +02:00
Clifford Wolf 61512b6f41 Verific build fixes 2015-05-17 08:19:52 +02:00
Clifford Wolf 7ff802e199 Verilog front-end: define `BLACKBOX in -lib mode 2015-04-19 21:30:46 +02:00
Clifford Wolf a923a63a89 Ignore celldefine directive in verilog front-end 2015-03-25 19:46:12 +01:00
Clifford Wolf 422794c584 Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker() 2015-03-01 11:20:22 +01:00
Clifford Wolf 1f1deda888 Added non-std verilog assume() statement 2015-02-26 18:47:39 +01:00
Clifford Wolf d5ce9a32ef Added deep recursion warning to AST simplify 2015-02-20 10:33:20 +01:00
Clifford Wolf dc1a0f06fc Parser support for complex delay expressions 2015-02-20 10:21:36 +01:00