riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
9,971 Commits 76 Branches 48 Tags 62 MiB
Commit Graph

27 Commits

Author SHA1 Message Date
whitequark 7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
Eddie Hung dac5adde12 design: -import to not count black/white-boxes as candidates for top 2020-04-16 12:46:07 -07:00
Eddie Hung 8d3f6d0d79
Merge pull request #1928 from YosysHQ/eddie/design_delete 
kernel: add design -delete option
 2020-04-16 10:51:09 -07:00
Eddie Hung a9ec0defb9 kernel: add design -delete option 2020-04-16 08:05:18 -07:00
Eddie Hung 75bb2c8c24 design: do not delete when iterating over Design::modules() directly 2020-04-14 10:43:05 -07:00
whitequark 0d69d532e0
Merge pull request #1859 from boqwxp/design_duplicate 
Add `-push-copy` option to the `design` command.
 2020-04-06 10:39:26 +00:00
Alberto Gonzalez a0416fe167
Rename `-duplicate` to `-push-copy`. 
Co-Authored-By: whitequark <whitequark@whitequark.org>
 2020-04-04 21:26:11 +00:00
Alberto Gonzalez 409e2ac09d
Add `-duplicate` option to the `design` command. 2020-04-03 16:46:35 +00:00
Eddie Hung fdafb74eb7 kernel: use more ID::* 2020-04-02 07:14:08 -07:00
Eddie Hung 0d878ca256
Merge pull request #1832 from boqwxp/cleanup_passes_cmds_design 
Clean up pseudo-private member usage in `passes/cmds/design.cc`.
 2020-03-30 11:56:17 -07:00
Alberto Gonzalez 7fc0938bb6
Replace `RTLIL::id2cstr()` with `log_id()`. 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-03-30 16:50:36 +00:00
Alberto Gonzalez 4681f02a6e
Clean up pseudo-private member usage in `passes/cmds/design.cc`. 2020-03-28 05:10:18 +00:00
Rupert Swarbrick 044ca9dde4 Add support for SystemVerilog-style `define to Verilog frontend 
This patch should support things like

  `define foo(a, b = 3, c)   a+b+c

  `foo(1, ,2)

which will evaluate to 1+3+2. It also spots mistakes like

  `foo(1)

(the 3rd argument doesn't have a default value, so a call site is
required to set it).

Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.

Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.

Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
 2020-03-27 16:08:26 +00:00
Henner Zeller 3aa4484a3c Consistent use of 'override' for virtual methods in derived classes. 
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
 2018-07-20 23:51:06 -07:00
Clifford Wolf 0f217080cf Add "design -import" 2017-06-30 19:18:52 +02:00
Clifford Wolf b1cdf772eb Added "design -reset-vlog" 2016-11-30 11:25:55 +01:00
Clifford Wolf 84bf862f7c Spell check (by Larry Doolittle) 2015-08-14 10:56:05 +02:00
Clifford Wolf 6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf 04727c7e0f No implicit conversion from IdString to anything else 2014-08-02 18:58:40 +02:00
Clifford Wolf 14412e6c95 Preparations for RTLIL::IdString redesign: cleanup of existing code 2014-08-02 00:45:25 +02:00
Clifford Wolf e6d33513a5 Added module->design and cell->module, wire->module pointers 2014-07-31 14:11:39 +02:00
Clifford Wolf 1cb25c05b3 Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00
Clifford Wolf 10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
Clifford Wolf 483c99fe46 Added "design -push" and "design -pop" 2014-02-20 23:28:59 +01:00
Clifford Wolf 366dcd3abf Fixed use of "cmd_error" in passes/cmds/design.cc 2014-02-07 14:16:42 +01:00
Clifford Wolf cf593222f2 Added design -stash/-copy-from/-copy-to 2014-02-06 21:52:07 +01:00
Clifford Wolf 0f38008ed3 Added "design" command (-reset, -save, -load) 2013-07-27 14:27:51 +02:00