riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
13,488 Commits 89 Branches 49 Tags 38 MiB
Commit Graph

13488 Commits

Author SHA1 Message Date
Miodrag Milanovic 71f2540cd8 docs conf.py change Release -> Version 2024-05-07 15:55:52 +02:00
Miodrag Milanovic b4034a881e Keep docs version in conf.py 2024-05-07 15:35:25 +02:00
Miodrag Milanović 90dd508156
Merge pull request #4372 from YosysHQ/krys/docs_version_number 
Docs: Set release to YOSYS_VER
 2024-05-07 09:15:51 +02:00
Krystine Sherwin 6eb49ee9e8
Makefile: Export YOSYS_VER only for make docs 2024-05-07 10:23:22 +12:00
Emil J 68c7fc4c91
Merge pull request #4300 from YosysHQ/cellmatch 
cellmatch: New pass for picking out standard cells automatically
 2024-05-06 15:12:37 +02:00
Krystine Sherwin fe27240b3a
Makefile: Export YOSYS_VER 2024-05-04 16:51:38 +12:00
Krystine Sherwin bb0be8c7a2
Docs: Set release to YOSYS_VER 
If building from read the docs, and the current build is "latest", add `-dev` to the version string.
Requires `YOSYS_VER` to be exported by .readthedocs.yaml.
 2024-05-04 16:51:29 +12:00
github-actions[bot] 0f9ee20ea2 Bump version 2024-05-04 00:16:00 +00:00
Emil J. Tywoniak e939182e68 cellmatch: add comments 2024-05-03 16:42:41 +02:00
Martin Povišer b143e5678f cellmatch: Rename the special design to `$cellmatch` 2024-05-03 16:42:41 +02:00
Martin Povišer 913bc87c44 cellmatch: Add test 2024-05-03 16:42:41 +02:00
Martin Povišer c0e68dcc4d cellmatch: Add debug print 2024-05-03 16:42:41 +02:00
Martin Povišer 6a9858cdad cellmatch: Delegate evaluation to `ConstEval` 2024-05-03 16:42:41 +02:00
Martin Povišer 86e1080f05 cellmatch: New pass 2024-05-03 16:42:41 +02:00
Emil J 2631c7e918
Merge pull request #4365 from widlarizer/techmap-chtype-test 
techmap: add dynamic cell type test
 2024-05-03 16:25:42 +02:00
Emil J. Tywoniak a833f05036 techmap: add dynamic cell type test 2024-05-03 13:53:49 +02:00
Martin Povišer 6ff4ecb2b4 techmap: Remove `techmap_chtype` from the result 2024-05-03 13:33:28 +02:00
Martin Povišer fc82251105 techmap: Support dynamic cell types 2024-05-03 13:33:28 +02:00
github-actions[bot] dd2195543b Bump version 2024-04-30 00:17:14 +00:00
Martin Povišer 640d6a5127
Merge pull request #4359 from georgerennie/aiger_parse_bug 
read_aiger: Fix incorrect read of binary Aiger without outputs
 2024-04-29 15:15:43 +02:00
George Rennie 4e6deb53b6 read_aiger: Fix incorrect read of binary Aiger without outputs 
* Also makes all ascii parsing finish reading lines and adds a small
  test
 2024-04-29 14:06:58 +01:00
N. Engelhardt 34d9a7451e
Merge pull request #4333 from YosysHQ/fix_hierarchy_generate 
fix hierarchy -generate mode handling of cells
 2024-04-25 09:56:24 +02:00
KrystalDelusion c3ae33da33
Merge pull request #4285 from YosysHQ/typo_fixup 
Typo fixing
 2024-04-25 09:54:48 +12:00
Martin Povišer cd1fb8b157
Merge pull request #4350 from jix/read_rtlil_performance 
rtlil: Add packed `extract` implementation for `SigSpec`
 2024-04-24 14:07:28 +02:00
github-actions[bot] cf02f86c28 Bump version 2024-04-24 00:16:06 +00:00
Martin Povišer 982a22da5e
Merge pull request #4351 from povik/bump-abc 
Bump abc
 2024-04-23 14:20:54 +02:00
Martin Povišer 67c7062fb8 Bump abc for a fix once more 2024-04-23 13:50:45 +02:00
Martin Povišer c167d9b76e Bump abc for one more fix 2024-04-23 11:41:20 +02:00
Martin Povišer 6d6aa4d35e Bump abc to cherry-pick a WASM build fix 2024-04-22 17:43:41 +02:00
Martin Povišer 4a666d3ba8 Bump abc 2024-04-22 16:39:42 +02:00
Martin Povišer 178eceb32d rtlil: Replace the packed `SigSpec::extract` impl 2024-04-22 16:23:51 +02:00
Jannis Harder 0d30a4d479 rtlil: Add packed `extract` implementation for `SigSpec` 
Previously `extract` on a `SigSpec` would always unpack it. Since a
significant amount of `SigSpec`s have one or few chunks, it's worth
having a dedicated implementation.

This is especially true, since the RTLIL frontend calls into this for
every `wire [lhs:rhs]` slice, making this `extract` take up 40% when
profiling `read_rtlil` with one of the largest coarse grained RTLIL
designs I had on hand.

With this change the `read_rtlil` profile looks like I would expect it
to look like, but I noticed that a lot of the other core RTLIL methods
also are a bit too eager with unpacking or implementing
`SigChunk`/`Const` overloads that just convert to a single chunk
`SigSpec` and forward to the implementation for that, when a direct
implementation would avoid temporary std::vector allocations. While not
relevant for `read_rtlil`, to me it looks like there might be a few easy
overall performance gains to be had by addressing this more generally.
 2024-04-22 13:26:17 +02:00
Martin Povišer 171577f909
Merge pull request #4340 from gadfort/abc-lib-merge 
add support for using ABCs library merging when providing multiple liberty files
 2024-04-17 22:01:20 +02:00
github-actions[bot] 4897e89547 Bump version 2024-04-17 00:16:15 +00:00
Miodrag Milanović 52c04f3029
Merge pull request #4341 from YosysHQ/mmicko/ci_update 
Add new verific testing environment CI
 2024-04-16 08:30:03 +02:00
Miodrag Milanovic c38bbd7824 Add new verific testing environment CI 2024-04-16 07:50:50 +02:00
github-actions[bot] 40e8f5b69d Bump version 2024-04-16 00:15:48 +00:00
Miodrag Milanović e78c38b556
Merge pull request #4339 from YosysHQ/mmicko/lib_as_attribute 
verific: expose library name as module attribute
 2024-04-15 20:25:49 +02:00
Jannis Harder 1527cc84c4
Merge pull request #4338 from jix/fix-formalff-setundef-srst 
formalff -setundef: Fix handling for has_srst FFs
 2024-04-15 18:34:07 +02:00
Miodrag Milanovic af94123730 verific: expose library name as module attribute 2024-04-15 17:01:07 +02:00
Jannis Harder 2bd889a59a formalff -setundef: Fix handling for has_srst FFs 
The `has_srst`` case was checking `sig_ce` instead of `sig_srst` due to
a copy and paste error.

This would crash when `has_ce` was false and could incorrectly determine
that an initial value is unused when `has_ce` and `has_srst` are both
set.
 2024-04-15 11:53:30 +02:00
Miodrag Milanović 7bb2746208
Merge pull request #4334 from YosysHQ/docs_tidy 
Strip compilation date from doc outputs
 2024-04-15 08:27:41 +02:00
Krystine Sherwin 73d021562f
Docs: Rename source/temp to source/generated 2024-04-15 10:13:22 +12:00
Krystine Sherwin 953f5bbe6c
Docs: Remove end-before tag for yosys-abc 2024-04-15 09:50:46 +12:00
Martin Povišer b827b9862f
Merge pull request #4265 from povik/iattr_help 
memory_map: Explain `-iattr` better
 2024-04-13 18:13:58 +02:00
Martin Povišer 4a8cdfabbb
Merge pull request #4169 from povik/clean-opt_clean-step2 
opt_clean: Remove dead assertion
 2024-04-13 18:12:40 +02:00
github-actions[bot] ed46453cfc Bump version 2024-04-13 00:14:07 +00:00
Krystine Sherwin b3024289c6
Docs: Force read_verilog to avoid verific header 2024-04-13 11:33:04 +12:00
Krystine Sherwin 1d7b7ddfd7
Docs: Skip footer in logs 2024-04-13 11:29:11 +12:00
Krystine Sherwin d4b6042e43
Makefile: Separate docs/usage stderr and stdout 2024-04-13 11:20:36 +12:00