Commit Graph

1543 Commits

Author SHA1 Message Date
Xiretza c6681508f1 verilog: fix leaking of type names in parser 2021-06-14 13:56:51 -04:00
Xiretza b57e47fad8 verilog: fix wildcard port connections leaking memory 2021-06-14 13:56:51 -04:00
Xiretza 62a42c317c ast: delete wires and localparams after finishing const evaluation 2021-06-14 13:56:51 -04:00
Xiretza 091295a5a5 verilog: fix leaking ASTNodes 2021-06-14 13:56:51 -04:00
Xiretza 9ca5a91724 ast: fix error condition causing assert to fail
type2str returns a string that doesn't start with $ or \, so it can't be
assigned to an IdString.
2021-06-14 13:56:51 -04:00
Marcelina Kościelnicka 801ecc0e1d verilog: Squash a memory leak.
That was added in ecc22f7fed
2021-06-14 17:07:41 +02:00
Claire Xen 55e8f5061a
Merge pull request #2817 from YosysHQ/claire/fixemails
Fixing old e-mail addresses and deadnames
2021-06-09 13:22:52 +02:00
Zachary Snow 2e697f5655 verilog: check for module scope identifiers during width detection
The recent fix for case expression width detection causes the width of
the expressions to be queried before they are simplified. Because the
logic supporting module scope identifiers only existed in simplify,
looking them up would fail during width detection. This moves the logic
to a common helper used in both simplify() and detectSignWidthWorker().
2021-06-08 15:03:16 -04:00
Zachary Snow c79fbfe0a1 mem2reg: tolerate out of bounds constant accesses
This brings the mem2reg behavior in line with the nomem2reg behavior.
2021-06-08 15:02:57 -04:00
Claire Xenia Wolf 72787f52fc Fixing old e-mail addresses and deadnames
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
2021-06-08 00:39:36 +02:00
Zachary Snow 8cfed1a979 sv: support tasks and functions within packages 2021-06-01 13:17:41 -04:00
Zachary Snow 0795b3ec07 verilog: fix case expression sign and width handling
- The case expression and case item expressions are extended to the
  maximum width among them, and are only interpreted as signed if all of
  them are signed
- Add overall width and sign detection for AST_CASE
- Add sign argument to genWidthRTLIL helper
- Coverage for both const and non-const case statements
2021-05-25 16:16:46 -04:00
Zachary Snow 15f35d6754 sv: support remaining assignment operators
- Add support for: *=, /=, %=, <<=, >>=, <<<=, >>>=
- Unify existing support for: +=, -=, &=, |=, ^=
2021-05-25 16:15:57 -04:00
Rupert Swarbrick 3421979f00 Change the type of current_module to Module
The current_module global is needed so that genRTLIL has somewhere to
put cells and wires that it generates as it makes sense of expressions
that it sees. However, that doesn't actually need to be an AstModule:
the Module base class is enough.

This patch should cause no functional change, but the point is that
it's now possible to call genRTLIL with a module that isn't an
AstModule as "current_module". This will be needed for 'bind' support.
2021-05-13 23:44:48 -04:00
Rupert Swarbrick 51ed4a7149 Use range-based for loop in AST::process
No functional change: just get rid of the explicit iterator and
replace (*it)-> with child->. It's even the same number of characters,
but is hopefully a little easier to read.
2021-05-13 23:37:27 -04:00
Zachary Snow 4452080861 sv: check validity of package end label 2021-05-10 14:37:32 -04:00
Marcelina Kościelnicka 32a0ce9d68 blif: Use library cells' start_offset and upto for wideports.
Fixes #2729.
2021-05-08 15:50:03 +02:00
Claire Xenia Wolf 58290c0c77 Remove duplicates from conns array in JSON front-end, fixes #2736 2021-04-26 16:32:12 +02:00
Zachary Snow ba2ff1ea98 verilog: revise hot comment warnings 2021-03-30 09:21:18 -04:00
Marcelina Kościelnicka 0505c604e7 preproc: Fix up conditional handling.
Fixes #2710.
Fixes #2711.
2021-03-30 02:29:26 +02:00
Zachary Snow c58bb1d2e1 ast: make design available to process_module() 2021-03-24 10:21:00 -04:00
Xiretza 92d5550a90 verilog: check entire user type stack for type definition 2021-03-21 19:35:13 -04:00
Zachary Snow 4f4e70876f sv: allow typenames as function return types 2021-03-19 12:08:43 -04:00
Xiretza 0c66141ed2 verilog: rebuild user_type_stack from globals before parsing file
This was actually a ticking UB bomb: after running the parser, the type
maps contain pointers to children of the current AST, which is
recursively deleted after the pass has executed. This leaves the
pointers in user_type_stack dangling, which just happened to never be a
problem due to another bug that causes typedefs from higher-level type
maps to never be considered.

Rebuilding the type stack from the design's globals ensures the AstNode
pointers are valid.
2021-03-18 20:52:36 -04:00
Marcelina Kościelnicka 8740fdf1d7 ast: Use better parameter serialization for paramod names.
Calling log_signal is problematic for several reasons:

- with recent changes, empty string is serialized as { }, which violates
  the "no spaces in IdString" rule
- the type (plain / real / signed / string) is dropped, wrongly conflating
  functionally different values and potentially introducing a subtle
  elaboration bug

Instead, use a custom simple serialization scheme.
2021-03-18 00:52:00 +01:00
Zachary Snow f71c2dcca6 sv: carry over global typedefs from previous files
This breaks the ability to use a global typename as a standard
identifier in a subsequent input file. This is otherwise backwards
compatible, including for sources which previously included conflicting
typedefs in each input file.
2021-03-17 15:53:52 -04:00
Xiretza 092e923330 verilog: fix buf/not primitives with multiple outputs
From IEEE1364-2005, section 7.3 buf and not gates:

> These two logic gates shall have one input and one or more outputs.
> The last terminal in the terminal list shall connect to the input of the
> logic gate, and the other terminals shall connect to the outputs of
> the logic gate.

yosys does not follow this and instead interprets the first argument as
the output, the second as the input and ignores the rest.
2021-03-17 11:44:03 -04:00
Zachary Snow 4f187d53c5 verilog: support module scope identifiers in parametric modules 2021-03-16 11:01:30 -04:00
Marcelina Kościelnicka 3d9698153f json: Add support for memories.
Previously, memories were silently discarded by the JSON backend, making
round-tripping modules with them crash.

Since there are already some users using JSON to implement custom
external passes that use memories (and infer width/size from memory
ports), let's fix this by just making JSON backend and frontend support
memories as first-class objects.

Processes are still not supported, and will now cause a hard error.

Fixes #1908.
2021-03-15 17:19:19 +01:00
Zachary Snow 640b9927fa sv: allow globals in one file to depend on globals in another
This defers the simplification of globals so that globals in one file
may depend on globals in other files. Adds a simplify() call downstream
because globals are appended at the end.
2021-03-12 11:22:41 -05:00
Zachary Snow cb9f3b6abf verilog: disallow overriding global parameters
It was previously possible to override global parameters on a
per-instance basis. This could be dangerous when using positional
parameter bindings, hiding oversupplied parameters.
2021-03-11 12:36:51 -05:00
whitequark 26e01a67db
Merge pull request #2643 from zachjs/fix-param-no-default-log
Fix param without default log line
2021-03-08 16:36:03 -08:00
Marcelina Kościelnicka 89c74ffd71 verilog: Use proc memory writes in the frontend. 2021-03-08 20:16:29 +01:00
Marcelina Kościelnicka 4e03865d5b Add support for memory writes in processes. 2021-03-08 20:16:29 +01:00
Zachary Snow bdc4fd0e92 Fix param without default log line 2021-03-07 16:06:25 -05:00
whitequark 9bb839c613
Merge pull request #2626 from zachjs/param-no-default
sv: support for parameters without default values
2021-03-07 05:48:03 -08:00
whitequark 72ae15c77c
Merge pull request #2632 from zachjs/width-limit
verilog: impose limit on maximum expression width
2021-03-07 03:45:41 -08:00
Zachary Snow b1a8e73a60 sv: fix some edge cases for unbased unsized literals
- Fix explicit size cast of unbased unsized literals
- Fix unbased unsized literal bound directly to port
- Output `is_unsized` flag in `dumpAst`
2021-03-06 15:20:34 -05:00
Zachary Snow c18ddbcd82 verilog: impose limit on maximum expression width
Designs with unreasonably wide expressions would previously get stuck
allocating memory forever.
2021-03-04 15:20:52 -05:00
Claire Xen 6c56c083f8
Update README 2021-03-04 16:43:30 +01:00
Zachary Snow d738b2c127 sv: support for parameters without default values
- Modules with a parameter without a default value will be automatically
  deferred until the hierarchy pass
- Allows for parameters without defaults as module items, rather than
  just int the `parameter_port_list`, despite being forbidden in the LRM
- Check for parameters without defaults that haven't been overriden
- Add location info to parameter/localparam declarations
2021-03-02 10:43:53 -05:00
Zachary Snow 10a6bc9b81 verilog: fix sizing of ports with int types in module headers
Declaring the ports as standard module items already worked as expected.
This adds a missing usage of `checkRange()` so that headers such as
`module m(output integer x);` now work correctly.
2021-03-01 13:39:05 -05:00
Zachary Snow 1ec5994100 verilog: fix handling of nested ifdef directives
- track depth so we know whether to consider higher-level elsifs
- error on unmatched endif/elsif/else
2021-03-01 12:28:33 -05:00
Claire Xen 004b780b8a
Merge pull request #2523 from tomverbeure/define_synthesis
Add -nosynthesis flag for read_verilog command
2021-03-01 18:00:48 +01:00
whitequark ca5f5ffcd6
Merge pull request #2615 from zachjs/genrtlil-conflict
genrtlil: improve name conflict error messaging
2021-03-01 08:10:19 -08:00
Zachary Snow 0f5b646ab8 sv: extended support for integer types
- Standard data declarations can now use any integer type
- Parameters and localparams can now use any integer type
- Function returns types can now use any integer type
- Fix `parameter logic`, `localparam reg`, etc. to be 1 bit (previously 32 bits)
- Added longint type (64 bits)
- Unified parser source for integer type widths
2021-02-28 16:31:56 -05:00
Zachary Snow bbff844acd genrtlil: improve name conflict error messaging 2021-02-26 18:08:23 -05:00
Michael Singer 04b41ed04a Implement $countones, $isunknown and $onehot{,0} 2021-02-26 12:28:58 -05:00
Michael Singer 8434ba5a3b Implement $countbits function 2021-02-26 12:28:58 -05:00
Zachary Snow 22bed38540 Extend simplify() recursion warning 2021-02-26 12:11:23 -05:00