yosys

mirror of https://github.com/YosysHQ/yosys.git

Author	SHA1	Message	Date
Clifford Wolf	5f1fea08d5	Add inout ports to cells_xtra.v Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-10-04 11:30:55 +02:00
Tim Ansell	ad975fb694	xilinx: Adding missing inout IO port to IOBUF	2018-10-03 16:38:32 -07:00
Clifford Wolf	ff5c61b120	Added black box modules for all the 7-series design elements (as listed in ug953)	2016-03-19 11:09:10 +01:00