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4511 Commits

Author SHA1 Message Date
Clifford Wolf d45379936b Progress in pmgen 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-15 11:23:25 +01:00
Clifford Wolf 1f8e76f993 Progress in pmgen 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-15 11:23:25 +01:00
Clifford Wolf b9545aa0e1 Progress in pmgen 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-15 11:23:25 +01:00
Clifford Wolf ad69c668ce Add mockup .pmg (pattern matcher generator) file 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-15 11:23:25 +01:00
Clifford Wolf e70ebe557c Add optional nullstr argument to log_id() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-15 11:06:48 +01:00
Clifford Wolf 6c5049f016 Fix handling of $shiftx in Verilog back-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-15 10:55:27 +01:00
Clifford Wolf 1d82a88e94
Merge pull request #788 from whitequark/master 
Document $tribuf and some gates
 2019-01-15 09:52:01 +01:00
Clifford Wolf 0994cfce7b
Merge pull request #787 from whitequark/flowmap_relax 
flowmap: implement depth relaxation
 2019-01-15 09:50:58 +01:00
whitequark fc2dd7ec8e manual: document some gates. 2019-01-14 16:17:25 +00:00
whitequark 7a45122168 manual: explain $tribuf cell. 2019-01-14 16:08:58 +00:00
Clifford Wolf 2a2e0a4722 Improve igloo2 example 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-08 20:16:36 +01:00
whitequark e792bd56b7 flowmap: clean up terminology. 
* "map": group gates into LUTs;
  * "pack": replace gates with LUTs.

This is important because we have FlowMap and DF-Map, and currently
our messages are ambiguous.

Also clean up some other log messages while we're at it.
 2019-01-08 02:05:06 +00:00
whitequark 211c26a4c9 flowmap: implement depth relaxation. 2019-01-08 01:13:05 +00:00
Clifford Wolf f042559e9d Fix typo in manual 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-07 10:07:28 +01:00
Clifford Wolf 8a63fc51d3 Bugfix in $memrd sharing 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-07 10:04:47 +01:00
Clifford Wolf dbd51d7bda
Merge pull request #782 from whitequark/flowmap_dfs 
flowmap: construct a max-volume max-flow min-cut, not just any one
 2019-01-07 09:47:57 +01:00
Clifford Wolf b5f6e786ea Switch "bugpoint" from system() to run_command() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-07 09:45:21 +01:00
Clifford Wolf d35858078d
Merge pull request #783 from whitequark/bugpoint 
bugpoint: new pass
 2019-01-07 09:42:17 +01:00
whitequark a342d6db49 bugpoint: new pass. 
A typical use of `bugpoint` would involve a script with a pass under
test, e.g.:

    flowmap -relax -optarea 100

and would be invoked as:

    bugpoint -yosys ./yosys -script flowmap.ys -clean -cells

This replaces the current design with the minimal design that still
crashes the `flowmap.ys` script.

`bugpoint` can also be used to perform generic design minimization
using `select`, e.g. the following script:

    select i:* %x t:$_MUX_ %i -assert-max 0

would remove all parts of the design except for an unbroken path from
an input to an output port that goes through exactly one $_MUX_ cell.
(The condition is inverted.)
 2019-01-07 03:13:19 +00:00
whitequark 8b44198e23 flowmap: construct a max-volume max-flow min-cut, not just any one. 2019-01-06 19:51:37 +00:00
Clifford Wolf a2c51d50fb
Merge pull request #780 from phire/rename_from_wire 
Rename cells based on the wires they drive.
 2019-01-06 11:35:31 +01:00
Scott Mansell 62c90c4e17 Rename cells based on the wires they drive. 2019-01-06 19:00:16 +13:00
Clifford Wolf f589ce86ba Add skeleton Yosys-Libero igloo2 example project 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-05 17:02:01 +01:00
Clifford Wolf 17ceab92a9 Bugfix in Verilog string handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-05 12:10:24 +01:00
whitequark 2fcc1ee72e flowmap: add -minlut option, to allow postprocessing with opt_lut. 2019-01-04 21:18:03 +00:00
Clifford Wolf e041ae3c6d
Merge pull request #777 from mmicko/achronix_cell_sim_fix 
Fix cells_sim.v for Achronix FPGA
 2019-01-04 15:18:18 +01:00
Miodrag Milanovic 50ef4561d4 Fix cells_sim.v for Achronix FPGA 2019-01-04 15:15:23 +01:00
Clifford Wolf 6d1e7e9403 Remove -m32 Verific eval lib build instructions 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-04 15:03:49 +01:00
Clifford Wolf 7a2db03aa7
Merge pull request #776 from mmicko/unify_noflatten 
Unify usage of noflatten among architectures
 2019-01-04 14:56:04 +01:00
Clifford Wolf f5d23d4c7a Update Verific default path 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-04 14:44:35 +01:00
whitequark 9bc5cf0844 flowmap: cleanup for clarity. NFCI. 2019-01-04 13:04:20 +00:00
Miodrag Milanovic 3b17c9018a Unify usage of noflatten among architectures 2019-01-04 11:37:25 +01:00
whitequark fd21564deb flowmap: improve debug graph output. NFC. 2019-01-04 03:30:04 +00:00
whitequark 7850a0c28a flowmap: add link to longer version of paper. NFC. 2019-01-04 02:33:10 +00:00
Clifford Wolf d98fe8ce1f
Merge pull request #775 from whitequark/opt_flowmap 
flowmap: new techmap pass
 2019-01-03 17:03:18 +01:00
whitequark 07af772a72 flowmap: new techmap pass. 2019-01-03 14:28:19 +00:00
Clifford Wolf 0fc6e2bfcf
Merge pull request #770 from whitequark/opt_expr_cmp 
opt_expr: refactor and improve simplification of comparisons
 2019-01-02 17:34:04 +01:00
whitequark bf8db55ef3 opt_expr: improve simplification of comparisons with large constants. 
The idea behind this simplification is that a N-bit signal X being
compared with an M-bit constant where M>N and the constant has Nth
or higher bit set, it either always succeeds or always fails.

However, the existing implementation only worked with one-hot signals
for some reason. It also printed incorrect messages.

This commit adjusts the simplification to have as much power as
possible, and fixes other bugs.
 2019-01-02 15:45:28 +00:00
Clifford Wolf 56ca1e6afc
Merge pull request #755 from Icenowy/anlogic-dram-init 
anlogic: implement DRAM initialization
 2019-01-02 16:28:18 +01:00
Clifford Wolf b236faffa1 Merge branch 'master' of github.com:YosysHQ/yosys 2019-01-02 15:53:50 +01:00
Clifford Wolf 979de95cf6
Merge pull request #750 from Icenowy/anlogic-ff-init 
Initialization of Anlogic DFFs
 2019-01-02 15:52:22 +01:00
Clifford Wolf 2e606b1802
Merge pull request #773 from whitequark/opt_lut_elim_fixes 
opt_lut: elimination fixes
 2019-01-02 15:45:29 +01:00
Clifford Wolf da1c8d8d3d
Merge pull request #772 from whitequark/synth_lut 
synth: add k-LUT mode
 2019-01-02 15:44:57 +01:00
Clifford Wolf 00330c741a
Merge pull request #771 from whitequark/techmap_cmp2lut 
cmp2lut: new techmap pass
 2019-01-02 15:43:10 +01:00
Clifford Wolf 1eb101a38a Improve VerificImporter support for writes to asymmetric memories 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-02 15:33:43 +01:00
Clifford Wolf 50b09de033 Fix VerificImporter asymmetric memories error message 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-02 15:05:23 +01:00
Clifford Wolf 16bb823db8
Merge pull request #769 from whitequark/typos 
Fix typographical and grammatical errors and inconsistencies
 2019-01-02 14:47:18 +01:00
whitequark efa278e232 Fix typographical and grammatical errors and inconsistencies. 
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.
 2019-01-02 13:12:17 +00:00
whitequark c55dfb8369 opt_lut: reflect changes in sigmap. 
Otherwise, some LUTs will be missed during elimination.
 2019-01-02 10:21:58 +00:00
whitequark 06143ab33f opt_lut: use a worklist, and revisit cells affected by elimination. 2019-01-02 09:36:32 +00:00