Kristoffer Ellersgaard Koch
30c762d3a1
Fix all warnings that occurred when compiling with gcc9
2019-05-08 10:27:14 +02:00
Clifford Wolf
c582a25bdb
Merge pull request #998 from mdaiter/get_bool_attribute_opts
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Minor optimization to get_attribute_bool
2019-05-08 08:34:35 +02:00
Matthew Daiter
6e629d2895
Minor optimization to get_attribute_bool
2019-05-07 22:04:28 -05:00
Matthew Daiter
bafbb9ee90
Optimize ceil_log2 function
2019-05-07 12:17:56 -05:00
Clifford Wolf
87426f5a06
Improve write_verilog specify support
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-04 08:46:24 +02:00
Eddie Hung
d9c4644e88
Merge remote-tracking branch 'origin/master' into clifford/specify
2019-05-03 15:05:57 -07:00
Udi Finkelstein
ac10e7d96d
Initial implementation of elaboration system tasks
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(IEEE1800-2017 section 20.11)
This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block.
This is very useful to stop a synthesis of a parametrized block when an
illegal combination of parameters is chosen.
2019-05-03 03:10:43 +03:00
Clifford Wolf
9268cd1613
Fix performance bug in RTLIL::SigSpec::operator==(), fixes #970
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 15:19:10 +02:00
Oleg Endo
4f15e7f00f
fix codestyle formatting
2019-04-29 19:20:33 +09:00
Oleg Endo
e531fb203a
escape spaces with backslash when writing dep file
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filenames are sparated by spaces in the dep file. if a filename in the
dep file contains spaces they must be escaped, otherwise the tool that
reads the dep file will see multiple wrong filenames.
2019-04-29 16:13:34 +09:00
Clifford Wolf
64925b4e8f
Improve $specrule interface
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 22:57:10 +02:00
Clifford Wolf
4575e4ad86
Improve $specrule interface
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 22:18:04 +02:00
Clifford Wolf
71c38d9de5
Add $specrule cells for $setup/$hold/$skew specify rules
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
e807e88b60
Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
aec2475a9d
Add CellTypes support for $specify2 and $specify3
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
e1d73e03d3
Add InternalCellChecker support for $specify2 and $specify3
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
3cc95fb4be
Add specify parser
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
David Shah
742c2f245d
Fixes for OAI4 cell implementation
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Fixes #955 and the underlying issue in #954
Signed-off-by: David Shah <dave@ds0.me>
2019-04-23 17:54:00 +01:00
Eddie Hung
2c6358ea25
Remove kernel/cost.cc since master has refactored it
2019-04-22 11:21:17 -07:00
Eddie Hung
4883391b63
Merge remote-tracking branch 'origin/master' into xaig
2019-04-22 11:19:52 -07:00
Clifford Wolf
e158ea2097
Add log_debug() framework
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-22 17:25:52 +02:00
Clifford Wolf
99d5435650
Merge pull request #905 from christian-krieg/feature/python_bindings
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Feature/python bindings
2019-04-22 14:47:52 +02:00
Eddie Hung
caec7f9d2c
Merge remote-tracking branch 'origin/master' into xaig
2019-04-20 12:23:49 -07:00
Clifford Wolf
5b915f0153
Add "wbflip" command
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 11:04:46 +02:00
Eddie Hung
290a798cec
Ignore 'whitebox' attr in flatten with "-wb" option
2019-04-18 10:32:00 -07:00
Eddie Hung
c997a77014
Ignore 'whitebox' attr in flatten with "-wb" option
2019-04-18 10:19:45 -07:00
Eddie Hung
8fe0a961b3
Merge remote-tracking branch 'origin/clifford/whitebox' into xaig
2019-04-18 09:00:06 -07:00
Clifford Wolf
f4abc21d8a
Add "whitebox" attribute, add "read_verilog -wb"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-18 17:45:47 +02:00
Eddie Hung
bca3cf6843
Merge branch 'master' into xaig
2019-04-08 16:31:59 -07:00
Clifford Wolf
dfb242c905
Add "read_ilang -lib"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-05 17:31:49 +02:00
Benedikt Tutzer
827a96d3a3
Global lists in rtlil.cc are now static objects
2019-04-03 14:27:39 +02:00
Benedikt Tutzer
0774a500d4
Added support for changing Yosys namespace
2019-04-03 12:21:21 +02:00
Benedikt Tutzer
072c939380
Fixed identation
2019-04-01 13:36:01 +02:00
Benedikt Tutzer
03d1606b42
Merge remote-tracking branch 'origin/master' into feature/python_bindings
2019-03-28 12:16:39 +01:00
Clifford Wolf
3b796c033c
Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signals
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-23 14:38:48 +01:00
Clifford Wolf
370db33a4c
Add fmcombine pass
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-15 20:46:17 +01:00
Clifford Wolf
76c9c350e7
Add hashlib "<container>::element(int n)" methods
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-14 22:04:42 +01:00
Clifford Wolf
1cd04a6838
Fix a bug in handling quotes in multi-cmd lines in Yosys scripts
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-12 21:15:11 +01:00
Clifford Wolf
20c6a8c9b0
Improve determinism of IdString DB for similar scripts
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-11 20:12:28 +01:00
Clifford Wolf
d9bb5f3637
Add ENABLE_GLOB Makefile switch
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-11 01:08:36 -07:00
Eddie Hung
f7c7003a19
Merge remote-tracking branch 'origin/master' into xaig
2019-02-26 13:16:03 -08:00
Eddie Hung
3ea0161ae7
Add IdString::ends_with()
2019-02-26 12:04:16 -08:00
Clifford Wolf
c521f4632f
Merge pull request #819 from YosysHQ/clifford/optd
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Rename "yosys -D" to "yosys -U", add "yosys -D" with expected behavior
2019-02-22 06:55:48 +01:00
Eddie Hung
a8803a1519
Merge remote-tracking branch 'origin/master' into xaig
2019-02-21 11:23:00 -08:00
Clifford Wolf
0a6588569b
Rename "yosys -U" to "yosys -P" to avoid confusion about "undefine"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 15:51:59 +01:00
Clifford Wolf
953e0bf88d
Rename "yosys -D" to "yosys -U", add "yosys -D" with expected behavior
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 14:27:46 +01:00
Clifford Wolf
246391200e
Add FF support to wreduce
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 16:36:42 +01:00
Eddie Hung
edf7267019
Refactor kernel/cost.h definition into cost.cc
2019-02-08 13:58:20 -08:00
Clifford Wolf
e70ebe557c
Add optional nullstr argument to log_id()
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-15 11:06:48 +01:00
whitequark
efa278e232
Fix typographical and grammatical errors and inconsistencies.
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The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.
DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint
More hits were found by looking through comments and strings manually.
2019-01-02 13:12:17 +00:00
whitequark
18291c20d2
proc_clean: remove any empty cases if all cases use all-def compare.
2018-12-23 09:04:30 +00:00
whitequark
2ca237e086
tcl: add support for passing arguments to scripts.
2018-12-20 07:32:24 +00:00
Clifford Wolf
e90195b737
Improve ConstEval error handling for non-eval cell types
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-29 05:07:40 +01:00
Jon Burgess
6732e56632
Avoid assert when label is an empty string
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Calling back() on an empty string is not allowed and triggers
an assert with recent gcc:
$ cd manual/PRESENTATION_Intro
$ ../../yosys counter.ys
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/usr/include/c++/8/bits/basic_string.h:1136: std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::reference std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::back() [with _CharT = char; _Traits = std::char_traits<char>; _Alloc = std::allocator<char>; std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::reference = char&]: Assertion '!empty()' failed.
802 if (label.back() == ':' && GetSize(label) > 1)
(gdb) p label
$1 = ""
2018-10-28 14:57:04 +00:00
whentze
9ed77f5ba8
fix unhandled std::out_of_range when calling yosys with 3-character argument
2018-10-22 19:40:22 +02:00
Ruben Undheim
c50afc4246
Documentation improvements etc.
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- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)
2018-10-13 20:34:44 +02:00
Ruben Undheim
458a94059e
Support for 'modports' for System Verilog interfaces
2018-10-12 21:11:48 +02:00
Ruben Undheim
75009ada3c
Synthesis support for SystemVerilog interfaces
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This time doing the changes mostly in AST before RTLIL generation
2018-10-12 21:11:36 +02:00
Adrian Wheeldon
1355492c89
Fix IdString M in setup_stdcells()
2018-10-04 15:36:26 +01:00
Benedikt Tutzer
6f8abc1143
Exposed generator script to make-process
2018-09-19 10:32:34 +02:00
Miodrag Milanovic
c5e9034834
Fix Cygwin build and document needed packages
2018-09-19 10:16:53 +02:00
Benedikt Tutzer
604734b484
added functions whose definitions are split over multiple lines
2018-08-23 14:48:20 +02:00
Benedikt Tutzer
586d7df7e2
added default yosys license text
2018-08-23 14:39:44 +02:00
Benedikt Tutzer
ba18e0f81a
Fixed segfault / multiple free issue with lists
2018-08-23 13:57:37 +02:00
Benedikt Tutzer
0ecfffa69c
Do not pass heap object to Python. This way they should be completely managed by Python and destroyed when out of scope. Also, the file in which a function/struct was found is added to the comment before the function
2018-08-22 14:42:42 +02:00
Benedikt Tutzer
60608a86bb
Fixed Identation
2018-08-22 11:59:22 +02:00
Benedikt Tutzer
038caab4e0
Wrapped functions that use unsigned int or type_t as types
2018-08-21 15:25:43 +02:00
Benedikt Tutzer
4acb29db0c
added operators <, == and !=
2018-08-21 14:49:35 +02:00
Benedikt Tutzer
334bfce4c4
Added previousely missed functions
2018-08-21 13:15:08 +02:00
Benedikt Tutzer
29efc9d0b1
Deleted duplicate Destructor
2018-08-21 11:07:59 +02:00
Benedikt Tutzer
95d65971f3
added some checks if python is enabled to make sure everything compiles if python is disabled in the makefile
2018-08-20 16:04:43 +02:00
Benedikt Tutzer
d41c68ee5a
The share directory cannot be searched when used as a Python library, only in shell mode
2018-08-20 15:27:50 +02:00
Benedikt Tutzer
6d18837d62
Python passes are now looked for in share/plugins and can be added by specifying a relative or absolute path
2018-08-20 15:11:06 +02:00
Benedikt Tutzer
5864db3c2b
Fixed issue when using a python plugin in the yosys shell
2018-08-20 14:44:03 +02:00
Benedikt Tutzer
d79a2808cf
Python Passes can now be added with the -m option or with the plugin command. There are still issues when run in shell mode, but they can be used just fine in a python script
2018-08-16 16:00:11 +02:00
Clifford Wolf
67b1026297
Merge pull request #591 from hzeller/virtual-override
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Consistent use of 'override' for virtual methods in derived classes.
2018-08-15 14:05:38 +02:00
litghost
80d7e007ff
Map .eblif extension as blif.
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Signed-off-by: litghost <537074+litghost@users.noreply.github.com>
2018-08-13 14:02:53 -07:00
Benedikt Tutzer
bf7b73acfc
Added Wrappers for:
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-IdString
-Const
-CaseRule
-SwitchRule
-SyncRule
-Process
-SigChunk
-SigBit
-SigSpec
With all their member functions as well as the remaining member
functions for Cell, Wire, Module and Design and static functions of
rtlil.h
2018-08-13 15:18:46 +02:00
Benedikt Tutzer
416946a16a
Saving id and pointer to c++ object. Object is valid only if both id and pointer match the pair saved in the corresponding map in kernel/rtlil.cc. Otherwise, the object was destroyed in c++ and should not be accessed any more
2018-08-01 10:57:57 +02:00
Benedikt Tutzer
79d7e608cf
Setup is called automatically when the module is loaded, shutdown when python exits
2018-08-01 10:57:46 +02:00
Benedikt Tutzer
57d2197703
Cleaned up comments
2018-08-01 10:57:41 +02:00
Henner Zeller
3aa4484a3c
Consistent use of 'override' for virtual methods in derived classes.
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o Not all derived methods were marked 'override', but it is a great
feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00
Henner Zeller
1a60126a34
Provide source-location logging.
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o Provide log_file_warning() and log_file_error() that prefix the log
message with <filename>:<lineno>: to be easily picked up by IDEs that
need to step through errors.
o Simplify some duplicate logging code in kernel/log.cc
o Use the new log functions in genrtlil.
2018-07-19 10:22:02 -07:00
Benedikt Tutzer
0371519c39
Added Monitor class that can monitor all changes in a Design or in a Module
2018-07-10 12:51:02 +02:00
Benedikt Tutzer
e7d3f3cd46
added destructors for wires and cells
2018-07-10 08:52:36 +02:00
Benedikt Tutzer
55df7fff19
removed debug output
2018-07-09 16:02:10 +02:00
Benedikt Tutzer
da8083dbd0
commands can now be run on arbitrary designs, not only on the active one
2018-07-09 16:01:56 +02:00
Benedikt Tutzer
8ebaeecd83
multiple designs can now exist independent from each other. Cells/Wires/Modules can now move to a different parent without referencing issues
2018-07-09 15:48:06 +02:00
Benedikt Tutzer
7911379d4a
Introduced namespace and removed class-prefixes to increase readability
2018-06-28 15:07:21 +02:00
Benedikt Tutzer
ccb4dcd013
changed references from hash-ids to IdString names
2018-06-28 14:44:28 +02:00
Benedikt Tutzer
a27fa1833e
added wrappers for Design, Modules, Cells and Wires
2018-06-25 17:08:29 +02:00
Robert Ou
0abe7c6c77
Modify emscripten main to mount nodefs and to run arg as a script
2018-05-18 22:53:52 -07:00
Robert Ou
bd87462b47
Fix reading techlibs under emscripten
2018-05-18 22:42:33 -07:00
Christian Krämer
c1ecb1b2f1
Add "#ifdef __FreeBSD__"
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(Re-commit e3575a8
with corrected author field)
2018-05-13 13:08:26 +02:00
Clifford Wolf
1167538d26
Revert "Add "#ifdef __FreeBSD__""
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This reverts commit e3575a86c5
.
2018-05-13 13:06:36 +02:00
Johnny Sorocil
e3575a86c5
Add "#ifdef __FreeBSD__"
2018-05-05 13:02:44 +02:00
Clifford Wolf
5c03aeac60
Add "yosys -e regex" for turning warnings into errors
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-04 15:27:28 +02:00
Clifford Wolf
0acea3548b
Set stack size to at least 128 MB (large stack needed for parsing huge expressions)
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-27 15:04:10 +02:00
Edmond Cote
64ea55056a
Rename rename to renames
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Create TCL alias for rename command. Using renames. Following the same convention as proc -> procs.
2018-03-20 15:50:50 -07:00
Larry Doolittle
82fecc98c0
Harmonize uses of _WIN32 macro
2018-03-11 16:01:30 +01:00
Clifford Wolf
e5534a080e
Improve handling of warning messages
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-04 22:35:59 +01:00
Clifford Wolf
2935e8ea41
Update copyright header
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-04 21:31:10 +01:00
Clifford Wolf
eb67a7532b
Add $allconst and $allseq cell types
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-23 13:14:47 +01:00
Clifford Wolf
82c436587c
Do not create deep backtraces unless in ENABLE_DEBUG mode
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-03 15:04:39 +01:00
Clifford Wolf
a96c775a73
Add support for "yosys -E"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-07 16:36:13 +01:00
Clifford Wolf
c80315cea4
Bugfix in hierarchy handling of blackbox module ports
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-05 13:28:45 +01:00
Clifford Wolf
76afff7ef6
Add RTLIL::Const::is_fully_ones()
2017-12-14 02:06:39 +01:00
Clifford Wolf
96ad688849
Add SigSpec::is_fully_ones()
2017-12-14 01:29:09 +01:00
Kevin Kiningham
7350f7692a
Use quote includes for yosys.h
2017-12-13 13:27:52 -08:00
Clifford Wolf
9ae25039fb
Add support for editline as replacement for readline
2017-11-08 02:55:00 +01:00
Clifford Wolf
13eb47c692
Add src arguments to all cell creator helper functions
2017-09-09 10:16:48 +02:00
Clifford Wolf
8a66bd30c6
Update more stuff to use get_src_attribute() and set_src_attribute()
2017-09-01 12:26:55 +02:00
Jason Lowdermilk
71d43cfc08
Merge remote-tracking branch 'upstream/master'
2017-08-30 11:47:06 -06:00
Jason Lowdermilk
271e8ba7cd
fix indent level
2017-08-30 11:46:41 -06:00
Clifford Wolf
8530333439
Add {get,set}_src_attribute() methods on RTLIL::AttrObject
2017-08-30 11:39:11 +02:00
Jason Lowdermilk
32c0f1193e
Add support for source line tracking through synthesis phase
2017-08-29 14:46:35 -06:00
Clifford Wolf
d3b3dd8e88
Add hashlib support for hashing of pools
2017-08-22 13:04:33 +02:00
Clifford Wolf
bce0bb6e43
Add consteval support for $_ANDNOT_ and $_ORNOT_
2017-08-22 13:04:05 +02:00
Clifford Wolf
4ba5bd12c6
Add Const methods is_fully_zero(), is_fully_def(), and is_fully_undef()
2017-08-18 11:40:08 +02:00
Clifford Wolf
159701962a
Auto-detect JSON front-end
2017-08-09 13:28:52 +02:00
Clifford Wolf
2336d5508b
Add log_warning_noprefix() API, Use for Verific warnings and errors
2017-07-27 12:17:04 +02:00
Clifford Wolf
493fedbaf9
Add "using std::get" to yosys.h
2017-07-25 14:52:34 +02:00
Clifford Wolf
c251e3a576
Change intptr_t to uintptr_t in hashlib.h
2017-07-18 17:38:19 +02:00
Robert Ou
f0741698fa
Fix build warnings for win64
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Win64 has a 32-bit long. Use intptr_t to work on any data model.
2017-07-17 12:36:43 -07:00
Clifford Wolf
1f517d2b96
Fix history namespace collision
2017-06-20 05:26:12 +02:00
Clifford Wolf
c0ca99483c
Store command history when terminating with an error
2017-06-20 04:41:58 +02:00
Clifford Wolf
05df3dbee4
Add "setundef -anyseq"
2017-05-28 11:59:05 +02:00
Clifford Wolf
662a047815
Enable readline and tcl in mxe builds
2017-05-17 20:46:22 +02:00
Clifford Wolf
6934b862d3
Add missing AndnotGate() and OrnotGate() declarations to rtlil.h
2017-05-17 19:10:57 +02:00
Clifford Wolf
05cdd58c8d
Add $_ANDNOT_ and $_ORNOT_ gates
2017-05-17 09:08:29 +02:00
Clifford Wolf
fcb274a564
Add ConstEval defaultval feature
2017-04-05 11:25:22 +02:00
Clifford Wolf
b8d7f57f61
Add front-end detection for *.tcl files
2017-03-28 12:13:58 +02:00
Clifford Wolf
5f1d0b1024
Add $live and $fair cell types, add support for s_eventually keyword
2017-02-25 10:36:39 +01:00
Clifford Wolf
c6d8d70109
Fix mingw compile issue (2nd attempt)
2017-02-23 14:21:02 +01:00
Clifford Wolf
0822b21844
Fix mingw compile issue (maybe.. I can't test it)
2017-02-23 13:59:02 +01:00
Clifford Wolf
e6d56d23b5
Fix eval implementation of $_NOR_
2017-02-16 12:17:03 +01:00
Clifford Wolf
828303791b
Add "yosys -w" for suppressing warnings
2017-02-12 11:11:00 +01:00
Clifford Wolf
63dfdb5d7f
Add log_wire() API
2017-02-11 11:08:36 +01:00
Clifford Wolf
aab58045a8
Fix undef propagation bug in $pmux SAT model
2017-02-05 22:43:33 +01:00
Clifford Wolf
3928482a3c
Add $cover cell type and SVA cover() support
2017-02-04 14:14:26 +01:00
Clifford Wolf
b54972c112
Fix RTLIL::Memory::start_offset initialization
2017-01-25 17:00:59 +01:00
Clifford Wolf
6b2c23c721
Bugfix in RTLIL::SigSpec::remove2()
2016-12-31 16:14:42 +01:00
Clifford Wolf
33a22f8768
Simplified log_spacer() code
2016-12-23 02:06:46 +01:00
Clifford Wolf
a0dff87a57
Added "yosys -W regex"
2016-12-22 23:41:44 +01:00
Clifford Wolf
f144adec58
Added AIGER back-end to automatic back-end detection
2016-12-21 10:16:47 +01:00
Clifford Wolf
00761de1b7
Bugfix in comment handling
2016-12-13 13:48:09 +01:00
Clifford Wolf
a926a6afc2
Remember global declarations and defines accross read_verilog calls
2016-11-15 12:42:43 +01:00
Clifford Wolf
fa535c0b00
Some minor build fixes for Visual C
2016-10-14 18:36:02 +02:00
Clifford Wolf
bdc316db50
Added $anyseq cell type
2016-10-14 15:24:03 +02:00
Clifford Wolf
53655d173b
Added $global_clock verilog syntax support for creating $ff cells
2016-10-14 12:33:56 +02:00
Clifford Wolf
8ebba8a35f
Added $ff and $_FF_ cell types
2016-10-12 01:18:39 +02:00
Clifford Wolf
59508c99b4
define PATH_MAX if not defined by limits.h
2016-10-11 12:12:09 +02:00
Clifford Wolf
cb7dbf4070
Improvements in assertpmux
2016-09-07 12:42:16 +02:00
Clifford Wolf
6f41e5277d
Removed $aconst cell type
2016-08-30 19:09:56 +02:00
Clifford Wolf
eae390ae17
Removed $predict again
2016-08-28 21:35:33 +02:00
Clifford Wolf
23afeadb5e
Fixed handling of transparent bram rd ports on ROMs
2016-08-27 17:06:22 +02:00
Clifford Wolf
f8a77abfac
Added glob support to all front-ends
2016-08-22 15:05:57 +02:00
William D. Jones
5299b17056
Add MSYS2-compatible build.
2016-08-16 14:41:59 -04:00
Clifford Wolf
5767e4bc4d
Use _Exit(0) on win32, always use _Exit(1) in log_error()
2016-08-16 09:38:54 +02:00
Clifford Wolf
39da8eddae
Added log_const() API
2016-08-09 19:56:10 +02:00
Yury Gribov
f7730d43bb
Use /proc/self/exe on Cygwin as well.
2016-08-08 12:00:27 +02:00
Clifford Wolf
8d88fcb270
Added SatGen support for $anyconst
2016-07-27 15:52:20 +02:00
Clifford Wolf
9540be1d45
Removed $predict support from SatGen
2016-07-27 15:44:11 +02:00
Clifford Wolf
4056312987
Added $anyconst and $aconst
2016-07-27 15:41:22 +02:00
Clifford Wolf
a7b0769623
Added "read_verilog -dump_rtlil"
2016-07-27 15:40:17 +02:00
Clifford Wolf
8537c4d206
Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell()
2016-07-25 16:39:25 +02:00
Clifford Wolf
b1c432af56
Improvements in CellEdgesDatabase
2016-07-24 17:21:53 +02:00
Clifford Wolf
f162b858f2
Added CellEdgesDatabase API
2016-07-24 13:59:57 +02:00
Clifford Wolf
89deb412c6
Added satgen initstate support
2016-07-22 10:28:45 +02:00
Clifford Wolf
5c166e76e5
Added $initstate cell type and vlog function
2016-07-21 14:23:22 +02:00
Clifford Wolf
d7763634b6
After reading the SV spec, using non-standard predict() instead of expect()
2016-07-21 13:34:33 +02:00
Clifford Wolf
721f1f5ecf
Added basic support for $expect cells
2016-07-13 16:56:17 +02:00
Ruben Undheim
a8200a773f
A few modifications after pull request comments
...
- Renamed Design::packages to Design::verilog_packages
- No need to include ast.h in rtlil.h
2016-06-18 14:23:38 +02:00
Ruben Undheim
178ff3e7f6
Added support for SystemVerilog packages with localparam definitions
2016-06-18 10:53:55 +02:00
Clifford Wolf
ebece2b8d5
Added $sop SAT model
2016-06-17 17:47:30 +02:00
Clifford Wolf
95757efb25
Improved support for $sop cells
2016-06-17 16:31:16 +02:00
Clifford Wolf
52bb1b968d
Added $sop cell type and "abc -sop"
2016-06-17 13:50:09 +02:00
Clifford Wolf
864eeadcd9
Added missing "#define HASHLIB_H"
2016-05-14 11:43:20 +02:00
Clifford Wolf
570014800a
Include <cmath> in yosys.h
2016-05-08 10:50:39 +02:00
Clifford Wolf
f103bfb9ba
Fixes for MXE build
2016-05-07 10:53:18 +02:00
Clifford Wolf
9aa4b3309c
Added "yosys -D ALL"
2016-04-24 17:12:34 +02:00
Clifford Wolf
0bc95f1e04
Added "yosys -D" feature
2016-04-21 23:28:37 +02:00
Clifford Wolf
a07f893a5f
Minor hashlib bugfix
2016-04-16 23:20:11 +02:00
Clifford Wolf
ace462237f
Hashlib indenting fix
2016-04-05 13:25:23 +02:00
Clifford Wolf
2553319081
Added ScriptPass helper class for script-like passes
2016-03-31 11:16:34 +02:00
Clifford Wolf
6f1b6dc322
Added log_dump() support for dict<> and pool<> containers
2016-03-31 09:57:44 +02:00
Clifford Wolf
0db53284fd
We have 2016 for a while now
2016-03-30 13:52:26 +02:00
Clifford Wolf
48dbc75bed
Added .vhd file extension support
2016-03-30 13:24:49 +02:00
Clifford Wolf
95784437ac
Merge pull request #137 from ravenexp/master
...
Embed DATDIR make variable value into yosys binary.
2016-03-28 16:54:23 +02:00
Sebastian Kuzminsky
73870c1edf
fix a cut-n-paste error in the -h help
2016-03-26 11:15:35 -06:00
Sergey Kvachonok
963c0d2525
Embed DATDIR make variable value into yosys binary.
...
Use it as the last resort in the share/ directory location search.
2016-03-26 11:16:53 +03:00
Clifford Wolf
45af4a4acf
Use easyer-to-read unoptimized ceil_log2()
...
see here for details on the optimized version:
http://svn.clifford.at/handicraft/2016/esbmc/ceilog2.c
2016-02-15 23:06:18 +01:00
Clifford Wolf
0c4b311242
Fixed more visual studio warnings
2016-02-14 09:35:25 +01:00
Clifford Wolf
bcc873b805
Fixed some visual studio warnings
2016-02-13 17:31:24 +01:00
Clifford Wolf
0d7fd2585e
Added "int ceil_log2(int)" function
2016-02-13 16:52:16 +01:00
Clifford Wolf
ba407da187
Added addBufGate module method
2016-02-02 11:26:07 +01:00
Clifford Wolf
01bcc5663f
SigMap performance improvement
2016-02-01 10:10:20 +01:00
Clifford Wolf
ea492abcf0
hashlib mfp<> performance improvements
2016-02-01 10:03:03 +01:00
Clifford Wolf
13e15a24a2
Added reserve() method to haslib classes and
...
calculate hashtable size based on entries capacity, not size
2016-01-31 22:50:34 +01:00
Rick Altherr
3c48de8e21
rtlil: Improve performance of SigSpec::extract(SigSpec, SigSpec*)
...
Converting to a pool<SigBit> is fairly expensive due to inserts somewhat
frequently causing rehashing. Instead, walk through the pattern SigSpec
directly on a chunk-by-chunk basis and apply it to this SigSpec's
individual bits. Using chunks for the pattern minimizes the number of
iterations in the outer loop.
2016-01-31 09:20:16 -08:00
Rick Altherr
0265d7b100
rtlil: speed up SigSpec::sort_and_unify()
...
std::set<> internally is often a red-black tree which is fairly
expensive to create but fast to lookup. In the case of
sort_and_unify(), a set<> is constructed as a temporary object to
attempt to speed up lookups. Being a temporarily, however, the cost of
creation far outweights the lookup improvement and is a net performance
loss. Instead, sort the vector<> that already exists and then apply
std::unique().
2016-01-31 09:20:16 -08:00
Rick Altherr
89dc40f162
rtlil: improve performance of SigSpec::replace(SigSpec, SigSpec, SigSpec*)
2016-01-31 09:20:16 -08:00
Rick Altherr
cd3e1095b0
rtlil: improve performance of SigSpec::remove2(SigSpec, SigSpec*)
2016-01-31 09:20:16 -08:00
Clifford Wolf
5462399c88
Meaningless coding style change
2016-01-31 16:12:35 +01:00
Rick Altherr
43756559d8
rtlil: rewrite remove2() to avoid copying
2016-01-30 00:28:07 -08:00
Rick Altherr
12ebdef17c
rtlil: duplicate remove2() for std::set<>
2016-01-29 23:06:40 -08:00
Rick Altherr
9e26147ccd
rtlil: change IdString comparison operators to take references instead of copies
2016-01-29 23:06:40 -08:00
Clifford Wolf
33a5b28e25
Added default values for hashlib at() methods
2015-12-02 20:41:57 +01:00
Clifford Wolf
276101f032
Re-added SigMap::allbits()
2015-11-30 19:43:52 +01:00
Clifford Wolf
6459e3ac39
Removed dangling ';' in rtlil.h
2015-11-26 18:11:34 +01:00
Clifford Wolf
1e32e4bdae
Improved SigMap performance
2015-10-28 11:21:55 +01:00
Clifford Wolf
e69efec588
Improvements in new SigMap
2015-10-28 00:39:53 +01:00
Clifford Wolf
f3db70d2f3
Removed old SigMap implementation
2015-10-27 15:09:44 +01:00
Clifford Wolf
09b4050f2e
Added hashlib::mfp and new SigMap
2015-10-27 15:04:47 +01:00
Clifford Wolf
d014ba2d0e
Major refactoring of equiv_struct
2015-10-25 19:31:29 +01:00
Clifford Wolf
207736b4ee
Import more std:: stuff into Yosys namespace
2015-10-25 19:30:49 +01:00
Clifford Wolf
da923c198e
Added "equiv_add -cell"
2015-10-25 14:35:40 +01:00
Clifford Wolf
7f110e7018
renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()
2015-10-24 22:56:40 +02:00
Clifford Wolf
a1c3df7fe4
Fixed driver conflict handling (various cmds)
2015-10-24 19:23:30 +02:00
Clifford Wolf
6fe48cf41e
equiv_purge bugfix, using SigChunk in Yosys namespace
2015-10-24 19:09:45 +02:00
Clifford Wolf
2a0f577f83
Fixed handling of driver-driver conflicts in wreduce
2015-10-24 13:44:35 +02:00
Clifford Wolf
281a033e92
Added support for ":" as comment symbol after ;-parsing
2015-10-23 20:08:33 +02:00
Clifford Wolf
5d1c0ce7c0
Progress on cell help messages
2015-10-17 02:35:19 +02:00
Clifford Wolf
7d3a3a3173
Added first help messages for cell types
2015-10-14 16:27:42 +02:00
Clifford Wolf
924d9d6e86
Added read-enable to memory model
2015-09-25 12:23:11 +02:00
Clifford Wolf
d212d4d0c1
Cosmetic fix in Module::addLut()
2015-09-18 21:55:12 +02:00
Andrei Errapart
522176c946
Removed unnecessary cast.
2015-09-01 12:40:36 +02:00
Andrei Errapart
09176bcf3f
Microsoft Visual C++ fixes in hashlib; template specializations on int32_t and int64_t.
2015-09-01 12:40:24 +02:00
Andrei Errapart
744a5333f5
Microsoft Visual C++ fix for log.h.
2015-09-01 12:40:12 +02:00
Clifford Wolf
ee8f6f31f4
Added SigMap::allbits()
2015-08-31 16:42:19 +02:00
Clifford Wolf
ff50bc2ac3
Added $tribuf and $_TBUF_ cell types
2015-08-16 12:54:52 +02:00
Clifford Wolf
84bf862f7c
Spell check (by Larry Doolittle)
2015-08-14 10:56:05 +02:00
Clifford Wolf
bc468cb6f2
Fixed hashlib for 64 bit int keys
2015-08-12 13:37:09 +02:00
Clifford Wolf
45ee2ba3b8
Fixed handling of [a-fxz?] in decimal constants
2015-08-11 11:32:37 +02:00
Clifford Wolf
8d6d5c30d9
Added WORDS parameter to $meminit
2015-07-31 10:40:09 +02:00
Clifford Wolf
6c84341f22
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
Clifford Wolf
caa274ada6
Added design->rename(module, new_name)
2015-06-30 01:37:59 +02:00
Clifford Wolf
99100f367d
Added "rename -top new_name"
2015-06-17 09:38:56 +02:00
Clifford Wolf
ea23bb8aa4
Added "write_smv" skeleton
2015-06-15 00:46:27 +02:00
Clifford Wolf
4c733301e6
Fixed cstr_buf for std::string with small string optimization
2015-06-11 13:39:49 +02:00
Clifford Wolf
3a6abc9bf6
Improvements in cellaigs.cc and "json -aig"
2015-06-11 10:48:16 +02:00
Clifford Wolf
1ae360cf72
AigMaker refactoring
2015-06-10 23:00:12 +02:00
Clifford Wolf
e534881794
Added "json -aig"
2015-06-10 08:13:56 +02:00
Clifford Wolf
85287295b2
Fixed cellaigs port extending
2015-06-10 07:16:30 +02:00
Clifford Wolf
66f9ee412a
Added "aig" pass
2015-06-09 22:33:26 +02:00
Clifford Wolf
e49e2662aa
Added cellaigs API
2015-06-09 09:54:22 +02:00
Clifford Wolf
de4f4dad3c
Fixed "avail_parameters" handling in module clone/copy
2015-06-08 14:49:34 +02:00
Clifford Wolf
98650a0609
Added log_dump() support for IdStrings
2015-06-08 14:49:02 +02:00
Clifford Wolf
2cc4e75914
Added read_blif command
2015-05-17 15:25:03 +02:00
Clifford Wolf
61512b6f41
Verific build fixes
2015-05-17 08:19:52 +02:00
Clifford Wolf
f483dce7c2
Added $eq/$neq -> $logic_not/$reduce_bool optimization
2015-04-29 07:28:15 +02:00
Clifford Wolf
49859393bb
Improved attributes API and handling of "src" attributes
2015-04-24 22:04:05 +02:00
Clifford Wolf
cfdc9fc50e
A "#" does start a comment, not a label.
2015-04-16 18:13:41 +02:00
Clifford Wolf
44519d4399
Added back-end auto-detect for .edif and .json
2015-04-09 15:37:54 +02:00
Clifford Wolf
25781e329b
Fixed const2big performance bug
2015-04-09 13:20:19 +02:00
Clifford Wolf
21a1cc1b60
Added support for "file names with blanks"
2015-04-08 12:14:34 +02:00
Clifford Wolf
aae5f2ca08
Added hashlib support for std::tuple<>
2015-04-07 17:23:30 +02:00
Clifford Wolf
b31e77fd06
Added pool<K>::pop()
2015-04-07 15:07:01 +02:00
Clifford Wolf
169d1c4711
Added support for initialized brams
2015-04-06 17:06:15 +02:00
Clifford Wolf
a1c62b79d5
Avoid parameter values with size 0 ($mem cells)
2015-04-05 18:04:19 +02:00
Clifford Wolf
706631225e
Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types
2015-04-05 09:45:14 +02:00
Clifford Wolf
c52a4cdeed
Added "dffinit", Support for initialized Xilinx DFF
2015-04-04 19:00:15 +02:00
Clifford Wolf
68bbb15214
Fixed detection of absolute paths in ABC for win32
2015-03-22 11:03:56 +01:00
Clifford Wolf
b005eedf36
Added $assume cell type
2015-02-26 18:04:10 +01:00
Clifford Wolf
9ae21263f0
Some cleanups in "clean"
2015-02-24 22:31:30 +01:00
Clifford Wolf
4e6ca7760f
Replaced ezDefaultSAT with ezSatPtr
2015-02-21 12:15:41 +01:00
Clifford Wolf
e0e6d130cd
YosysJS stuff
2015-02-19 13:36:54 +01:00
Clifford Wolf
f41378af8c
Fixed clang (svn trunk) warnings
2015-02-18 14:54:22 +01:00
Clifford Wolf
3e5e9a3889
More YosysJS stuff
2015-02-16 13:23:54 +01:00
Clifford Wolf
33e80b96c7
Added YosysJS wrapper
2015-02-16 12:41:48 +01:00
Clifford Wolf
8d45f81046
More emcc stuff
2015-02-15 17:15:29 +01:00
Clifford Wolf
3216f9420e
More emscripten stuff, Added example app
2015-02-15 12:09:30 +01:00
Clifford Wolf
dcf2e24240
Added $meminit support to "memory" command
2015-02-14 12:55:03 +01:00
Clifford Wolf
910556560f
Added $meminit cell type
2015-02-14 10:23:03 +01:00
Clifford Wolf
adf4ecbc1f
Some hashlib improvements
2015-02-09 20:11:51 +01:00
Clifford Wolf
a779a09771
Fixed creation of command reference in manual
2015-02-09 13:24:29 +01:00
Clifford Wolf
bcd8a2fc56
Fixed eval_select_op() api
2015-02-08 19:06:16 +01:00
Clifford Wolf
09ee65a050
Added eval_select_args() and eval_select_op()
2015-02-08 18:56:06 +01:00
Clifford Wolf
6d2f31c04a
Various ModIndex improvements
2015-02-08 14:23:12 +01:00
Clifford Wolf
05d4223fb6
Added SigSpec::has_const()
2015-02-08 00:01:51 +01:00
Clifford Wolf
dce1fae777
Added cell->known(), cell->input(portname), cell->output(portname)
2015-02-07 11:40:19 +01:00
Clifford Wolf
5b41470e15
Skip blackbox modules in design->selected_modules()
2015-02-03 23:12:23 +01:00
Clifford Wolf
8514fe79db
Added "yosys -L logfile"
2015-02-03 23:12:23 +01:00
Clifford Wolf
1df81f92ce
Added "make mklibyosys", some minor API changes
2015-02-01 13:38:46 +01:00
Clifford Wolf
9948ff2d8a
Added yosys_banner(), Updated Copyright range
2015-02-01 00:39:59 +01:00
Clifford Wolf
07326943e7
Added <algorithm> include to hashlib.h
2015-02-01 00:27:07 +01:00
Clifford Wolf
67218443be
Log msg change
2015-01-31 21:26:53 +01:00
Clifford Wolf
bc86b4a7e9
Added "equiv_induct -undef"
2015-01-31 13:58:04 +01:00
Clifford Wolf
e9cfc4a453
Added "equiv_simple -undef"
2015-01-31 13:06:41 +01:00
Clifford Wolf
f80f5b721d
Added "equiv_make -blacklist <file> -encfile <file>"
2015-01-31 12:08:20 +01:00
Clifford Wolf
cb9d0a414d
Synced RTLIL::unescape_id() to log_id() behavior
2015-01-30 22:51:16 +01:00
Clifford Wolf
aabd5097ed
More log_id() stuff
2015-01-30 22:22:52 +01:00
Clifford Wolf
114a78d11a
Some cleanups in log.cc
2015-01-30 22:12:26 +01:00
Clifford Wolf
13b50bacfe
Rethrow with "catch(...) throw;"
2015-01-25 22:57:09 +01:00
Clifford Wolf
2a9ad48eb6
Added ENABLE_NDEBUG makefile options
2015-01-24 12:16:46 +01:00
Clifford Wolf
8fe9ab50e5
Added #ifdef NDEBUG for log_assert()
2015-01-24 11:49:34 +01:00
Clifford Wolf
43951099cf
Added dict/pool.sort()
2015-01-24 00:13:27 +01:00
Clifford Wolf
a6aa32e762
Various equiv_simple improvements
2015-01-22 13:42:04 +01:00
Clifford Wolf
abf8398216
Progress in equiv_simple
2015-01-21 23:59:58 +00:00
Clifford Wolf
76c5d863c5
Added equiv_make command
2015-01-19 13:59:08 +01:00
Clifford Wolf
e13a45ae61
Added $equiv cell type
2015-01-19 11:55:05 +01:00
Clifford Wolf
0217ea0fb8
Added hashlib::idict<>
2015-01-18 12:12:33 +01:00
Clifford Wolf
b32ba6f568
Optimizing no-op cell->setPort()
2015-01-17 12:04:40 +01:00
Clifford Wolf
95f1eb9b87
Only enable code coverage counters on linux
2015-01-09 17:32:53 +01:00
Clifford Wolf
07703bdac4
fixed compiler warning on non-linux archs
2015-01-06 16:12:43 +01:00
Clifford Wolf
859e3e41e7
hashlib iterator fix
2015-01-06 16:05:00 +01:00
Clifford Wolf
9fb715dc74
build fix for mxe
2015-01-06 15:46:58 +01:00
Clifford Wolf
f9304e6c10
Print non-errors to stdout
2015-01-03 22:10:33 +01:00
Clifford Wolf
e62d838bd4
Removed SigSpec::extend_xx() api
2015-01-01 11:41:52 +01:00
Clifford Wolf
327a5d42b6
Progress in memory_bram
2014-12-31 22:50:08 +01:00
Clifford Wolf
94e6b70736
Added memory_bram (not functional yet)
2014-12-31 16:53:53 +01:00
Clifford Wolf
1e08621e7e
Added hashlib .count(key, iterator) and it1 < it2
2014-12-31 14:52:46 +01:00
Clifford Wolf
ba48b6b1e6
improved bitpattern (proc_mux) performance
2014-12-31 13:15:35 +01:00
Clifford Wolf
b9e412423a
hashlib cleanups and a fix
2014-12-31 13:05:33 +01:00
Clifford Wolf
12b05dfc04
gcc-4.6 compile fixes
2014-12-31 04:24:04 +01:00
Clifford Wolf
429ccb62a1
new hashlib::pool<> (derived from new dict)
2014-12-31 04:19:04 +01:00
Clifford Wolf
c4bd6cb9d3
major rewrite of hashlib::dict<>
2014-12-31 03:58:29 +01:00
Clifford Wolf
7d6a7fe2ce
IdString optimization
2014-12-31 03:56:09 +01:00
Clifford Wolf
60f16e17af
hotfix for ModInfo
2014-12-31 03:55:13 +01:00
Clifford Wolf
6fef4b82a2
using pool<> in bitpattern.h
2014-12-30 23:45:43 +01:00
Clifford Wolf
1909edfa9c
improved -v option
2014-12-30 22:54:42 +01:00
Clifford Wolf
50fff2b240
print timing details (-d) in -q mode
2014-12-30 22:31:04 +01:00
Clifford Wolf
0675098733
added hashlib::mkhash_init
2014-12-30 18:51:24 +01:00
Clifford Wolf
120a8313d9
Small optimization in hashlib
2014-12-30 13:30:22 +01:00
Clifford Wolf
3857e1cb66
Improvements in hashlib
2014-12-30 13:22:33 +01:00
Clifford Wolf
d72a666440
Put dummy reference to empty idstring in yosys_shutdown()
2014-12-29 21:26:15 +01:00
Clifford Wolf
2f1e6aa256
Improved free list management in hashlib
2014-12-29 20:24:28 +01:00
Clifford Wolf
7a4d5d1c0f
Less verbose ABC output
2014-12-29 15:17:40 +01:00
Clifford Wolf
0bb6b24c11
Added global yosys_celltypes
2014-12-29 14:30:33 +01:00
Clifford Wolf
ecd64182c5
Added "yosys -X"
2014-12-29 13:33:33 +01:00
Clifford Wolf
33e25394b4
Fixed comment parsing in Pass::call()
2014-12-29 04:23:19 +01:00
Clifford Wolf
7d843adef9
dict/pool changes in opt_clean
2014-12-29 04:06:52 +01:00
Clifford Wolf
662cb549e4
Added newline support to Pass::call() parser
2014-12-29 03:49:45 +01:00
Clifford Wolf
90bc71dd90
dict/pool changes in ast
2014-12-29 03:11:50 +01:00
Clifford Wolf
397ae5b697
gcc build fixes
2014-12-29 02:46:59 +01:00
Clifford Wolf
cfe0817697
Converting "share" to dict<> and pool<> complete
2014-12-29 02:01:42 +01:00
Clifford Wolf
a2226e5307
Added mkhash_xorshift()
2014-12-29 00:12:36 +01:00
Clifford Wolf
dede5353b1
Some changes to hashlib to make for better stl compatibility
2014-12-28 22:26:09 +01:00
Clifford Wolf
2ad131764f
Some cleanups
2014-12-28 21:43:14 +01:00
Clifford Wolf
8773fd5897
Added memhasher (yosys -M)
2014-12-28 21:27:51 +01:00
Clifford Wolf
137f35373f
Changed more code to dict<> and pool<>
2014-12-28 19:24:24 +01:00
Clifford Wolf
f3a97b75c7
Fixed performance bug in object hashing
2014-12-28 19:03:18 +01:00
Clifford Wolf
89723a45cf
Improved hashlib iterator implementation
2014-12-28 18:48:48 +01:00
Clifford Wolf
3da46d3437
Renamed hashmap.h to hashlib.h, some related improvements
2014-12-28 17:51:16 +01:00
Clifford Wolf
3e8e483233
Various improvements in ModIndex
2014-12-27 13:04:44 +01:00
Clifford Wolf
6c8b0a5fd1
More dict/pool related changes
2014-12-27 12:02:57 +01:00
Clifford Wolf
2c2f8e6e9f
Added memory statistics (at least on linux)
2014-12-27 11:25:51 +01:00
Clifford Wolf
d6ee6f653f
Better help message printing for command line tool
2014-12-27 11:01:59 +01:00
Clifford Wolf
66ab88d7b0
More hashtable finetuning
2014-12-27 03:04:50 +01:00
Clifford Wolf
88d08e8f24
Some cleanups in dict/pool hashtable implementation
2014-12-26 23:21:23 +01:00
Clifford Wolf
6ce6689b63
Using Yosys::dict and Yosys::pool in sigtools.h
2014-12-26 22:08:44 +01:00
Clifford Wolf
ec4751e55c
Replaced std::unordered_set (nodict) with Yosys::pool
2014-12-26 21:59:41 +01:00
Clifford Wolf
9e6fb0b02c
Replaced std::unordered_map as implementation for Yosys::dict
2014-12-26 21:35:22 +01:00
Clifford Wolf
e52d1f9b9a
Added new_dict (hashmap.h) and re-enabled code coverage counters
2014-12-26 19:28:52 +01:00
Clifford Wolf
e0c0011863
Temporary gcc 4.6 build hotfix for Yosys::dict and Yosys::nodict
2014-12-26 11:05:23 +01:00
Clifford Wolf
35f611e2f6
Added "yosys -d" command line option
2014-12-26 10:54:23 +01:00
Clifford Wolf
a6c96b986b
Added Yosys::{dict,nodict,vector} container types
2014-12-26 10:53:21 +01:00
Clifford Wolf
edb3c9d0c4
Renamed extend() to extend_xx(), changed most users to extend_u0()
2014-12-24 09:51:17 +01:00
Clifford Wolf
76fa527492
Added support for multiple clock domains to "abc" pass
2014-12-21 16:52:05 +01:00
Clifford Wolf
6cec188c52
Fixed build with gcc 4.6
2014-12-16 10:38:25 +01:00
Clifford Wolf
7775d2806f
Added IdString::destruct_guard hack
2014-12-11 21:46:36 +01:00
Clifford Wolf
032511fac8
Added functionality to dff2dffe pass
2014-12-08 15:38:58 +01:00
Clifford Wolf
7d6e586df8
Added bool constructors to SigBit and SigSpec
2014-12-08 15:08:02 +01:00
Clifford Wolf
bca2442c67
Added module->addDffe() and module->addDffeGate()
2014-12-08 14:59:38 +01:00
Clifford Wolf
f1764b4fe9
Added $dffe cell type
2014-12-08 10:50:19 +01:00
Clifford Wolf
fad9cec47b
Added $_DFFE_??_ cell types
2014-12-08 10:43:38 +01:00
Clifford Wolf
1e0f6b5ddb
Added "yosys -qq" to also quiet warning messages
2014-11-09 11:02:20 +01:00
Clifford Wolf
a112b10934
Introducing YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN
2014-11-09 10:55:04 +01:00
Clifford Wolf
fe829bdbdc
Added log_warning() API
2014-11-09 10:44:23 +01:00
Clifford Wolf
003336c58d
Use a cache for log_id() memory management
2014-11-08 12:38:22 +01:00
Clifford Wolf
89be7bf527
Added "used" attribute to entries in yosys_cover_list
...
http://www.reddit.com/r/yosys/comments/2kw479/fyi_clang_350_build_error/cltgwyc
http://llvm.org/bugs/show_bug.cgi?id=19474
2014-11-07 20:58:08 +01:00
Clifford Wolf
546e8b5fe7
Improved TopoSort determinism
2014-11-07 15:21:03 +01:00
Clifford Wolf
99cdfb3110
Fixed typo in "log_cmd_error_exception"
2014-11-07 12:48:15 +01:00
Clifford Wolf
a346c0bf2b
Made "cover" a compile-time option (disabled by default)
2014-11-06 09:39:55 +01:00
Clifford Wolf
269e37e969
Added support for empty lines to here documents
2014-10-29 09:05:17 +01:00
Clifford Wolf
70b2efdb05
Added support for $readmemh/$readmemb
2014-10-26 20:33:10 +01:00
Clifford Wolf
c5eb5e56b8
Re-introduced Yosys::readsome() helper function
...
(f.read() + f.gcount() made problems with lines > 16kB)
2014-10-23 10:58:36 +02:00
Clifford Wolf
3202ba621c
Merge pull request #40 from parvizp/compile_mac_10.9.2
...
Builds on Mac 10.9.2 with LLVM 3.5.
2014-10-19 18:40:22 +02:00
Parviz Palangpour
de8adb8ec5
Builds on Mac 10.9.2 with LLVM 3.5.
2014-10-19 11:14:43 -05:00
Clifford Wolf
6c1c1e9a07
Improved new_id() for win32
2014-10-18 19:26:03 +02:00
Clifford Wolf
0471d158d9
Various improvements to version reporting on win32
2014-10-18 19:00:52 +02:00
Clifford Wolf
6bcb4f1f45
Fixed shell prompt and proc_self_dirname() for win32
2014-10-18 16:51:50 +01:00
Clifford Wolf
84ffe04075
Fixed various VS warnings
2014-10-18 15:20:38 +02:00
Clifford Wolf
b3a6f8f530
More win32 (mxe and vs) build fixes
2014-10-17 16:04:59 +02:00
Clifford Wolf
468ae92374
Various win32 / vs build fixes
2014-10-17 14:01:47 +02:00
Clifford Wolf
4df902637a
Various MXE build fixes
2014-10-17 12:04:40 +02:00
William Speirs
31267a1ae8
Header changes so it will compile on VS
2014-10-17 11:41:36 +02:00
Clifford Wolf
34caeeb4f3
Fixed a few VS warnings
2014-10-17 06:02:38 +02:00
Clifford Wolf
3be5fa053f
Fixed RTLIL::SigSpec::parse() for out-of-range bit- and part-selects
2014-10-16 00:54:14 +02:00
Clifford Wolf
82ed814fa1
Replaced log_assert() do { ... } while (0) hack with a static inline function
2014-10-15 20:36:32 +02:00
Clifford Wolf
2355ddf75d
Fixed gcc warning
2014-10-15 02:48:51 +02:00
Clifford Wolf
3445a933a5
Fixed MXE build
2014-10-15 02:43:50 +02:00
Clifford Wolf
1fc6208ec0
Check for _YOSYS_ in yosys.h
2014-10-15 01:18:31 +02:00
Clifford Wolf
c3e9922b5d
Replaced readsome() with read() and gcount()
2014-10-15 01:12:53 +02:00
Clifford Wolf
cf85aab62f
A few indent fixes
2014-10-15 01:05:08 +02:00
William Speirs
9cb2303799
Made iterators extend std::iterator and added == operator
2014-10-15 00:56:37 +02:00
Clifford Wolf
069521e2d5
Define empty __attribute__ macro for non-gcc, non-clang compilers
2014-10-15 00:56:04 +02:00
William Speirs
0352dbfd65
Fixed log so it will compile under Visual Studio
...
- Included an implementation of gettimeofday
2014-10-15 00:48:59 +02:00
Clifford Wolf
0913e968f5
More win32/abc fixes
2014-10-12 14:48:19 +02:00
Clifford Wolf
1a7684be24
Various small fixes for non-win32 builds
2014-10-12 12:18:38 +02:00
Clifford Wolf
0b9282a779
Added make_temp_{file,dir}() and remove_directory() APIs
2014-10-12 12:11:57 +02:00
Clifford Wolf
b1596bc0e7
Added run_command() api to replace system() and popen()
2014-10-12 10:57:15 +02:00
Clifford Wolf
0dc249ccd7
Shrinked the copyright banner by 1 character
2014-10-11 11:59:35 +02:00
Clifford Wolf
8263f6a74a
Fixed win32 troubles with f.readsome()
2014-10-11 11:36:22 +02:00
Clifford Wolf
568fee5e74
Added proc_self_dirname() for win32
2014-10-11 11:08:52 +02:00
Clifford Wolf
53349fb634
Fixed ifdefs for plugin unloading
2014-10-11 10:57:46 +02:00
Clifford Wolf
df537a216b
Using next_token() to parse commands
2014-10-10 18:53:03 +02:00
Clifford Wolf
20d85f20db
Fixed next_token()
2014-10-10 18:38:40 +02:00
Clifford Wolf
2c683102be
Added next_token() function (strtok() replacement)
2014-10-10 18:33:55 +02:00
Clifford Wolf
986bcc13cb
Various win32 build fixes in yosys.cc
2014-10-10 18:20:17 +02:00
Clifford Wolf
ee5165c6e4
Moved patmatch() to yosys.cc
2014-10-10 18:20:17 +02:00
Clifford Wolf
774933a0d8
Replaced fnmatch() with patmatch()
2014-10-10 18:02:17 +02:00
Clifford Wolf
bbd808072b
Added format __attribute__ to stringf()
2014-10-10 17:22:08 +02:00
Clifford Wolf
7cb0d3aa1a
Renamed TRUE/FALSE to CONST_TRUE/CONST_FALSE because of name collision on Win32
2014-10-10 17:07:24 +02:00
Clifford Wolf
4569a747f8
Renamed SIZE() to GetSize() because of name collision on Win32
2014-10-10 17:07:24 +02:00
Clifford Wolf
c7f5aab625
Replaced "#ifdef WIN32" with "#ifdef _WIN32"
2014-10-09 17:00:54 +02:00
Clifford Wolf
fea11f0fa4
Added API for generic cell cost calculations
2014-10-09 13:59:26 +02:00
Clifford Wolf
d3405c15bf
No rusage on win32
2014-10-09 10:51:24 +02:00
Clifford Wolf
56c1d43408
satgen import sigbit api
2014-10-03 18:51:50 +02:00
Clifford Wolf
3e4b0cac8d
added resource sharing of $macc cells
2014-10-03 12:58:40 +02:00
Clifford Wolf
c3e779a65f
Added $_BUF_ cell type
2014-10-03 10:12:28 +02:00
Clifford Wolf
0b8cfbc6fd
Added support for "keep" on modules
2014-09-29 12:51:54 +02:00
Clifford Wolf
f9a307a50b
namespace Yosys
2014-09-27 16:17:53 +02:00
Clifford Wolf
edf11c635a
Assert on new logic loops in "share" pass
2014-09-21 12:57:33 +02:00
Clifford Wolf
00964f2f61
Initialize RTLIL::Const from std::vector<bool>
2014-09-19 15:50:55 +02:00
Clifford Wolf
fa96cf4a16
Added new CodingReadme file (replaces CodingStyle and CHECKLISTS)
2014-09-16 11:26:44 +02:00
Clifford Wolf
b470c480e9
Added the obvious optimizations to alumacc $macc generator
2014-09-15 12:22:03 +02:00
Clifford Wolf
2442eb3832
Fixed monitor notifications for removed cell
2014-09-14 17:04:39 +02:00
Clifford Wolf
7815f81c32
Added "synth" command
2014-09-14 16:09:06 +02:00
Clifford Wolf
fcb46138ce
Simplified $fa undef model
2014-09-08 16:59:39 +02:00
Clifford Wolf
af0c8873bb
Added $lcu cell type
2014-09-08 13:31:04 +02:00
Clifford Wolf
d46bac3305
Added "$fa" cell type
2014-09-08 12:15:39 +02:00
Clifford Wolf
98e6463ca7
Added $macc eval model
2014-09-06 19:44:28 +02:00
Clifford Wolf
fa64942018
Added $macc SAT model
2014-09-06 19:44:11 +02:00
Clifford Wolf
b847ec8a0b
Added $macc cell type
2014-09-06 15:47:46 +02:00
Ruben Undheim
79cbf9067c
Corrected spelling mistakes found by lintian
2014-09-06 08:47:06 +02:00
Clifford Wolf
8927aa6148
Removed $bu0 cell type
2014-09-04 02:07:52 +02:00
Clifford Wolf
b9cb483f3e
Using $pos models for $bu0
2014-09-03 21:20:59 +02:00
Clifford Wolf
50ac284823
Fixes in $alu SAT- and eval-models
2014-09-03 13:39:46 +02:00
Clifford Wolf
da360771a1
Create a default selection stack in RTLIL::Design::Design()
2014-09-02 22:49:24 +02:00
Clifford Wolf
c38283dbd0
Small bug fixes in $not, $neg, and $shiftx models
2014-09-02 17:48:41 +02:00
Clifford Wolf
2fcf66b91d
Added ConstEval model for $alu cells
2014-09-01 16:35:46 +02:00
Clifford Wolf
bae09dca2b
Added SAT model for $alu cells
2014-09-01 16:35:25 +02:00
Clifford Wolf
e07698818d
Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::data
2014-09-01 11:36:02 +02:00
Clifford Wolf
83ec3fa204
Fixed return size of const_*() eval functions
2014-08-31 18:08:26 +02:00
Clifford Wolf
be44157c0f
Added RTLIL::Const::size()
2014-08-31 18:07:48 +02:00
Clifford Wolf
a1c7d4a8e2
Added eval model for $lut cells
2014-08-31 17:43:31 +02:00
Clifford Wolf
0b6769af3f
Typo fixes in cell->*Param() API
2014-08-31 17:43:31 +02:00
Clifford Wolf
8649b57b6f
Added $lut support in test_cell, techmap, satgen
2014-08-31 17:43:31 +02:00
Clifford Wolf
2a1b08aeb3
Added design->scratchpad
2014-08-30 19:37:12 +02:00
Clifford Wolf
4724d94fbc
Added $alu cell type
2014-08-30 18:59:05 +02:00
Clifford Wolf
dfbd7dd15a
Fixed module->addPmux()
2014-08-30 18:17:22 +02:00
Clifford Wolf
eda603105e
Added is_signed argument to SigSpec.as_int() and Const.as_int()
2014-08-24 15:14:00 +02:00
Clifford Wolf
58367cd87a
Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore
2014-08-23 15:14:58 +02:00
Clifford Wolf
19cff41eb4
Changed frontend-api from FILE to std::istream
2014-08-23 15:03:55 +02:00
Clifford Wolf
5dce303a2a
Changed backend-api from FILE to std::ostream
2014-08-23 13:54:21 +02:00
Clifford Wolf
98442e019d
Added emscripten (emcc) support to build system and some build fixes
2014-08-22 16:20:22 +02:00
Clifford Wolf
a3494fa9ed
Added "plugin" command
2014-08-22 14:00:11 +02:00
Clifford Wolf
b37d70dfd7
Added mod->addGate() methods for new gate types
2014-08-19 14:26:54 +02:00
Clifford Wolf
aa7a3ed83f
Fixed proc_{self,share}_dirname error handling
2014-08-17 02:25:59 +02:00
Clifford Wolf
f3326a6421
Improved sig.remove2() performance
2014-08-17 02:16:56 +02:00
Clifford Wolf
9bacc0b54c
Added stackmap<> container
2014-08-17 00:56:47 +02:00
Clifford Wolf
410d043dd8
Renamed toposort.h to utils.h
2014-08-17 00:55:35 +02:00
Clifford Wolf
7f734ecc09
Added module->uniquify()
2014-08-16 23:50:36 +02:00
Clifford Wolf
47c2637a96
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
2014-08-16 18:29:39 +02:00
Clifford Wolf
56a30cf42c
Added CellTypes::cell_evaluable()
2014-08-16 16:17:07 +02:00
Clifford Wolf
dbdf89c705
Added log_spacer()
2014-08-16 15:34:00 +02:00
Clifford Wolf
b64b38eea2
Renamed $lut ports to follow A-Y naming scheme
2014-08-15 14:18:40 +02:00
Clifford Wolf
f092b50148
Renamed $_INV_ cell type to $_NOT_
2014-08-15 14:11:40 +02:00
Clifford Wolf
ca87116449
More idstring sort_by_* helpers and fixed tpl ordering in techmap
2014-08-15 02:40:46 +02:00
Clifford Wolf
8ff71b5ae5
Added Frontend "+/" filename syntax for files from proc_share_dir
2014-08-15 02:08:02 +02:00
Clifford Wolf
978a933b6a
Added RTLIL::SigSpec::to_sigbit_map()
2014-08-14 23:14:47 +02:00
Clifford Wolf
2f44d8ccf8
Added sig.{replace,remove,extract} variants for std::{map,set} pattern
2014-08-14 22:32:18 +02:00
Clifford Wolf
1bf7a18fec
Added module->ports
2014-08-14 16:22:52 +02:00
Clifford Wolf
746aac540b
Refactoring of CellType class
2014-08-14 15:46:51 +02:00
Clifford Wolf
13f2f36884
RIP $safe_pmux
2014-08-14 11:39:46 +02:00
Clifford Wolf
e5ac8fdf2b
Fixed SigBit(RTLIL::Wire *wire) constructor
2014-08-12 15:39:48 +02:00
Clifford Wolf
5215723c64
Another build fix by americanrouter (via reddit)
2014-08-11 15:55:41 +02:00
Clifford Wolf
0b8b8d41eb
Fixed build with gcc-4.6
2014-08-07 22:37:01 +02:00
Clifford Wolf
523df73145
Added support for truncating of wires to wreduce pass
2014-08-05 14:47:03 +02:00
Clifford Wolf
ebbbe7fc83
Added RTLIL::IdString::in(...)
2014-08-04 15:40:07 +02:00
Clifford Wolf
653edd7a2f
Added query() API to ModIndex
2014-08-03 15:00:38 +02:00
Clifford Wolf
75423169c5
Added ID() macro for static IdStrings
2014-08-03 14:59:13 +02:00
Clifford Wolf
bc947d4c7b
Fixed a va_list corruption in logv_error()
2014-08-02 21:54:30 +02:00
Clifford Wolf
b6acbc82e6
Bugfix in "techmap -extern"
2014-08-02 20:54:30 +02:00
Clifford Wolf
8e7361f128
Removed at() method from RTLIL::IdString
2014-08-02 19:08:02 +02:00
Clifford Wolf
04727c7e0f
No implicit conversion from IdString to anything else
2014-08-02 18:58:40 +02:00
Clifford Wolf
768eb846c4
More bugfixes related to new RTLIL::IdString
2014-08-02 18:14:21 +02:00
Clifford Wolf
08392aad8f
Limit size of log_signal buffer to 100 elements
2014-08-02 15:52:21 +02:00
Clifford Wolf
e590ffc84d
Improvements in new RTLIL::IdString implementation
2014-08-02 15:44:10 +02:00
Clifford Wolf
60f3dc9923
Implemented new reference counting RTLIL::IdString
2014-08-02 15:11:35 +02:00
Clifford Wolf
97ad0623df
Fixed memory corruption related to id2cstr()
2014-08-02 13:34:07 +02:00
Clifford Wolf
b9bd22b8c8
More cleanups related to RTLIL::IdString usage
2014-08-02 13:19:57 +02:00
Clifford Wolf
14412e6c95
Preparations for RTLIL::IdString redesign: cleanup of existing code
2014-08-02 00:45:25 +02:00
Clifford Wolf
75ffd1643c
Added logfile hash to statistics footer
2014-08-01 19:43:28 +02:00
Clifford Wolf
1e224506be
Added per-pass cpu usage statistics
2014-08-01 18:42:10 +02:00
Clifford Wolf
d13eb7e099
Added ModIndex helper class, some changes to RTLIL::Monitor
2014-08-01 17:14:32 +02:00
Clifford Wolf
97a17d39e2
Packed SigBit::data and SigBit::offset in a union
2014-08-01 15:25:42 +02:00
Clifford Wolf
32a1cc3efd
Renamed modwalker.h to modtools.h
2014-07-31 23:30:18 +02:00
Clifford Wolf
cdae8abe16
Renamed port access function on RTLIL::Cell, added param access functions
2014-07-31 16:38:54 +02:00
Clifford Wolf
b5a9e51b96
Added "trace" command
2014-07-31 15:02:16 +02:00
Clifford Wolf
cd9407404a
Added RTLIL::Monitor
2014-07-31 14:45:14 +02:00
Clifford Wolf
e6d33513a5
Added module->design and cell->module, wire->module pointers
2014-07-31 14:11:39 +02:00
Clifford Wolf
1cb25c05b3
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
2014-07-31 13:19:47 +02:00
Clifford Wolf
6166c76831
Added "yosys -A"
2014-07-31 01:05:27 +02:00
Clifford Wolf
e5c245df9d
Added "yosys -Q"
2014-07-31 00:53:21 +02:00
Clifford Wolf
2541489105
Added techmap CONSTMAP feature
2014-07-30 22:04:30 +02:00
Clifford Wolf
6400ae3648
Added write_file command
2014-07-30 19:59:29 +02:00
Clifford Wolf
3f0a5746ef
Using native ezSAT shift ops in satgen, fixed $shift and $shiftx SAT models
2014-07-30 18:37:17 +02:00
Clifford Wolf
45fd26b76e
Added "log_dump_val_worker(char *v)"
2014-07-30 15:58:21 +02:00
Clifford Wolf
a7c6b37abf
Added "kernel/yosys.h" and "kernel/yosys.cc"
2014-07-30 14:10:15 +02:00
Clifford Wolf
273383692a
Added "test_cell" command
2014-07-29 22:07:41 +02:00
Clifford Wolf
e6df25bf74
Renamed "write_autotest" to "test_autotb" and moved to passes/tests/
2014-07-29 21:12:50 +02:00
Clifford Wolf
03c96f9ce7
Added "techmap -map %{design-name}"
2014-07-29 16:35:13 +02:00
Clifford Wolf
397b00252d
Added $shift and $shiftx cell types (needed for correct part select behavior)
2014-07-29 16:35:13 +02:00
Clifford Wolf
3c45277ee0
Added wire->upto flag for signals such as "wire [0:7] x;"
2014-07-28 12:12:13 +02:00
Clifford Wolf
7bd2d1064f
Using log_assert() instead of assert()
2014-07-28 11:27:48 +02:00
Clifford Wolf
d86a25f145
Added std::initializer_list<> constructor to SigSpec
2014-07-28 10:52:58 +02:00
Clifford Wolf
f99495a895
Added cover() to all SigSpec constructors
2014-07-28 10:52:30 +02:00
Clifford Wolf
c4bdba78cb
Added proper Design->addModule interface
2014-07-27 21:12:09 +02:00
Clifford Wolf
5da343b7de
Added topological sorting to techmap
2014-07-27 16:43:39 +02:00
Clifford Wolf
0c86d6106c
Added SigPool::check(bit)
2014-07-27 15:38:02 +02:00
Clifford Wolf
ddd31a0b66
Small improvements in PerformanceTimer API
2014-07-27 15:14:02 +02:00
Clifford Wolf
d07a871d35
Improved performance of opt_const on large modules
2014-07-27 14:50:25 +02:00
Clifford Wolf
4be645860b
Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs
2014-07-27 14:47:48 +02:00
Clifford Wolf
cbc3a46a97
Added RTLIL::SigSpecConstIterator
2014-07-27 14:47:23 +02:00
Clifford Wolf
d878fcbdc7
Added log_cmd_error_expection
2014-07-27 12:05:50 +02:00
Clifford Wolf
675cb93da9
Added RTLIL::Module::wire(id) and cell(id) lookup functions
2014-07-27 11:18:31 +02:00
Clifford Wolf
0bd8fafbd2
Added RTLIL::Design::modules()
2014-07-27 11:18:30 +02:00
Clifford Wolf
10e5791c5e
Refactoring: Renamed RTLIL::Design::modules to modules_
2014-07-27 11:18:30 +02:00
Clifford Wolf
d088854b47
Added conversion from ObjRange to std::vector and std::set
2014-07-27 11:18:30 +02:00
Clifford Wolf
1c8fdaeef8
Added RTLIL::ObjIterator and RTLIL::ObjRange
2014-07-27 11:18:30 +02:00
Clifford Wolf
ddc5b41848
Using std::move() in SigSpec move constructor
2014-07-27 09:20:59 +02:00
Clifford Wolf
7f3dc86ecd
Added RTLIL::SigSpec move constructor and move assignment operator
2014-07-27 02:11:57 +02:00
Clifford Wolf
c91570bde3
Mostly cosmetic changes to rtlil.h
2014-07-27 02:00:04 +02:00
Clifford Wolf
4c4b602156
Refactoring: Renamed RTLIL::Module::cells to cells_
2014-07-27 01:51:45 +02:00
Clifford Wolf
f9946232ad
Refactoring: Renamed RTLIL::Module::wires to wires_
2014-07-27 01:49:51 +02:00
Clifford Wolf
d68c993ed2
Changed more code to the new RTLIL::Wire constructors
2014-07-26 21:30:38 +02:00
Clifford Wolf
946ddff9ce
Changed a lot of code to the new RTLIL::Wire constructors
2014-07-26 20:12:50 +02:00
Clifford Wolf
267c615640
Added support for here documents
2014-07-26 17:21:40 +02:00
Clifford Wolf
97a59851a6
Added RTLIL::Cell::has(portname)
2014-07-26 16:11:28 +02:00
Clifford Wolf
f8fdc47d33
Manual fixes for new cell connections API
2014-07-26 15:58:23 +02:00
Clifford Wolf
b7dda72302
Changed users of cell->connections_ to the new API (sed command)
...
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
2014-07-26 15:58:23 +02:00
Clifford Wolf
cd6574ecf6
Added some missing "const" in rtlil.h
2014-07-26 15:58:22 +02:00
Clifford Wolf
7ac9dc7f6e
Added RTLIL::Module::connections()
2014-07-26 15:58:21 +02:00
Clifford Wolf
b03aec6e32
Added RTLIL::Module::connect(const RTLIL::SigSig&)
2014-07-26 14:31:47 +02:00
Clifford Wolf
3719281ed4
Automatically pack SigSpec on copy/assign
2014-07-26 13:59:30 +02:00
Clifford Wolf
e75e495c2b
Added new RTLIL::Cell port access methods
2014-07-26 12:22:58 +02:00
Clifford Wolf
cc4f10883b
Renamed RTLIL::{Module,Cell}::connections to connections_
2014-07-26 11:58:03 +02:00
Clifford Wolf
4755e14e7b
Added copy-constructor-like module->addCell(name, other) method
2014-07-26 00:38:44 +02:00
Clifford Wolf
2bec47a404
Use only module->addCell() and module->remove() to create and delete cells
2014-07-25 17:56:19 +02:00
Clifford Wolf
c762050e7f
Added RTLIL::SigSpec is_chunk()/as_chunk() API
2014-07-25 14:23:10 +02:00
Clifford Wolf
c4e4f79a2a
Disabled cover() for non-linux builds
2014-07-25 12:27:36 +02:00
Clifford Wolf
7f1789ad1b
Fixed typo in cover id
2014-07-25 03:41:53 +02:00
Clifford Wolf
6aa792c864
Replaced more old SigChunk programming patterns
2014-07-24 23:10:58 +02:00
Clifford Wolf
10d2402e2f
Added cover_list() API
2014-07-24 20:47:18 +02:00
Clifford Wolf
2f54345cff
Added "cover" command
2014-07-24 16:14:19 +02:00
Clifford Wolf
e589289df7
Some improvements in SigSpec packing/unpacking and checking
2014-07-24 15:05:41 +02:00
Clifford Wolf
7679000673
Now using a dedicated ELF section for all coverage counters
2014-07-24 15:05:05 +02:00
Clifford Wolf
22ede43b3f
Small changes regarding cover() and check() in SigSpec
2014-07-24 04:46:36 +02:00
Clifford Wolf
798f713629
Added support for YOSYS_COVER_FILE env variable
2014-07-24 04:16:32 +02:00
Clifford Wolf
1b0d5fc22d
Added cover() calls to RTLIL::SigSpec methods
2014-07-24 03:50:28 +02:00
Clifford Wolf
9cf12570ba
Added support for YOSYS_COVER_DIR env variable
2014-07-24 03:49:32 +02:00
Clifford Wolf
6b1018314c
Added cover() API
2014-07-24 03:48:38 +02:00
Clifford Wolf
82fa356037
Added hashing to RTLIL::SigSpec relational and equal operators
2014-07-23 23:58:03 +02:00
Clifford Wolf
f368d792fb
Disabled RTLIL::SigSpec::check() in release builds
2014-07-23 21:42:44 +02:00
Clifford Wolf
95ac484548
Fixed release build
2014-07-23 21:38:18 +02:00
Clifford Wolf
2a41afb7b2
Added RTLIL::SigSpec::repeat()
2014-07-23 21:34:14 +02:00
Clifford Wolf
c094c53de8
Removed RTLIL::SigSpec::optimize()
2014-07-23 20:32:28 +02:00
Clifford Wolf
8fd8e4a468
Turned RTLIL::SigSpec::optimize() to a no-op: a packed SigSpec is now always optimized
2014-07-23 20:11:55 +02:00
Clifford Wolf
a62c21c9c6
Removed RTLIL::SigSpec::expand() method
2014-07-23 19:34:51 +02:00
Clifford Wolf
4e802eb7f6
Fixed all users of SigSpec::chunks_rw() and removed it
2014-07-23 15:36:09 +02:00
Clifford Wolf
85db102e13
Replaced RTLIL::SigSpec::operator!=() with inline version
2014-07-23 15:35:09 +02:00
Clifford Wolf
ec923652e2
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
2014-07-23 09:52:55 +02:00
Clifford Wolf
a8d3a68971
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
2014-07-23 09:49:43 +02:00
Clifford Wolf
260c19ec5a
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3
2014-07-23 09:34:47 +02:00
Clifford Wolf
c61467a32c
Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL::Const&)
2014-07-23 08:59:54 +02:00
Clifford Wolf
115dd959d9
SigSpec refactoring: More cleanups of old SigSpec use pattern
2014-07-22 23:50:21 +02:00
Clifford Wolf
9e94f41b89
SigSpec refactoring: Added RTLIL::SigSpecIterator
2014-07-22 23:49:26 +02:00
Clifford Wolf
f80da7b41d
SigSpec refactoring: added RTLIL::SigSpec::operator[]
2014-07-22 22:54:03 +02:00
Clifford Wolf
fd4cbe6275
SigSpec refactoring: rewrote some RTLIL::SigSpec methods to use unpacked form
2014-07-22 22:26:30 +02:00
Clifford Wolf
a97be0828a
Removed RTLIL::SigChunk::compare()
2014-07-22 21:40:52 +02:00
Clifford Wolf
08e1e25169
SigSpec refactoring: added RTLIL::SigSpec::bits() and pack/unpack api
2014-07-22 21:33:52 +02:00
Clifford Wolf
28b3fd05fa
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
2014-07-22 20:58:44 +02:00
Clifford Wolf
7bffde6abd
SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only
2014-07-22 20:39:38 +02:00
Clifford Wolf
4b4048bc5f
SigSpec refactoring: using the accessor functions everywhere
2014-07-22 20:39:37 +02:00
Clifford Wolf
16e5ae0b92
SigSpec refactoring: renamed the SigSpec members to chunks_ and width_ and added accessor functions
2014-07-22 20:39:37 +02:00
Clifford Wolf
a233762a81
SigSpec refactoring: renamed chunks and width to __chunks and __width
2014-07-22 20:39:37 +02:00
Clifford Wolf
550ac35873
Added support for scripts with labels
2014-07-21 13:28:18 +02:00
Clifford Wolf
361e0d62ff
Replaced depricated NEW_WIRE macro with module->addWire() calls
2014-07-21 12:42:02 +02:00
Clifford Wolf
1d88f1cf9f
Removed deprecated module->new_wire()
2014-07-21 12:35:06 +02:00
Clifford Wolf
c54d1f2ad1
Bugfix in satgen for cells with wider in- than outputs.
2014-07-21 12:03:41 +02:00
Clifford Wolf
54b0f2e659
Added module->remove(), module->addWire(), module->addCell(), cell->check()
2014-07-21 12:02:55 +02:00
Clifford Wolf
caae6e19df
Added log_ping()
2014-07-21 12:01:45 +02:00
Clifford Wolf
8d04ca7d22
Added call_on_selection() and call_on_module() API
2014-07-20 15:33:06 +02:00
Clifford Wolf
e57db5e9b2
Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversion
2014-07-20 11:01:04 +02:00
Clifford Wolf
efa7884026
Added SIZE() macro
2014-07-20 10:36:14 +02:00
Clifford Wolf
a6174aaf5e
Added log_cell()
2014-07-20 10:35:47 +02:00
Clifford Wolf
02f0acb3bc
Fixed log_id() memory corruption
2014-07-19 20:53:29 +02:00
Clifford Wolf
35edac0b31
Added ModWalker helper class
2014-07-19 15:33:00 +02:00
Clifford Wolf
1c288adcc0
Some "const" cleanups in SigMap
2014-07-19 15:32:39 +02:00
Clifford Wolf
a721f7d768
Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit>
2014-07-18 11:36:34 +02:00
Clifford Wolf
2d69c309f9
Added function-like cell creation helpers
2014-07-18 10:27:06 +02:00
Clifford Wolf
a8cedb2257
Added log_id() helper function
2014-07-18 10:26:01 +02:00
Clifford Wolf
274c514879
Fixed RTLIL::SigSpec::append_bit() for appending constants
2014-07-17 12:10:57 +02:00
Clifford Wolf
73e0e13d2f
Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal
2014-07-16 11:38:02 +02:00
Clifford Wolf
847e2ee4a1
Use "verilog -sv" to parse .sv files
2014-07-11 13:10:51 +02:00
Clifford Wolf
e275e8eef9
Add support for cell arrays
2014-06-07 11:48:50 +02:00
Clifford Wolf
f9c1cd5edb
Improved error message for options after front-end filename arguments
2014-06-04 09:10:50 +02:00
Clifford Wolf
a5a519a9d1
workaround for OpenBSD 'stdout' implementation
2014-05-03 12:55:56 +02:00
Clifford Wolf
75a5d6bd1e
workaround for OpenBSD 'stdin' implementation
2014-05-02 13:22:26 +02:00
Clifford Wolf
d4a1b0af5b
Added support for dlatchsr cells
2014-03-31 14:14:40 +02:00
Clifford Wolf
e164edc8d1
Fixed typo in RTLIL::Module::addAdff()
2014-03-17 14:41:41 +01:00
Clifford Wolf
ef1795a1e8
Fixed typo in RTLIL::Module::{addSshl,addSshr}
2014-03-15 22:52:10 +01:00
Clifford Wolf
b7c71d92f6
Added RTLIL::Module::add{Dff,Dffsr,Adff,Dlatch}Gate() API
2014-03-15 14:35:29 +01:00
Clifford Wolf
5da9558fa8
Added log_dump() support for generic pointers
2014-03-14 16:39:50 +01:00
Clifford Wolf
0ac915a757
Progress in Verific bindings
2014-03-14 11:46:13 +01:00
Clifford Wolf
77e5968323
Added RTLIL::Module::Add{Inv,And,Or,Xor,Mux}Gate API
2014-03-14 11:45:44 +01:00
Clifford Wolf
542afc562f
Hotfix for kernel/compatibility.h
2014-03-13 12:55:15 +01:00
Clifford Wolf
fad8558eb5
Merged OSX fixes from Siesh1oo with some modifications
2014-03-13 12:48:10 +01:00
Siesh1oo
8127d5e8c3
- kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname().
...
This refactoring improves robustness and allows OSX support with only 7 new lines of code, and easy extension for other systems.
- passes/abc/abc.cc, passes/cmds/show.cc, passes/techmap/techmap.cc: use new, refactored semantics.
2014-03-12 23:17:14 +01:00
Clifford Wolf
94c1307c26
Added libs/minisat (copy of minisat git master)
2014-03-12 10:17:51 +01:00
Clifford Wolf
91704a7853
Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys
...
(see https://github.com/cliffordwolf/yosys/pull/28 )
2014-03-11 14:24:24 +01:00
Clifford Wolf
78c64a6401
Fixed a typo in RTLIL::Module::addReduce...
2014-03-10 12:07:26 +01:00
Clifford Wolf
fdef064b1d
Added RTLIL::Module::add... helper methods
2014-03-10 03:02:27 +01:00
Clifford Wolf
97710ffad5
Fixed use of frozen literals in SatGen
2014-03-06 13:08:44 +01:00
Clifford Wolf
a1bfde8c5e
Strictly zero-extend unsigned A-inputs of shift operations
2014-03-06 11:53:37 +01:00
Clifford Wolf
9e99984336
Fixed const folding of $bu0 cells
2014-02-27 04:09:32 +01:00
Clifford Wolf
aaaa604853
Added support for $bu0 to SatGen
2014-02-26 21:31:34 +01:00
Clifford Wolf
dab1612f81
Added support for Minisat::SimpSolver + ezSAT frezze() API
2014-02-23 01:35:59 +01:00
Clifford Wolf
b76528d8a5
Fixed small memory leak in Pass::call()
2014-02-23 01:28:29 +01:00
Clifford Wolf
483c99fe46
Added "design -push" and "design -pop"
2014-02-20 23:28:59 +01:00
Clifford Wolf
8f9c707a4c
Improved checking of internal cell conventions
2014-02-08 19:13:49 +01:00
Clifford Wolf
d85a6bf5d3
Added $slice and $concat to CellTypes list
2014-02-07 19:50:44 +01:00
Clifford Wolf
fc3b3c4ec3
Added $slice and $concat cell types
2014-02-07 17:44:57 +01:00
Clifford Wolf
a1ac710ab8
Stronger checking of internal cells
2014-02-07 17:39:35 +01:00
Clifford Wolf
a51a3fa2d2
Added echo command
2014-02-07 14:17:00 +01:00
Clifford Wolf
fa295a4528
Added generic RTLIL::SigSpec::parse_sel() with support for selection variables
2014-02-06 19:22:46 +01:00
Clifford Wolf
1c6dea3a0d
Added support for #-comments in same line as command
2014-02-06 14:26:39 +01:00
Clifford Wolf
19029f377b
Added support for backslash continuation in script files
2014-02-06 01:28:33 +01:00
Clifford Wolf
d267bcde4e
Fixed bug in sequential sat proofs and improved handling of asserts
2014-02-04 12:46:16 +01:00
Clifford Wolf
a6750b3753
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
2014-02-03 13:01:45 +01:00
Clifford Wolf
f9c4d33909
Added RTLIL::SigSpec::to_single_sigbit()
2014-02-02 21:35:26 +01:00
Clifford Wolf
672229eda5
Added yosys -H for command list
2014-01-30 12:32:59 +01:00
Clifford Wolf
96084e9864
Added -h command line option
2014-01-29 11:10:39 +01:00
Clifford Wolf
c36bac0e10
Added $assert support to satgen
2014-01-19 15:37:56 +01:00
Clifford Wolf
1e67099b77
Added $assert cell
2014-01-19 14:03:40 +01:00
Clifford Wolf
548d5aafa4
Some improvements in log_dump_val_worker() templates
2014-01-17 23:14:17 +01:00
Clifford Wolf
651ce67d97
Added select -assert-none and -assert-any
2014-01-17 16:34:50 +01:00
Clifford Wolf
7354a1718e
Fixed SAT and ConstEval undef handling for $pmux and $safe_pmux
2014-01-03 17:30:50 +01:00
Clifford Wolf
eec2cd1e78
Added RTLIL::SigSpec::optimized() API
2014-01-03 02:43:31 +01:00
Clifford Wolf
fb2bf934dc
Added correct handling of $memwr priority
2014-01-03 00:22:17 +01:00
Clifford Wolf
1f80557ade
Added SAT undef model for $pmux and $safe_pmux
2014-01-02 19:58:59 +01:00
Clifford Wolf
249ef8695a
Major rewrite of "freduce" command
2014-01-02 16:52:33 +01:00
Clifford Wolf
15acf593e7
Added additional checks for A_SIGNED == B_SIGNED for cells with that constraint
2013-12-31 14:54:06 +01:00
Clifford Wolf
bf607df6d5
Fixed undef extend for bitwise binary ops (bugs in simplemap and satgen)
2013-12-29 17:39:49 +01:00
Clifford Wolf
c69c416d28
Added $bu0 cell (for easy correct $eq/$ne mapping)
2013-12-28 12:02:14 +01:00
Clifford Wolf
122b3c067b
Fixed sat handling of $eqx and $nex with unequal port widths
2013-12-27 18:11:05 +01:00
Clifford Wolf
0f5ab7649e
Small cleanup in SatGen
2013-12-27 15:18:14 +01:00
Clifford Wolf
ebf9abfeb6
Fixed sat handling of $eqx and $nex cells
2013-12-27 14:32:42 +01:00
Clifford Wolf
369bf81a70
Added support for non-const === and !== (for miter circuits)
2013-12-27 14:20:15 +01:00
Clifford Wolf
ecc30255ba
Added proper === and !== support in constant expressions
2013-12-27 13:50:08 +01:00
Clifford Wolf
2ee3ac4ba3
Added log_dump() API
2013-12-20 12:11:58 +01:00
Clifford Wolf
8a815ac741
Added "sat" undef support and "sat -set-init" options
2013-12-07 17:28:51 +01:00
Clifford Wolf
ccf083e5b0
Fixed uninitialized const flags bug
2013-12-07 16:56:34 +01:00
Clifford Wolf
5d83904746
Fixes and improvements in RTLIL::SigSpec::parse
2013-12-07 11:57:29 +01:00
Clifford Wolf
f4b46ed31e
Replaced signed_parameters API with CONST_FLAG_SIGNED
2013-12-04 14:24:44 +01:00
Clifford Wolf
93a70959f3
Replaced RTLIL::Const::str with generic decoder method
2013-12-04 14:14:05 +01:00
Clifford Wolf
a66ca0472a
Added Pass:call_newsel API
2013-12-02 12:17:04 +01:00
Clifford Wolf
905eac04f1
Added "history" command
2013-12-02 11:29:39 +01:00
Clifford Wolf
1b3a60976d
Using RTLIL::id2cstr for prompt printing
2013-11-29 11:55:18 +01:00
Clifford Wolf
61412d167f
Improvements in satgen undef handling
2013-11-25 16:50:45 +01:00
Clifford Wolf
bd65e67d8a
Improvements in satgen undef handling
2013-11-25 15:12:01 +01:00
Clifford Wolf
8c3f4b3957
Started implementing undef handling in satgen
2013-11-25 04:51:33 +01:00
Clifford Wolf
8dafecd34d
Added module->avail_parameters (for advanced techmap features)
2013-11-24 20:29:07 +01:00
Clifford Wolf
f71e27dbf1
Remove auto_wire framework (smarter than the verilog standard)
2013-11-24 17:29:11 +01:00
Clifford Wolf
609caa23b5
Implemented correct handling of signed module parameters
2013-11-24 17:17:21 +01:00
Clifford Wolf
532091afcb
Added more generic _TECHMAP_ wire mechanism to techmap pass
2013-11-23 15:58:06 +01:00
Clifford Wolf
c854ad2e7e
Some driver changes/fixes
2013-11-22 14:53:57 +01:00
Clifford Wolf
058ceda6a0
Added more performance measurement infrastructure
2013-11-22 14:08:10 +01:00
Clifford Wolf
18d003254c
Massive performance improvement from refactoring RTLIL::SigSpec::optimize()
2013-11-22 04:41:20 +01:00
Clifford Wolf
8e58bb330d
Added SigBit struct and refactored RTLIL::SigSpec::extract
2013-11-22 04:07:13 +01:00
Clifford Wolf
09471846c5
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
Clifford Wolf
7d52eb0ddb
Added -v<level> option and some minor driver cleanups
2013-11-17 13:26:31 +01:00
Clifford Wolf
0fd3ebdb23
Added information on all internal cell types to internal checker
2013-11-11 00:13:18 +01:00
Clifford Wolf
378cc509cd
Call internal checker more often
2013-11-10 23:24:21 +01:00
Clifford Wolf
223892ac28
Improved user-friendliness of "sat" and "eval" expression parsing
2013-11-09 12:02:27 +01:00
Clifford Wolf
18f9477e95
Added verification of SAT model to "eval -vloghammer_report" command
2013-11-09 11:38:17 +01:00
Clifford Wolf
259cc1391e
More undef-propagation related fixes
2013-11-08 11:40:36 +01:00
Clifford Wolf
81b8f3292e
Removed debug log from const_pow()
2013-11-08 04:43:38 +01:00
Clifford Wolf
fc6dc0d7b8
Fixed handling of power operator
2013-11-07 22:20:00 +01:00
Clifford Wolf
d7cb62ac96
Fixed more extend vs. extend_u0 issues
2013-11-07 19:20:20 +01:00
Clifford Wolf
947bd9b96b
Renamed extend_un0() to extend_u0() and use it in genrtlil
2013-11-07 18:17:10 +01:00
Clifford Wolf
0e1661f84e
Fixed type of sign extension in opt_const $eq/$ne handling
2013-11-07 16:53:28 +01:00
Clifford Wolf
8c523ef81d
Improved undef handling in == and != for ConstEval
2013-11-06 22:25:35 +01:00
Clifford Wolf
6fcbc79b5c
Improved width extension with regard to undef propagation
2013-11-06 21:05:11 +01:00
Clifford Wolf
f839b842a2
Fixed handling of undef values in POS cells in ConstEval
2013-11-06 18:45:31 +01:00
Clifford Wolf
204572d926
Fixed handling of undef values in MUX select input in ConstEval
2013-11-06 17:33:20 +01:00
Clifford Wolf
f94266bb42
Added eval -vloghammer_report mode
2013-11-06 04:14:56 +01:00
Clifford Wolf
27fec4e77c
Fixed sign handling in const eval of sshl and sshr
2013-11-05 10:22:22 +01:00
Clifford Wolf
1dcb683fcb
Write yosys version to output files
2013-11-03 21:41:39 +01:00
Clifford Wolf
f39c0c9928
Fixed get_share_file_name() for installed yosys
2013-10-27 10:05:19 +01:00
Clifford Wolf
73e68fe323
Added API and Makefile rules for share/ files
2013-10-27 09:33:26 +01:00
Clifford Wolf
bd2c8ec886
Added design->full_selection() helper method
2013-10-27 09:30:58 +01:00
Clifford Wolf
e679a5d046
Fixed handling of boolean attributes (passes)
2013-10-24 11:37:54 +02:00
Clifford Wolf
eae43e2db4
Fixed handling of boolean attributes (kernel)
2013-10-24 10:59:27 +02:00
Clifford Wolf
8e8f1994b8
Changed NEW_WIRE API to return the wire, not the signal
2013-10-18 14:19:45 +02:00
Clifford Wolf
cc5e379eca
Added RTLIL NEW_WIRE macro
2013-10-18 13:25:24 +02:00
Clifford Wolf
e0f693cbb0
Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_
2013-10-18 12:13:34 +02:00
Clifford Wolf
5998c101a4
Added $sr, $dffsr and $dlatch cell types
2013-10-18 11:56:16 +02:00
Clifford Wolf
485e870bcd
Added version info to yosys command and added -V option
2013-08-20 09:48:12 +02:00
Clifford Wolf
a860efa8ac
Implemented same div-by-zero behavior as found in other synthesis tools
2013-08-15 21:00:06 +02:00
Clifford Wolf
78658199e6
Fixed signed div/mod in const eval (rounding and stuff)
2013-08-15 18:23:42 +02:00
Clifford Wolf
2f3da54f26
Added sat -ignore_div_by_zero switch
2013-08-15 11:40:01 +02:00
Clifford Wolf
d0e93e04d1
Added eval -brute_force_equiv_checker_x mode
2013-08-15 11:09:30 +02:00
Clifford Wolf
ccf36cb7d8
Added SAT support for $div and $mod cells
2013-08-11 16:27:15 +02:00
Clifford Wolf
a5836af172
Added "clean -purge" and ";;;" support
2013-08-11 13:59:14 +02:00
Clifford Wolf
080f0aac34
Added ";;" as shortcut for "; clean;"
2013-08-11 13:33:38 +02:00
Clifford Wolf
376150c926
Added techmap -opt mode
2013-08-09 15:20:22 +02:00
Clifford Wolf
05483619f0
Some fixes to improve determinism
2013-08-09 12:42:32 +02:00
Clifford Wolf
117489f95a
Fixed SigPool::del() method
2013-08-06 15:04:24 +02:00
Clifford Wolf
ff965424c2
Added proper deallocation of history buffer
2013-08-06 15:03:46 +02:00
Clifford Wolf
0f38008ed3
Added "design" command (-reset, -save, -load)
2013-07-27 14:27:51 +02:00
Clifford Wolf
974b6a947c
Added "help -write-web-command-reference-manual"
2013-07-26 00:01:31 +02:00
Clifford Wolf
ad9bbcbf40
Added $lut cells and abc lut mapping support
2013-07-23 16:19:34 +02:00
Clifford Wolf
7daeee340a
Fixed shift ops with large right hand side
2013-07-09 18:59:59 +02:00
Clifford Wolf
21e38bed98
Added "eval" pass
2013-06-19 09:30:37 +02:00
Clifford Wolf
a046a302f0
Fixed build with clang
2013-06-18 19:54:33 +02:00
Clifford Wolf
6971c4db62
Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() API
2013-06-18 17:11:13 +02:00
Clifford Wolf
6d7b5f9064
Fixed even more ConstEval bugs found using xsthammer
2013-06-14 17:50:26 +02:00
Clifford Wolf
30db70b1ba
Added consteval testing to xsthammer and fixed bugs
2013-06-13 19:51:13 +02:00
Clifford Wolf
0c6ffc4c65
More fixes for bugs found using xsthammer
2013-06-13 11:18:45 +02:00
Clifford Wolf
bf2c149329
Another fix for a bug found using xsthammer
2013-06-12 19:09:14 +02:00
Clifford Wolf
a5c30183b5
Sign-extension related fixes in SatGen and AST frontend
2013-06-10 17:10:06 +02:00
Clifford Wolf
7d790febb0
Improvements and fixes in SAT code
2013-06-10 16:09:29 +02:00
Clifford Wolf
15ff4cc63b
Added history file read/write to driver
2013-06-10 15:42:52 +02:00
Clifford Wolf
a75b249427
Implemented temporal induction proofs in sat_solve
2013-06-09 18:07:05 +02:00
Clifford Wolf
b7ba90910d
Fixed handling of $_XOR_ in SAT generator
2013-06-09 14:01:50 +02:00
Clifford Wolf
0efde13775
Added sequential solving support to sat_solve
2013-06-09 13:35:46 +02:00
Clifford Wolf
6f330f0132
Set rl_basic_word_break_characters in shell
2013-06-09 11:51:06 +02:00
Clifford Wolf
e52c9aff1b
Improved readline tab completion
2013-06-09 01:04:23 +02:00
Clifford Wolf
bf59a28f80
Look for yosys-abc and yosys-svgviewer where the main exe is
2013-06-09 00:07:26 +02:00
Clifford Wolf
5a592b3739
Moved cmds from kernel/ to passes/cmds/
2013-06-08 23:16:36 +02:00
Clifford Wolf
23a7973094
Added support for shifter cells to SAT generator
2013-06-08 15:12:08 +02:00
Clifford Wolf
92f04eab10
Added "cd" and "ls" commands for convenience
2013-06-08 14:45:28 +02:00
Clifford Wolf
1434312fdd
Various improvements in sat_solve pass and SAT generator
2013-06-08 14:11:50 +02:00
Clifford Wolf
c681c17038
Improved auto-detection of -show signals in sat_solve
2013-06-08 09:34:36 +02:00
Clifford Wolf
56b593b91c
Improved sat generator and sat_solve pass
2013-06-07 14:37:33 +02:00
Clifford Wolf
46fbe9d262
Added SAT generator and simple sat_solve command
2013-06-07 13:59:13 +02:00
Clifford Wolf
21d9251e52
Added "dump" command (part ilang backend)
2013-06-02 17:53:30 +02:00
Clifford Wolf
ed0e2f7a6f
Added log_assert() api
2013-05-24 14:38:36 +02:00
Clifford Wolf
ccd2a93439
Added log_abort() api
2013-05-24 12:32:06 +02:00
Clifford Wolf
cbe423a1fe
Only initialize TCL interpreter when needed
2013-05-23 12:56:23 +02:00
Clifford Wolf
6a38e767ba
Added labels to "help -write-tex-command-reference-manual" output
2013-05-23 09:49:37 +02:00
Clifford Wolf
ebb155b2d5
Added support for processes to show command
2013-05-23 09:15:51 +02:00
Clifford Wolf
04996657c8
Fixed show command for constant assignments
2013-05-23 08:22:44 +02:00
Clifford Wolf
595db0d7b9
Added tcl "yosys -import" command
2013-05-02 15:27:01 +02:00
Clifford Wolf
97f783e668
Improved/simplified TCL bindings
2013-05-01 14:21:03 +02:00
Clifford Wolf
e6dca3445a
Fixed "show -format ..." command line parsing
2013-04-15 11:59:35 +02:00
Clifford Wolf
af4444e5b9
Fixed/improved handling of colored wires in show command
2013-04-01 14:58:43 +02:00
Clifford Wolf
32ee794bfb
Added support for @<set-name> in expand select ops (%x, %ci, %co)
2013-04-01 14:58:11 +02:00
Clifford Wolf
5919bf5525
Removed 4096 bytes limit for size of command from script file
2013-04-01 14:38:05 +02:00
Clifford Wolf
3ec9fa4048
Added -color <color> <selection> option to show command
2013-04-01 14:12:17 +02:00
Clifford Wolf
9b1ce98db6
Fixed "select" for "%%" stmt with emty stack
2013-03-31 18:06:27 +02:00
Clifford Wolf
b66e9fb348
Added "script" command
2013-03-31 18:05:31 +02:00
Clifford Wolf
88af5b6a16
Improved opt_share for reduce cells
2013-03-29 11:19:21 +01:00
Clifford Wolf
73fba5164f
Implemented TCL support (only via -c option at the moment)
2013-03-28 12:26:17 +01:00
Clifford Wolf
7bfc7b61a8
Implemented proper handling of stub placeholder modules
2013-03-28 09:20:10 +01:00
Clifford Wolf
92cf7ae2f7
Added check: only one module for "show" unless format is "ps"
2013-03-27 18:31:42 +01:00
Clifford Wolf
35a02ee81e
Now using SVG and yosys-svgviewer per default in show command
2013-03-27 18:14:16 +01:00
Clifford Wolf
041c06bd9d
Create nice errors when calling RTLIL::Module::derive() of base class
2013-03-26 19:27:49 +01:00
Clifford Wolf
4a7d624bef
Added hierarchy -generate command for generating skeletton modules
2013-03-25 02:14:33 +01:00
Clifford Wolf
e1a80b356e
Fixed handling of show -viewer
2013-03-24 15:21:57 +01:00
Clifford Wolf
2887e4305f
Fixed handling of internal signals in show command
2013-03-24 15:15:28 +01:00
Clifford Wolf
181b479e77
Improved show -colors color assignments
2013-03-24 13:32:56 +01:00
Clifford Wolf
bbae24bdf7
Added show -strech and renamed -widthlabels to -width
2013-03-24 13:27:11 +01:00
Clifford Wolf
f921b06fb0
Added -widthlabels options to chow command
2013-03-24 13:11:06 +01:00
Clifford Wolf
55c50dc499
Added -colors option to show command
2013-03-24 10:41:24 +01:00
Clifford Wolf
47325fb271
Added help -write-tex-command-reference-manual option
2013-03-21 11:33:56 +01:00
Clifford Wolf
8f610dca58
Added -S option for simple synthesis to gate logic
2013-03-21 09:52:21 +01:00
Clifford Wolf
91b94ef57b
Disabled the per-default dumping of ILANG code
2013-03-21 09:12:32 +01:00
Johann Glaser
15ad2db8fc
fixed a crash when lines start with whitespace
2013-03-18 20:58:47 +01:00
Johann Glaser
cd8008bda0
fixed typos
2013-03-18 07:28:31 +01:00
Clifford Wolf
35b4a2c553
Fixed gcc warnings and added error handling to shell escape
2013-03-15 10:29:25 +01:00
Clifford Wolf
89f009d171
Added additional functionality and cleanups in sigtools.h and celltypes.h
2013-03-15 10:22:23 +01:00
Clifford Wolf
3377a04bf2
Changed prefix for selection operators from # to %
2013-03-14 16:15:24 +01:00
Clifford Wolf
697cf1eb80
Added #ci and #co selection operators
2013-03-14 15:57:47 +01:00
Clifford Wolf
b35add5f8c
Added more features to #x selection operator
2013-03-14 15:35:05 +01:00
Clifford Wolf
b0f386751c
Added "select -write" command
2013-03-14 13:02:10 +01:00
Clifford Wolf
de823ce964
Added $sr cell type to celltypes.h
2013-03-14 01:08:30 +01:00
Clifford Wolf
eadf73c823
Added shell escape to command language
2013-03-10 14:05:42 +01:00
Clifford Wolf
0be19f6ca7
Fixed and improved #x selection operator
2013-03-08 10:15:15 +01:00
Clifford Wolf
79b3afa011
Added ## selection operator (union all on stack)
2013-03-08 08:47:35 +01:00
Clifford Wolf
653f0049a8
Added select -count mode
2013-03-08 08:31:12 +01:00
Clifford Wolf
8960bba9b5
Fixed parsing of select #x<num> operator
2013-03-06 19:01:08 +01:00
Clifford Wolf
f2f3e2cb19
Improved error message on failed module load
2013-03-06 18:30:45 +01:00
Clifford Wolf
b380af9d6d
Added support for loadable modules (aka plugins)
2013-03-06 11:58:07 +01:00
Clifford Wolf
334fd03e1c
Implemented much better #x select operator
2013-03-05 12:53:40 +01:00
Clifford Wolf
d4680fd5a0
Added design->select() api and use it in extract pass
2013-03-03 20:53:24 +01:00
Clifford Wolf
b9b990ca2c
Added support for #x:<num> select stmt
2013-03-03 17:41:46 +01:00