This website requires JavaScript.
Explore
Help
Sign In
riscv
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Projects
Releases
Wiki
Activity
6,836
Commits
84
Branches
48
Tags
36
MiB
c1459bc748
Commit Graph
1 Commits
Author
SHA1
Message
Date
Udi Finkelstein
536ae16c3a
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
...
meaningful info on the error. Also add 13 compilation examples that triggers each of these messages.
2018-10-25 02:37:56 +03:00