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1047 Commits

Author SHA1 Message Date
Marcelina Kościelnicka 34d2fbd2f9
Add opt_lut_ins pass. (#1673) 2020-02-03 14:57:17 +01:00
Rodrigo Alejandro Melo 313a425bd5 Merge branch 'master' of https://github.com/YosysHQ/yosys 
Solved a conflict into the CHANGELOG

Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
 2020-02-03 10:56:41 -03:00
David Shah ebe1d7d5ab sv: More tests for wildcard port connections 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
David Shah 7e741714df hierarchy: Correct handling of wildcard port connections with default values 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
David Shah a210675d71 sv: Add tests for wildcard port connections 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
Rodrigo Alejandro Melo 8217f579b7 Removed 'synth' into tests/memfile/run-test.sh 
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-02-02 12:34:27 -03:00
Rodrigo Alejandro Melo 9b49f1bc46 Added content1.dat into tests/memfile 
Modified run-test.sh to use it.

Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-02-02 12:18:34 -03:00
David Shah 9f5613100b
Merge pull request #1647 from YosysHQ/dave/sprintf 
ast: Add support for $sformatf system function
 2020-02-02 14:53:46 +00:00
Rodrigo Alejandro Melo eaaba6e091 Added tests/memfile to 'make test' with an extra testcase 
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-02-01 22:44:06 -03:00
Rodrigo Alejandro Melo 43396fae2c Added a test for the Memory Content File inclusion using $readmemb 
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-02-01 17:41:10 -03:00
Eddie Hung 136842b1ef Merge branch 'master' into eddie/submod_po 2020-02-01 02:14:19 -08:00
Miodrag Milanović 71d148bcaa
Merge pull request #1559 from YosysHQ/efinix_test_fix 
Fix for non-deterministic test
 2020-01-29 11:18:06 +01:00
Eddie Hung d004953772 Add "help -all" and "help -celltypes" sanity test 2020-01-28 18:11:34 -08:00
Eddie Hung a855f23f22 Merge remote-tracking branch 'origin/master' into eddie/opt_merge_init 2020-01-28 12:46:18 -08:00
Eddie Hung 7939727d14
Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts 
Unpermute LUT ordering for ice40/ecp5/xilinx
 2020-01-28 11:55:51 -08:00
Miodrag Milanovic 94191a93dd Updated test to use assert-max 2020-01-28 18:26:10 +01:00
Claire Wolf 4ddaa70fd6
Merge pull request #1567 from YosysHQ/eddie/sat_init_warning 
sat: suppress 'Warning: ignoring initial value on non-register: ...' when init[i] = 1'bx
 2020-01-28 17:40:28 +01:00
N. Engelhardt 086c133ea5
Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate 
synth_xilinx: error out if tristate without '-iopad'
 2020-01-28 17:24:54 +01:00
Eddie Hung cfb0366a18 Import tests from #1628 2020-01-27 13:56:16 -08:00
Eddie Hung 48f3f5213e
Merge pull request #1619 from YosysHQ/eddie/abc9_refactor 
Refactor `abc9` pass
 2020-01-27 13:29:15 -08:00
Eddie Hung af8281d2f5
Merge pull request #1656 from YosysHQ/eddie/ice40_abc9_warnings 
ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
 2020-01-27 09:54:04 -08:00
Eddie Hung b178761551 ice40: reduce ABC9 internal fanout warnings with a param for CI->I3 2020-01-24 11:59:48 -08:00
Eddie Hung 2d795fb8c0 simple_abc9 tests to discard whitebox before write for sim 2020-01-23 22:07:43 -08:00
Eddie Hung dca1c806ec simple_abc9 tests to discard whitebox before write for sim 2020-01-23 19:55:11 -08:00
Eddie Hung e471b330ac abc_box_id -> abc9_box_id in test 2020-01-23 19:12:19 -08:00
Eddie Hung 11e50c0e9e Test for (* keep *)-ed abc9_box_id 2020-01-23 18:56:25 -08:00
Eddie Hung 48aec34e0d abc_box_id -> abc9_box_id in test 2020-01-23 18:53:14 -08:00
Eddie Hung 5aaa19f1ab Update tests with reduced area 2020-01-21 16:50:04 -08:00
Eddie Hung 3d9737c1bd Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-21 16:27:40 -08:00
Eddie Hung 8d1b736c4f Move from +/shiftx2mux.v into +/techmap.v; cleanup 2020-01-21 15:19:41 -08:00
Eddie Hung 7977574995 New techmap +/shiftx2mux.v which decomposes LSB first; better for ABC 2020-01-21 15:19:41 -08:00
Eddie Hung cd8f55a911 write_xaiger: fix for (* keep *) on flop output 2020-01-21 09:43:04 -08:00
David Shah 22c967e35e ast: Add support for $sformatf system function 
Signed-off-by: David Shah <dave@ds0.me>
 2020-01-19 21:20:17 +00:00
Eddie Hung 6a163b5ddd xilinx_dsp: another typo; move xilinx specific test 2020-01-17 17:07:03 -08:00
Eddie Hung db68e4c2a7 ice40_dsp: fix typo 2020-01-17 16:08:04 -08:00
Eddie Hung 5507c328ff Add #1644 testcase 2020-01-17 15:57:52 -08:00
Eddie Hung ad6c49fff1 ice40_dsp: add test 2020-01-17 15:38:26 -08:00
Jeff Wang 8ef5c7d48c scoped enum tests 2020-01-16 18:13:30 -05:00
Jeff Wang caf35896da enum in package test 2020-01-16 18:09:03 -05:00
Jeff Wang febe7706a2 simple enum test 2020-01-16 18:09:03 -05:00
Eddie Hung 2245afa142 More rigorous test 2020-01-16 09:15:42 -08:00
Eddie Hung 03ce2c72bb Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-15 16:42:16 -08:00
Eddie Hung 5918ede9bd abc9: aAdd test to check $_NOT_s are absorbed 2020-01-15 14:36:05 -08:00
Eddie Hung e30b6bbbf8 clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_* 2020-01-15 09:51:31 -08:00
Eddie Hung 53a99ade9c Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-14 11:46:56 -08:00
Eddie Hung 61ffd2d199
Merge pull request #1633 from YosysHQ/eddie/fix_autoname 
autoname: do not rename ports
 2020-01-14 11:40:54 -08:00
Eddie Hung 9fa0e03cc9
Merge pull request #1632 from YosysHQ/eddie/fix1630 
read_aiger: uniquify wires with $aiger<autoidx> prefix
 2020-01-14 11:40:40 -08:00
Miodrag Milanović 9fbeb57bbd
Merge pull request #1623 from YosysHQ/mmicko/edif_attr 
Export wire properties in EDIF
 2020-01-14 19:19:32 +01:00
Eddie Hung 00964e999d autoname: add testcase with $-prefix-ed port 2020-01-14 10:13:03 -08:00
Eddie Hung 565d349dc9 Add #1630 testcase 2020-01-13 21:27:53 -08:00
Eddie Hung a6d4ea7463 abc9: respect (* keep *) on cells 2020-01-13 19:21:11 -08:00
Eddie Hung 9ec948f396 write_xaiger: add support and test for (* keep *) on wires 2020-01-13 19:07:55 -08:00
Eddie Hung ca2f3db53f
Merge pull request #1620 from YosysHQ/eddie/abc9_scratchpad 
abc9: add some scripts/options into "scratchpad"
 2020-01-13 09:04:20 -08:00
Eddie Hung ae619ba87a Add #1626 testcase 2020-01-12 15:21:26 -08:00
Eddie Hung c063436eea Merge remote-tracking branch 'origin/master' into eddie/abc9_scratchpad 2020-01-11 17:02:20 -08:00
Miodrag Milanovic ccfe1e5909 this one is fine 2020-01-10 15:20:50 +01:00
Miodrag Milanovic af852a0ea8 Fix tests 2020-01-10 14:48:01 +01:00
Eddie Hung a10016ccc5 Add abc9 sanity test 2020-01-09 18:17:06 -08:00
Eddie Hung 94ab3791ce Merge remote-tracking branch 'origin/master' into eddie/abc9_mfs 2020-01-07 15:44:18 -08:00
Eddie Hung 0d3f10d3cc Add testcases 2020-01-07 11:44:20 -08:00
Eddie Hung 7c878bf397 tests/aiger: write Yosys output 2020-01-07 11:44:03 -08:00
Eddie Hung 3df869cc7c Add testcase from #1459 2020-01-06 16:22:22 -08:00
Eddie Hung 6e866030c2 Combine tests to check multiple clock domains 2020-01-02 14:38:59 -08:00
Eddie Hung b454735bea Merge remote-tracking branch 'origin/master' into xaig_dff 2020-01-02 12:44:06 -08:00
Eddie Hung 9e5ff30d05
Merge pull request #1606 from YosysHQ/eddie/improve_tests 
Fix a few issues in tests/arch/*
 2020-01-01 13:31:46 -08:00
Eddie Hung 52fe1e0c44 Revert insertion of 'reg', leave note behind 2020-01-01 09:05:46 -08:00
Miodrag Milanovic a1344ec06e Added a test case 2020-01-01 16:24:30 +01:00
Eddie Hung 713484fa66 Do not do call equiv_opt when no sim model exists 2019-12-31 18:40:30 -08:00
Eddie Hung a59016b146 Fix warnings 2019-12-31 18:40:11 -08:00
Eddie Hung c082329af3 Call equiv_opt with -multiclock and -assert 2019-12-31 18:39:32 -08:00
Eddie Hung ccc0a740d2 Add some abc9 dff tests 2019-12-31 16:16:05 -08:00
Eddie Hung 0c4be94a02 Add -D DFF_MODE to abc9_map test 2019-12-30 20:13:25 -08:00
Eddie Hung fc4b8b8991 Remove submod changes 2019-12-30 14:56:14 -08:00
Eddie Hung 405e974fe5 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-30 14:31:42 -08:00
Miodrag Milanović c0a17c2457
Merge pull request #1589 from YosysHQ/iopad_default 
Make iopad option default for all xilinx flows
 2019-12-30 20:34:31 +01:00
Eddie Hung c2c74f9bb0
Merge pull request #1599 from YosysHQ/eddie/retry_1588 
Retry #1588 -- "write_xaiger: only instantiate each whitebox cell type once"
 2019-12-30 10:01:02 -08:00
Miodrag Milanovic f9749c202c Fix new tests 2019-12-28 16:43:19 +01:00
Miodrag Milanovic 8c3de1d4bd Merge remote-tracking branch 'origin/master' into iopad_default 2019-12-28 16:23:31 +01:00
Miodrag Milanovic a82c701668 Make test without iopads 2019-12-28 16:22:24 +01:00
Miodrag Milanovic 509da7ed1a Revert "Fix xilinx tests, when iopads are default" 
This reverts commit 477e43d921.
 2019-12-28 16:12:45 +01:00
Eddie Hung 011f749ecf Update resource count 2019-12-28 02:15:11 -08:00
Eddie Hung d45869855c Add #1598 testcase 2019-12-27 16:44:57 -08:00
Marcin Kościelnicki a24596def3 iopadmap: Emit tristate buffers with const OE for some edge cases. 2019-12-25 17:37:58 +01:00
Eddie Hung 2e21aa59a2 Add DSP cascade tests 2019-12-23 14:58:06 -08:00
Marcin Kościelnicki 666c6128a9 xilinx_dsp: Initial DSP48A/DSP48A1 support. 2019-12-22 20:51:14 +01:00
Miodrag Milanovic 436fea9e69 Addressed review comments 2019-12-21 20:23:23 +01:00
Miodrag Milanovic 477e43d921 Fix xilinx tests, when iopads are default 2019-12-21 13:18:44 +01:00
Eddie Hung 1ea1e8e54f Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-20 13:56:13 -08:00
Eddie Hung 94f15f023c Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-19 10:29:40 -08:00
Eddie Hung d406f2ffd7
Merge pull request #1569 from YosysHQ/eddie/fix_1531 
verilog: preserve size of $genval$-s in for loops
 2019-12-19 12:21:33 -05:00
Eddie Hung d675f22f4e
Merge pull request #1571 from YosysHQ/eddie/fix_1570 
mem_arst.v: do not redeclare ANSI port
 2019-12-19 12:21:22 -05:00
Eddie Hung b2a42e1fac
Merge pull request #1572 from nakengelhardt/scratchpad_pass 
add a command to read/modify scratchpad contents
 2019-12-18 13:55:44 -05:00
Marcin Kościelnicki f382164d6e tests/xilinx: fix flaky mux test 2019-12-18 15:53:29 +01:00
Marcin Kościelnicki a235250403 xilinx: Add xilinx_dffopt pass (#1557) 2019-12-18 13:43:43 +01:00
Marcin Kościelnicki aff6ad1ce0 xilinx: Improve flip-flop handling. 
This adds support for infering more kinds of flip-flops:

- FFs with async set/reset and clock enable
- FFs with sync set/reset
- FFs with sync set/reset and clock enable

Some passes have been moved (and some added) in order for dff2dffs to
work correctly.

This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop
capabilities (though not latch capabilities).  Older FPGAs also support
having both a set and a reset input, which will be handled at a later
data.
 2019-12-18 13:43:43 +01:00
Eddie Hung a73f96594f
Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram 
xilinx: add LUTRAM rules for RAM32M, RAM64M
 2019-12-16 21:48:21 -08:00
Eddie Hung aed67dd020 abc9 needs a clean afterwards 2019-12-16 18:42:23 -08:00
Eddie Hung 378d9e6e0c Add another test 2019-12-16 13:57:55 -08:00
Eddie Hung db0003410f Accidentally commented out tests 2019-12-16 13:31:47 -08:00
Eddie Hung 5a00d5578c Add unconditional match blocks for force RAM 2019-12-16 13:31:15 -08:00