Commit Graph

503 Commits

Author SHA1 Message Date
Martin Povišer 1b1a6c4aed
Merge pull request #4525 from georgerennie/peepopt_clock_gate
peepopt: Add formal opt to rewrite latches to ffs in clock gates
2024-11-11 14:49:09 +01:00
Emil J. Tywoniak 785bd44da7 rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
Emily Schmidt bdb59ffc8e add -fst-noinit flag to sim for not initializing the state from the fst file 2024-08-21 11:03:29 +01:00
George Rennie 236c69bed4 clk2fflogic: run peepopt -formalclk before processing design
* this attempts to rewrite clock gating patterns into a form that is
  less likely to introduce combinational loops with clk2fflogic

* can be disabled with -nopeepopt which is useful for testing
  clk2fflogic
2024-08-07 10:14:04 +01:00
Miodrag Milanovic 6d98418f3d Set ranges on exported wires in VCD and FST 2024-08-02 15:23:00 +02:00
Martin Povišer e063b96104 synthprop: Reformat the help 2024-07-25 11:43:58 +02:00
Jannis Harder 2bd889a59a formalff -setundef: Fix handling for has_srst FFs
The `has_srst`` case was checking `sig_ce` instead of `sig_srst` due to
a copy and paste error.

This would crash when `has_ce` was false and could incorrectly determine
that an initial value is unused when `has_ce` and `has_srst` are both
set.
2024-04-15 11:53:30 +02:00
N. Engelhardt d70113a909
Merge pull request #3972 from nakengelhardt/celledges_shift_ops
celledges: support shift ops
2024-03-08 09:35:47 +01:00
Jannis Harder bbdfcfdf30 clk2fflogic: Fix handling of $check cells
Fixes a bug in the handling of the recently introduced $check cells.
Both $check and $print cells in clk2fflogic are handled by the same code
and the existing tests for that were only using $print cells. This
missed a bug where the additional A signal of $check cells that is not
present on $print cells was dropped due to a typo, rendering $check
cells non-functional.

Also updates the tests to explicitly cover both cell types such that
they would have detected the now fixed bug.
2024-02-14 11:42:27 +01:00
Jannis Harder e1a59ba80b async2sync, clk2fflogic: Add support for $check and $print cells 2024-02-01 20:10:39 +01:00
Jannis Harder 7c818d30f7 sim: Bring $print trigger/sampling semantics in line with FFs 2024-01-25 16:21:03 +01:00
Martin Povišer 149bcd88ad
Merge pull request #4026 from uis246/fix-format
Fix printf formats
2024-01-15 16:04:11 +01:00
uis 5902b2826d Fix printf formats 2024-01-15 12:07:54 +01:00
Dag Lem acf916f654 Restore sim output from initial $display 2024-01-14 16:52:51 +01:00
Jannis Harder 57b4e16acd sim: Include $display output in JSON summary
This allows tools like SBY to capture the $display output independent
from anything else sim might log. Additionally it provides source and
hierarchy locations for everything printed.
2024-01-11 12:01:39 +01:00
Martin Povišer 6581b5593c sim: Print hierarchy for failed assertions 2023-12-06 12:09:07 +01:00
Claire Xen a4951a3a97
Merge pull request #3986 from povik/sim-ui-fixes
Slightly improve `sim` UI
2023-10-16 16:54:05 +02:00
N. Engelhardt 6c562c76bc fix handling right shifts 2023-10-12 11:46:09 +02:00
N. Engelhardt 3e22791810
Merge pull request #3975 from rmlarsen/optmerge 2023-10-09 17:05:19 +02:00
Martin Povišer c3fd88624a sim: Bail on processes
Instead of silently missimulating, error out when there are processes
found in the simulation hierarchy.
2023-10-05 19:25:17 +02:00
Martin Povišer a782b15aae sim: s/instanced/instantiated/ 2023-10-05 19:25:17 +02:00
Martin Povišer 6ac43e49bc sim: Change clocked read port suggestion to `memory_nordff`
`memory_nordff` has the advantage that it can be called just ahead of
the simulation step no matter whether the clocked read port has been
inferred or was explicitly instantiated in a flow.
2023-10-05 19:25:17 +02:00
Rasmus Munk Larsen 8e0308b5e7 Revert changes to celltypes.h. Use dict instead of std::unordered_map and most hash function for uint64_t to hashlib.h to support this. 2023-10-03 14:25:59 -07:00
Jannis Harder 7eaa4bcb46 sim: Add -noinitstate option and handle non-cosim initstate
This adds the -noinitstate option which is required to simulate
counterexamples to induction with yw-cosim. Also add handling for
$initstate cells for non-co-simulation.
2023-09-28 17:29:24 +02:00
Martin Povišer 5bef9b4e75
Merge pull request #3915 from povik/sim-print
sim: Add print support
2023-09-11 17:03:59 +02:00
Martin Povišer d4d951657f sim: Add `-assert` option to fail on failed assertions 2023-09-05 10:46:04 +02:00
Martin Povišer 50d117956c sim: Add print support 2023-09-04 17:12:38 +02:00
Martin Povišer f5485b59a9 sim: Bail if there are blackboxes in simulation 2023-07-20 21:01:03 +01:00
Jannis Harder e36c71b5b7 Use clk2fflogic attr on cells to track original FF names in witnesses
This makes clk2fflogic add an attr to $ff cells that carry the state of
the emulated async FF. The $ff output doesn't have any async updates
that happened in the current cycle, but the $ff input does, so the $ff
input corresponds to the async FF's output in the original design.

Hence this patch also makes the following changes to passes besides
clk2fflogic (but only for FFs with the clk2fflogic attr set):

  * opt_clean treats the input as a register name (instead of the
    output)

  * rename -witness ensures that the input has a public name

  * the formal backends (smt2, btor, aiger) will use the input's
    name for the initial state of the FF in witness files

  * when sim reads a yw witness that assigns an initial value to the
    input signal, the state update is redirected to the output

This ensures that yosys witness files for clk2fflogic designs have
useful and stable public signal names. It also makes it possible to
simulate a clk2fflogic witness on the original design (with some
limitations when the original design is already using $ff cells).

It might seem like setting the output of a clk2fflogic FF to update the
input's initial value might not work in general, but it works fine for
these reasons:

  * Witnesses for FFs are only present in the initial cycle, so we do
    not care about any later cycles.

  * The logic that clk2fflogic generates loops the output of the
    genreated FF back to the input, with muxes in between to apply any
    edge or level sensitive updates. So when there are no active updates
    in the current gclk cycle, there is a combinational path from the
    output back to the input.

  * The logic clk2fflogic generates makes sure that an edge sensitive
    update cannot be active in the first cycle (i.e. the past initial
    value is assumed to be whatever it needs to be to avoid an edge).

  * When a level sensitive update is active in the first gclk cycle, it
    is actively driving the output for the whole gclk cycle, so ignoring
    any witness initialization is the correct behavior.
2023-05-25 12:48:02 +02:00
Jannis Harder 7caeb922a0 sim: Run level triggered async updates to fixpoint during initialization 2023-05-25 12:46:16 +02:00
gatecat 52c8c28d2c Add recover_names pass to recover names post-mapping 2023-05-25 10:55:07 +02:00
Jannis Harder ad2b04d63a sim: Fix cosimulation with nested modules having unconnected inputs
When assigning values to input ports of nested modules in cosimulation,
sim needs to find the actual driver of the signal to perform the
assignment. The existing code didn't handle unconnected inputs in that
scenario.
2023-05-18 16:50:11 +02:00
Krystine Sherwin 5a4e72f57a
Fix sim writeback check for yw_cosim
Writeback of simulation state into initial state was only working for `run()` and `run_cosim_fst()`.
This change moves the writeback into the `write_output_files()` function so that all simulation modes work with the writeback option.
2023-05-08 13:13:09 +12:00
Miodrag Milanović 4251d37f4f
Merge pull request #3610 from YosysHQ/synthprop
Synthesizable properties
2023-05-05 11:03:09 +02:00
Miodrag Milanovic 550a5b7b6b Update license 2023-02-13 17:23:26 +01:00
Miodrag Milanovic 713b7d3e26 added support for latched output reset 2023-02-13 17:23:26 +01:00
Miodrag Milanovic 131b557727 Initial implementation of synthesizable assertions 2023-02-13 17:23:26 +01:00
Jannis Harder 1698202ccc sim: For yw cosim, drive parent module's signals for input ports 2023-02-13 12:26:06 +01:00
Jannis Harder afac3f2c76 formalff: Fix crash with _NOT_ gates in -hierarchy mode 2023-01-25 12:55:29 +01:00
Jannis Harder d6c7aa0e3d sim/formalff: Clock handling for yw cosim 2023-01-11 18:07:16 +01:00
Jannis Harder 7ddec5093f sim: Improvements and fixes for yw cosim
* Fixed $cover handling
  * Improved sparse memory handling when writing traces
  * JSON summary output
2023-01-11 18:07:16 +01:00
Jannis Harder dda972a148 sim: New -append option for Yosys witness cosim
This is needed to support SBY's append option.
2023-01-11 18:07:16 +01:00
Jannis Harder 2dd5652215 sim: Add Yosys witness (.yw) cosimulation 2023-01-11 18:07:16 +01:00
Jannis Harder f6458bab70 sim: Only check formal cells during gclk simulation updates
This is required for compatibility with non-multiclock formal semantics.
2023-01-11 18:07:16 +01:00
Jannis Harder 9c6198a827 sim: Internal API to set $initstate
This is not yet added to any of the simulation drivers.
2023-01-11 18:07:16 +01:00
Jannis Harder 44b26d5c6d sim: Emit used memory addresses as signals to output traces
This matches the behavior of smtbmc.

This also updates the sim internal memory API to allow masked writes
where State::Sa bits (internal don't care - not a valid value for a
signal) leave the memory content unchanged.
2023-01-11 18:07:16 +01:00
Claire Xen 843f329b96
Merge branch 'master' into claire/eqystuff 2023-01-11 16:33:08 +01:00
Jannis Harder 5abaa59080
Merge pull request #3537 from jix/xprop
New xprop pass
2023-01-11 16:26:04 +01:00
Miodrag Milanovic 5801152779 Deprecate gcc-4.8 2023-01-11 09:54:19 +01:00
Claire Xenia Wolf 6d56d4ecfc Merge branch 'master' of github.com:YosysHQ/yosys into claire/eqystuff 2023-01-11 04:10:12 +01:00