7 Commits

Author	SHA1	Message	Date
Clifford Wolf	88db09255b	Added autotest -e (do not use -noexpr on write_verilog)	2014-08-30 18:34:07 +02:00
Clifford Wolf	7d98645fe8	Added "make -j{N}" support to "make test"	2014-07-30 19:23:26 +02:00
Clifford Wolf	964a67ac41	Added note to "make test": use git checkout of iverilog	2014-07-16 10:03:07 +02:00
Clifford Wolf	a4ec19c25c	Added tests/realmath to "make test"	2014-06-15 09:31:03 +02:00
Clifford Wolf	cc05404128	Fixed undef behavior in tests/asicworld/code_verilog_tutorial_fsm_full_tb.v	2013-05-24 15:15:59 +02:00
Clifford Wolf	2d9cbd3b02	added more .gitignore files (make test)	2013-01-05 11:35:52 +01:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00