yosys

Commit Graph

Author	SHA1	Message	Date
Eddie Hung	fdafb74eb7	kernel: use more ID::*	2020-04-02 07:14:08 -07:00
Marcin Kościelnicki	6cdea425b8	clkbufmap: Add support for inverters in clock path.	2019-11-25 20:40:39 +01:00
Marcin Kościelnicki	5fb4b12cb5	improve clkbuf_inhibit propagation upwards through hierarchy	2019-08-27 17:26:47 +02:00
Eddie Hung	619f2414e5	clkbufmap to only check clkbuf_inhibit if no selection given	2019-08-23 11:14:42 -07:00
Eddie Hung	4d89c3f468	Review comment from @cliffordwolf	2019-08-23 10:03:41 -07:00
Marcin Kościelnicki	3c75a72feb	move attributes to wires	2019-08-13 19:36:59 +00:00
Marcin Kościelnicki	c6d5b97b98	review fixes	2019-08-13 00:35:54 +00:00
Marcin Kościelnicki	f4c62f33ac	Add clock buffer insertion pass, improve iopadmap. A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it.	2019-08-13 00:16:38 +02:00

8 Commits