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657 Commits

Author SHA1 Message Date
Clifford Wolf d3b1a29708 Cleanups and improvements in wreduce pass 2014-08-05 13:11:04 +02:00
Clifford Wolf 1c182cedb7 Added mux support to wreduce command 2014-08-05 12:49:53 +02:00
Clifford Wolf 0bb6942218 Added "show -signed" 2014-08-04 15:40:08 +02:00
Clifford Wolf ebbbe7fc83 Added RTLIL::IdString::in(...) 2014-08-04 15:40:07 +02:00
Clifford Wolf c7f99be3be Fixed "share" for memory read ports 2014-08-03 20:22:33 +02:00
Clifford Wolf 027376515a Progress in "wreduce" pass 2014-08-03 20:02:42 +02:00
Clifford Wolf 0b02f6ca30 Added "wreduce" command (work in progress) 2014-08-03 15:02:05 +02:00
Clifford Wolf 014a41fcf3 Implemented recursive techmap 2014-08-03 12:40:43 +02:00
Clifford Wolf 9bb5298c10 Fixes in show command (related to new IdString) 2014-08-03 12:40:23 +02:00
Clifford Wolf 08ec33a5e5 Implemented simplemap support for "techmap -extern" 2014-08-02 21:55:13 +02:00
Clifford Wolf b6acbc82e6 Bugfix in "techmap -extern" 2014-08-02 20:54:30 +02:00
Clifford Wolf 8e7361f128 Removed at() method from RTLIL::IdString 2014-08-02 19:08:02 +02:00
Clifford Wolf 04727c7e0f No implicit conversion from IdString to anything else 2014-08-02 18:58:40 +02:00
Clifford Wolf 768eb846c4 More bugfixes related to new RTLIL::IdString 2014-08-02 18:14:21 +02:00
Clifford Wolf 8fd1c269ac Fixed a performance bug in opt_reduce 2014-08-02 15:12:16 +02:00
Clifford Wolf b9bd22b8c8 More cleanups related to RTLIL::IdString usage 2014-08-02 13:19:57 +02:00
Clifford Wolf 14412e6c95 Preparations for RTLIL::IdString redesign: cleanup of existing code 2014-08-02 00:45:25 +02:00
Clifford Wolf bd74ed7da4 Replaced sha1 implementation 2014-08-01 19:01:10 +02:00
Clifford Wolf d13eb7e099 Added ModIndex helper class, some changes to RTLIL::Monitor 2014-08-01 17:14:32 +02:00
Clifford Wolf 03ef9a75c6 Added "test_autotb -n <num_iter>" option 2014-08-01 03:55:51 +02:00
Clifford Wolf 32a1cc3efd Renamed modwalker.h to modtools.h 2014-07-31 23:30:18 +02:00
Clifford Wolf cdae8abe16 Renamed port access function on RTLIL::Cell, added param access functions 2014-07-31 16:38:54 +02:00
Clifford Wolf b5a9e51b96 Added "trace" command 2014-07-31 15:02:16 +02:00
Clifford Wolf e6d33513a5 Added module->design and cell->module, wire->module pointers 2014-07-31 14:11:39 +02:00
Clifford Wolf 1cb25c05b3 Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00
Clifford Wolf 1202f7aa4b Renamed "stdcells.v" to "techmap.v" 2014-07-31 02:32:00 +02:00
Clifford Wolf 6ca0c569d9 Added "techmap -assert" 2014-07-31 02:21:41 +02:00
Clifford Wolf 2541489105 Added techmap CONSTMAP feature 2014-07-30 22:04:30 +02:00
Clifford Wolf 6400ae3648 Added write_file command 2014-07-30 19:59:29 +02:00
Clifford Wolf ceecf5b153 Improvements in test_cell 2014-07-30 18:49:12 +02:00
Clifford Wolf 273383692a Added "test_cell" command 2014-07-29 22:07:41 +02:00
Clifford Wolf e6df25bf74 Renamed "write_autotest" to "test_autotb" and moved to passes/tests/ 2014-07-29 21:12:50 +02:00
Clifford Wolf 77e2d39cd0 Allow "hierarchy -generate" for $__ cells 2014-07-29 16:35:13 +02:00
Clifford Wolf 03c96f9ce7 Added "techmap -map %{design-name}" 2014-07-29 16:35:13 +02:00
Clifford Wolf 397b00252d Added $shift and $shiftx cell types (needed for correct part select behavior) 2014-07-29 16:35:13 +02:00
Clifford Wolf 7bd2d1064f Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
Clifford Wolf 8b0f50792c Added techmap -extern 2014-07-27 21:31:18 +02:00
Clifford Wolf 5da343b7de Added topological sorting to techmap 2014-07-27 16:43:39 +02:00
Clifford Wolf 0c86d6106c Added SigPool::check(bit) 2014-07-27 15:38:02 +02:00
Clifford Wolf 77a1462f2d Fixed bug in opt_clean 2014-07-27 15:13:29 +02:00
Clifford Wolf d07a871d35 Improved performance of opt_const on large modules 2014-07-27 14:50:25 +02:00
Clifford Wolf dbb3556e3f Fixed a bug in opt_clean and some RTLIL API usage cleanups 2014-07-27 13:19:05 +02:00
Clifford Wolf d878fcbdc7 Added log_cmd_error_expection 2014-07-27 12:05:50 +02:00
Clifford Wolf 49f72421d5 Using new obj iterator API in a few places 2014-07-27 11:32:42 +02:00
Clifford Wolf 10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
Clifford Wolf 4c4b602156 Refactoring: Renamed RTLIL::Module::cells to cells_ 2014-07-27 01:51:45 +02:00
Clifford Wolf f9946232ad Refactoring: Renamed RTLIL::Module::wires to wires_ 2014-07-27 01:49:51 +02:00
Clifford Wolf d68c993ed2 Changed more code to the new RTLIL::Wire constructors 2014-07-26 21:30:38 +02:00
Clifford Wolf 946ddff9ce Changed a lot of code to the new RTLIL::Wire constructors 2014-07-26 20:12:50 +02:00
Clifford Wolf 3f4e3ca8ad More RTLIL::Cell API usage cleanups 2014-07-26 16:14:02 +02:00
Clifford Wolf 97a59851a6 Added RTLIL::Cell::has(portname) 2014-07-26 16:11:28 +02:00
Clifford Wolf f8fdc47d33 Manual fixes for new cell connections API 2014-07-26 15:58:23 +02:00
Clifford Wolf b7dda72302 Changed users of cell->connections_ to the new API (sed command) 
git grep -l 'connections_' | xargs sed -i -r -e '
	s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
	s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
	s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
	s/(->|\.)connections_.push_back/\1connect/g;
	s/(->|\.)connections_/\1connections()/g;'
 2014-07-26 15:58:23 +02:00
Clifford Wolf cc4f10883b Renamed RTLIL::{Module,Cell}::connections to connections_ 2014-07-26 11:58:03 +02:00
Clifford Wolf 4755e14e7b Added copy-constructor-like module->addCell(name, other) method 2014-07-26 00:38:44 +02:00
Clifford Wolf 2bec47a404 Use only module->addCell() and module->remove() to create and delete cells 2014-07-25 17:56:19 +02:00
Clifford Wolf 5826670009 Various RTLIL::SigSpec related code cleanups 2014-07-25 14:25:42 +02:00
Clifford Wolf 0520bfea89 Fixed memory corruption in "opt_reduce" pass 2014-07-25 12:49:51 +02:00
Clifford Wolf c4e4f79a2a Disabled cover() for non-linux builds 2014-07-25 12:27:36 +02:00
Clifford Wolf 91bf0c90c8 Improvements in "cover" command 2014-07-25 12:04:40 +02:00
Clifford Wolf 6aa792c864 Replaced more old SigChunk programming patterns 2014-07-24 23:10:58 +02:00
Clifford Wolf 9962384d3e Added cover() calls to opt_const 2014-07-24 20:47:18 +02:00
Clifford Wolf 45b4154b37 Added "make SMALL=1" 2014-07-24 19:03:57 +02:00
Clifford Wolf b17d6531c8 Added "make PRETTY=1" 2014-07-24 17:15:01 +02:00
Clifford Wolf 2f54345cff Added "cover" command 2014-07-24 16:14:19 +02:00
Clifford Wolf 20a7965f61 Various small fixes (from gcc compiler warnings) 2014-07-23 20:45:27 +02:00
Clifford Wolf c094c53de8 Removed RTLIL::SigSpec::optimize() 2014-07-23 20:32:28 +02:00
Clifford Wolf a62c21c9c6 Removed RTLIL::SigSpec::expand() method 2014-07-23 19:34:51 +02:00
Clifford Wolf 4e802eb7f6 Fixed all users of SigSpec::chunks_rw() and removed it 2014-07-23 15:36:09 +02:00
Clifford Wolf ec923652e2 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 2014-07-23 09:52:55 +02:00
Clifford Wolf a8d3a68971 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 2014-07-23 09:49:43 +02:00
Clifford Wolf 260c19ec5a Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3 2014-07-23 09:34:47 +02:00
Clifford Wolf 4a6d234ec7 SigSpec refactoring: cleanup of old SigSpec usage in fsm_* commands 2014-07-22 23:11:36 +02:00
Clifford Wolf 65a939cb27 Fixed memory corruption with new SigSpec API in proc_mux 2014-07-22 22:54:39 +02:00
Clifford Wolf e7e30f1c86 fixed memory leak in fsm_opt 2014-07-22 22:52:57 +02:00
Clifford Wolf 28b3fd05fa SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw() 2014-07-22 20:58:44 +02:00
Clifford Wolf 4b4048bc5f SigSpec refactoring: using the accessor functions everywhere 2014-07-22 20:39:37 +02:00
Clifford Wolf a233762a81 SigSpec refactoring: renamed chunks and width to __chunks and __width 2014-07-22 20:39:37 +02:00
Clifford Wolf 137dbf3cf7 Added "opt_const -keepdc" 2014-07-21 21:38:55 +02:00
Clifford Wolf 1873480ca5 Added mul to mux conversion to "opt_const -fine" 2014-07-21 17:19:50 +02:00
Clifford Wolf 1241a9fd50 Added "opt_const -fine" and "opt_reduce -fine" 2014-07-21 16:34:16 +02:00
Clifford Wolf e035f1d886 Added opt_const support for simple identities 2014-07-21 14:41:02 +02:00
Clifford Wolf 361e0d62ff Replaced depricated NEW_WIRE macro with module->addWire() calls 2014-07-21 12:42:02 +02:00
Clifford Wolf 1d88f1cf9f Removed deprecated module->new_wire() 2014-07-21 12:35:06 +02:00
Clifford Wolf 3cb61d03f8 Wider range of cell types supported in "share" pass 2014-07-21 12:18:29 +02:00
Clifford Wolf b49beab1f3 Use ezSAT::non_incremental() in "share" pass 2014-07-21 02:08:38 +02:00
Clifford Wolf 04fcb07213 Added support for resource sharing in mux control logic 2014-07-20 20:44:14 +02:00
Clifford Wolf 1ce5e83555 Added "select -assert-count" 2014-07-20 20:15:49 +02:00
Clifford Wolf e9506bb2da Supercell creation for $div/$mod worked all along, fixed test benches 2014-07-20 18:54:06 +02:00
Clifford Wolf ff28029fdb Fixed creation of shift supercells in "share" pass 2014-07-20 17:06:36 +02:00
Clifford Wolf 4c38ec1cc8 Added "miter -equiv -flatten" 2014-07-20 15:33:07 +02:00
Clifford Wolf 8d04ca7d22 Added call_on_selection() and call_on_module() API 2014-07-20 15:33:06 +02:00
Clifford Wolf 5b3ee7a072 Added "share" supercell creation 2014-07-20 15:01:17 +02:00
Clifford Wolf 7b98e46ac3 Added removing of always inactive cells to "share" pass 2014-07-20 13:24:36 +02:00
Clifford Wolf 8819493db4 Progress in "share" pass 2014-07-20 11:04:52 +02:00
Clifford Wolf 15fd615da5 Progress in "share" pass 2014-07-20 03:03:04 +02:00
Clifford Wolf 2278995bd8 Started to implement real resource sharing 2014-07-19 20:54:32 +02:00
Clifford Wolf efd9604dfb Improved memory_share log messages 2014-07-19 15:46:11 +02:00
Clifford Wolf e0a819dbe5 More verbose memory_share help message 2014-07-19 15:34:14 +02:00
Clifford Wolf 297a0962ea Added SAT-based write-port sharing to memory_share 2014-07-19 15:33:55 +02:00
Clifford Wolf 26f982ac0b Fixed bug in memory_share feedback-to-en code 2014-07-19 15:32:14 +02:00
Clifford Wolf e441f07d89 Added translation from read-feedback to en-signals in memory_share 2014-07-18 16:46:40 +02:00
Clifford Wolf 44f13aff92 Improved seeding of color rng in show command 2014-07-18 16:44:45 +02:00
Clifford Wolf a341931972 Only create collision detect logic in memory_share if necessary 2014-07-18 14:32:40 +02:00
Clifford Wolf ab4b26679f Added memory_share 2014-07-18 13:16:56 +02:00
Clifford Wolf 309ae98246 Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN port 2014-07-18 10:28:45 +02:00
Clifford Wolf 1b00861d0a Improved opt_reduce handling of mem wr_en mux bits 2014-07-17 12:12:04 +02:00
Clifford Wolf b76bf05cda Added support for "blackbox" attribute to iopadmap 2014-07-17 08:59:07 +02:00
Clifford Wolf 64a6906cc4 Added support for "blackbox" attribute to flatten/techmap 2014-07-17 08:58:51 +02:00
Clifford Wolf d678b6533d improved opt_reduce for $mem/$memwr WR_EN multiplexers 2014-07-16 14:08:51 +02:00
Clifford Wolf 765f172211 Changes to "memory" pass for new $memwr/$mem WR_EN interface 2014-07-16 12:49:50 +02:00
Clifford Wolf 3b52121d32 now ignore init attributes on non-register wires in sat command 2014-07-05 11:18:38 +02:00
Clifford Wolf 1c85584fe5 Do not create $dffsr cells with no-op resets in proc_dff 2014-06-19 12:29:29 +02:00
Clifford Wolf 22a998903b Added %D and %c select commands 2014-06-14 16:19:32 +02:00
Clifford Wolf 744e518467 fixed cell array handling of positional arguments 2014-06-07 12:17:11 +02:00
Clifford Wolf e275e8eef9 Add support for cell arrays 2014-06-07 11:48:50 +02:00
Clifford Wolf 7020f7fc13 added tee cmd 2014-06-03 09:23:31 +02:00
Clifford Wolf 68c99bf734 Fixed log messages in memory_dff 2014-06-01 11:32:27 +02:00
Johann Glaser 278085fa01 added log_header to miter and expose pass, show cell type for exposed ports 2014-05-28 18:05:38 +02:00
Johann Glaser 684c85902d be more verbose when techmap yielded processes 2014-05-26 17:13:41 +02:00
Clifford Wolf 68c059565a Fixed bug in opt_reduce (see vloghammer issue_044) 2014-05-12 12:45:47 +02:00
Clifford Wolf f69b5800c9 fixed syntax error in dot file created by "show" command 2014-05-10 16:22:56 +02:00
Clifford Wolf 9a34486bfb Fixed performance problem in opt_mux with nets driven by many conflicting drivers 2014-03-19 10:05:01 +01:00
Clifford Wolf 34e54cda5b Small improvement in SAT log messages 2014-03-13 13:12:49 +01:00
Clifford Wolf fad8558eb5 Merged OSX fixes from Siesh1oo with some modifications 2014-03-13 12:48:10 +01:00
Siesh1oo 8127d5e8c3 - kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname(). 
This refactoring improves robustness and allows OSX support with only 7 new lines of code, and easy extension for other systems.
 - passes/abc/abc.cc, passes/cmds/show.cc, passes/techmap/techmap.cc: use new, refactored semantics.
 2014-03-12 23:17:14 +01:00
Clifford Wolf 9087ece97c OSX compatible creation of stdcells.inc, using code from github.com/Siesh1oo/yosys 
(see https://github.com/cliffordwolf/yosys/pull/28)
 2014-03-11 14:52:37 +01:00
Clifford Wolf 91704a7853 Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys 
(see https://github.com/cliffordwolf/yosys/pull/28)
 2014-03-11 14:24:24 +01:00
Clifford Wolf fa75c8286e Fixed memory corruption in passes/abc/blifparse.cc 2014-03-11 13:09:01 +01:00
Clifford Wolf fcae92868d Fixed dumping of timing() { .. } block in libparse 2014-03-09 15:16:07 +01:00
Clifford Wolf 22aabe05c9 Verbose reading of liberty and constr files in ABC pass 2014-03-09 15:15:38 +01:00
Clifford Wolf e3b11ea2d6 Fixed bug in freduce command 2014-03-07 18:44:23 +01:00
Clifford Wolf 6f8865d81a Some minor code cleanups in freduce command 2014-03-07 18:29:04 +01:00
Clifford Wolf 54d74cf616 Added freduce -dump 2014-03-06 22:06:58 +01:00
Clifford Wolf da5859a674 Added freduce -stop 2014-03-06 18:14:26 +01:00
Clifford Wolf 9b9c3327cc Fixed undef handling in opt_reduce 2014-03-06 14:18:34 +01:00
Clifford Wolf 1ecaf1bb76 Added techmap -max_iter option 2014-03-06 12:15:17 +01:00
Clifford Wolf 96e753041d fixed freduce for Minisat::SimpSolver: use frozen_literal() 2014-03-03 02:14:27 +01:00
Clifford Wolf 9e99984336 Fixed const folding of $bu0 cells 2014-02-27 04:09:32 +01:00
Clifford Wolf 548519875b Fixed bug (typo) in passes/opt/opt_const.cc 2014-02-22 17:07:22 +01:00
Clifford Wolf 8b508dc90b Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst 2014-02-21 23:34:45 +01:00
Clifford Wolf 4e43cb7317 Added _TECHMAP_REPLACE_ feature to techmap 2014-02-20 23:42:07 +01:00
Clifford Wolf 737b71c735 Added "extract -ignore_parameters" and "extract -ignore_param ..." 2014-02-20 23:31:13 +01:00
Clifford Wolf 236fc4209c Added "extract -map %<design_name>" 2014-02-20 23:30:15 +01:00
Clifford Wolf 483c99fe46 Added "design -push" and "design -pop" 2014-02-20 23:28:59 +01:00
Clifford Wolf 0dadfed46d Added connwrappers command 2014-02-20 20:44:11 +01:00
Clifford Wolf 23a3b488a0 Merge branch 'master' of github.com:cliffordwolf/yosys 2014-02-18 20:05:53 +01:00
Clifford Wolf a71d09421d Added techmap support for _TECHMAP_CONNMAP_*_ 2014-02-18 19:51:00 +01:00
Clifford Wolf a78bba1f5c Added "sat -dump_cnf" 2014-02-18 09:29:08 +01:00
Clifford Wolf 32af10fa9b Coding style corrections in SatHelper::dump_model_to_vcd() 2014-02-18 09:28:05 +01:00
Clifford Wolf 13051e6acf Added "sat -initsteps" 2014-02-18 09:03:16 +01:00
Clifford Wolf 0851c2b6ea Renamed "sat -dump_fail_to_vcd" to "sat -dump_vcd" and some minor cleanups 2014-02-17 13:59:39 +01:00
Andrew Zonenberg 4a948d780a Added "-dump_fail_to_vcd" argument to SAT solver 2014-02-17 13:52:36 +01:00
Clifford Wolf ca53ef5098 Better preserve wires when flattening (in comparison to techmap) 2014-02-17 09:44:39 +01:00
Clifford Wolf 6d63f39eb6 Added some additional checks to techmap 2014-02-16 22:18:06 +01:00
Clifford Wolf a9b11d7c83 Added CONSTMSK and CONSTVAL feature to techmap 2014-02-16 21:58:59 +01:00
Clifford Wolf 28e14ee50a Fixed handling of "keep" attribute on wires in opt_clean 2014-02-16 21:58:27 +01:00
Clifford Wolf 42ce3db983 Fixed use of selection in splitnets command 2014-02-16 17:39:50 +01:00
Clifford Wolf d3dc22a90f Added recursion support to techmap 2014-02-16 17:16:44 +01:00
Clifford Wolf 9a816b65a8 Added != support for relational select pattern 2014-02-16 00:16:54 +01:00
Clifford Wolf 623a68f528 Added iopadmap -bits 2014-02-15 21:59:26 +01:00
Clifford Wolf cdf0f10760 Fixed dfflibmap for cell libraries with no set-reset-ff 2014-02-15 16:34:12 +01:00
Clifford Wolf 67effc9f5b Fixed opt_const handling of double invert with non-1 output width 2014-02-15 13:16:08 +01:00
Clifford Wolf 3121d19d95 Added abc -keepff option 2014-02-14 11:28:42 +01:00
Clifford Wolf de3ea9269a updated default ABC command strings 2014-02-13 19:14:15 +01:00
Clifford Wolf a123941618 Updated ABC 2014-02-13 18:56:36 +01:00
Clifford Wolf cd9e8741a7 Implemented read_verilog -defer 2014-02-13 13:59:13 +01:00
Clifford Wolf b463907890 Removed double blanks in ABC default command sequences 2014-02-13 08:12:52 +01:00
Clifford Wolf 7664f5d92b Updated ABC and some related changes 2014-02-13 08:07:08 +01:00
Clifford Wolf ab71bd0746 Updated ABC to rev e97a6e1d59b9 2014-02-12 08:35:42 +01:00
Clifford Wolf 38469e7686 Various improvements in expose command (added -sep and -cut) 2014-02-09 11:07:46 +01:00
Clifford Wolf b6f33576d5 Added delete {-input|-output|-port} 2014-02-09 10:03:26 +01:00
Clifford Wolf b3b5fac191 Bugfix in delete command 2014-02-09 09:34:58 +01:00
Clifford Wolf 85914c36e5 Fixed handling of async reset in expose -evert-dff 2014-02-08 21:26:40 +01:00
Clifford Wolf db86aaa07d Build fixes for log cmd 2014-02-08 21:21:51 +01:00
Clifford Wolf c06de50f05 Merge branch 'master' of github.com:cliffordwolf/yosys 2014-02-08 21:08:46 +01:00
Clifford Wolf 0935e20003 Implemented expose -evert-dff 2014-02-08 21:08:38 +01:00
Johann Glaser af14bb5f65 added "log" command 2014-02-08 19:19:32 +01:00
Clifford Wolf 7f52c18a22 Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect 2014-02-08 19:13:19 +01:00
Clifford Wolf 926fa61119 Added various new options to splice command 2014-02-08 16:37:18 +01:00
Clifford Wolf 0c11d04144 Added %a select operator 2014-02-08 16:31:38 +01:00
Clifford Wolf 6644f80d97 Moved some passes to other source directories 2014-02-08 14:39:15 +01:00
Clifford Wolf 03ee63ff80 Added support for "keep" attribute to abc pass 2014-02-08 14:25:29 +01:00
Clifford Wolf 82c98bbbe6 Added opt -purge (frontend to opt_clean -purge) 2014-02-08 14:21:34 +01:00
Clifford Wolf 922d1c9520 Only count non-trivial attributes when findinf master signal in opt_clean 2014-02-08 14:21:04 +01:00
Clifford Wolf 2c51619c2b Now also move net labes to the right position in splice cmd 2014-02-08 00:06:00 +01:00
Clifford Wolf 274bcef66c Improved detection of primary wire for a signal in opt_clean 2014-02-07 23:50:17 +01:00
Clifford Wolf 244e8ce1f4 Added splice command 2014-02-07 20:30:56 +01:00
Clifford Wolf 08aa1062b4 Added log_header() to splitnets 2014-02-07 19:51:15 +01:00
Clifford Wolf fc3b3c4ec3 Added $slice and $concat cell types 2014-02-07 17:44:57 +01:00
Clifford Wolf 99b1e9ee56 Re-enabled abc "retime" after sorting yout the yosys-bigsim problem 2014-02-07 16:36:37 +01:00
Clifford Wolf 366dcd3abf Fixed use of "cmd_error" in passes/cmds/design.cc 2014-02-07 14:16:42 +01:00
Clifford Wolf 0192f1c66e Disabled ABC retime for now (elliptic_curve_group testcase in yosys-bigsim failed) 2014-02-06 22:31:58 +01:00
Clifford Wolf 58cb8d65af Added "retime" to standard ABC recipes 2014-02-06 22:16:20 +01:00
Clifford Wolf 91eab69912 Added copy command 2014-02-06 22:09:21 +01:00
Clifford Wolf cf593222f2 Added design -stash/-copy-from/-copy-to 2014-02-06 21:52:07 +01:00
Clifford Wolf 37fdb2ca7a Added support for s: select expressions (wire width) 2014-02-06 19:45:03 +01:00
Clifford Wolf 9428050dd6 Added i:, o:, and x: selection pattern 2014-02-06 19:35:33 +01:00
Clifford Wolf d7d1c7baf8 Added support for %m selection op 2014-02-06 19:30:08 +01:00
Clifford Wolf f2fdcef13d Merge branch 'master' of github.com:cliffordwolf/yosys 2014-02-06 19:22:50 +01:00