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2295 Commits

Author SHA1 Message Date
YRabbit 79c5a06673 gowin: Fix SDP write enable port. 
This primitive does not have a separate WRE port, so we regulate writing
using Clock Enable.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-01-30 17:06:59 +10:00
YRabbit a5fdf3f881 gowin: Change BYTE ENABLE handling. 
When inferring we allow writing to all bytes for now.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-01-27 17:19:49 +10:00
YRabbit ae991abf2e gowin: fix the BRAM mapping. 
The primitives used have been corrected and changes have been made to the set of signals.
The empirically established need to set the OCEx signal to 1 when using READ_MODE=0 is reflected.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-01-19 15:26:37 +10:00
Martin Povišer 568418b50b opt_lut: Replace `-dlogic` with `-tech ice40` 2024-01-15 12:35:21 +01:00
Miodrag Milanovic 627fbc3477 Fix Windows build by forcing initialization order, fixes #4068 2024-01-02 11:26:48 +01:00
Miodrag Milanović 86b8a1c5ae
Merge pull request #4087 from povik/lattice-dp8kc-fix 
lattice: Fix mapping onto DP8KC for data width 1 or 2
 2023-12-21 11:46:11 +01:00
Martin Povišer c028f25158 lattice: Disable broken port configuration in bram inference 2023-12-21 10:47:40 +01:00
Martin Povišer fc5c5172f8 lattice: Fix mapping onto DP8KC for data width 1 or 2 2023-12-20 23:42:12 +01:00
Miodrag Milanović a4ad7cb81a
Merge pull request #4049 from pepijndevos/patch-3 
Enable bram for Gowin
 2023-12-19 08:16:54 +01:00
N. Engelhardt d87bd7ca3f
Merge pull request #3887 from kivikakk/env-bash 
tests: use /usr/bin/env for bash.
 2023-12-18 16:33:35 +01:00
Miodrag Milanovic 6dc62bd013 Fix out of tree build 2023-12-06 09:56:35 +01:00
Miodrag Milanovic d71dd5b9bb Fix out of tree build 2023-12-06 09:11:51 +01:00
Martin Povišer 16ea497d7c pmgen: Have a single make pattern 
Remove duplicate %.pmg -> %_pm.h pattern. One of the duplicates overrode
the other, and in some conditions there were build races as to whether
the target directory for the generated header would exist. Instead have
a single rule which is properly generalized.
 2023-12-05 18:30:13 +01:00
Martin Povišer e0fc48e196 quicklogic: Generate `bram_types_sim.v` at build time 2023-12-04 18:21:00 +01:00
Martin Povišer 22cc4aff51 quicklogic: Test TDP36K inference with initial data 2023-12-04 15:52:03 +01:00
N. Engelhardt f9c8978128 add example memory test 2023-12-04 15:52:03 +01:00
Martin Povišer e0a6a01ecb quicklogic: Add `RAM_INIT` to specialized BRAM models 2023-12-04 15:52:03 +01:00
Martin Povišer 4903f99f85 quicklogic: Add missing `RAM_INIT` param on TDP36K sim model 2023-12-04 15:52:03 +01:00
Martin Povišer b602c0858f quicklogic: Set initial values on inferred TDP36K 2023-12-04 15:52:03 +01:00
Martin Povišer b30544d61d ql_dsp_io_regs: Fix ID strings, constant detection 2023-12-04 15:52:03 +01:00
Martin Povišer dad85b5178 synth_quicklogic: Fix missing FF mapping 2023-12-04 15:52:03 +01:00
Martin Povišer 532aca28ab quicklogic: Drop `blackbox` off `adder_carry` 2023-12-04 15:52:03 +01:00
Martin Povišer e19833f8c7 synth_quiclogic: Fix conditioning of bram passes 2023-12-04 15:52:02 +01:00
Martin Povišer e43810e13f ql_dsp_macc: Tune DSP inference code 2023-12-04 15:52:02 +01:00
Martin Povišer 7d738b07da ql_dsp_*: Clean up 
Clean up the code up to Yosys standards. Drop detection of
QL_DSP2_MULTADD in io_regs since those cells can't be inferred with
the current flow anyway.
 2023-12-04 15:52:02 +01:00
Martin Povišer 4bb4fd358e ql_k6n10f: Remove support for parameter-configured DSP variety 2023-12-04 15:52:02 +01:00
N. Engelhardt b80b1ab8b6 merge brams_final_map.v into brams_map.v 2023-12-04 15:52:02 +01:00
N. Engelhardt 20d864bbde add dsp inference 2023-12-04 15:52:02 +01:00
N. Engelhardt 6682693888 change ql-bram-types pass to use mode parameter; clean up primitive libraries 2023-12-04 15:52:02 +01:00
N. Engelhardt 48c1fdc33d add qlf_k6n10f architecture + bram inference 
(Copied from QuickLogic Yosys plugin repo)
 2023-12-04 15:52:02 +01:00
N. Engelhardt 98769010af synth_quicklogic: rearrange files to prepare for adding more architectures 2023-12-04 15:52:02 +01:00
gatecat bf955cc2b0 nexus: Fix format strings to remove space padding 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-12-03 10:36:34 +01:00
Pepijn de Vos f19c6b4415
Enable bram for Gowin 2023-12-03 10:17:28 +01:00
N. Engelhardt beaae79e73
Merge pull request #4021 from povik/booth-wallace 
Change `booth` architecture for improved delay, similar signed/unsigned results
 2023-11-27 16:26:03 +01:00
Martin Povišer de16cd253d synth_lattice: Enable `booth` by default on XO3 2023-11-22 15:47:11 +01:00
Lofty 5c96746309 ice40: fix -noabc9 2023-11-17 12:49:17 +00:00
Lofty 309558767d gowin: fix typo 2023-11-14 22:37:29 +00:00
N. Engelhardt 8e470add4d
Merge pull request #4029 from YosysHQ/lofty/abc9-again 
ice40, ecp5, gowin: enable ABC9 by default
 2023-11-13 17:29:57 +01:00
N. Engelhardt 52d3fa6d77
Merge pull request #4022 from povik/machxo3-qor-work 
MachXO3 QoR improvements
 2023-11-13 16:56:06 +01:00
N. Engelhardt 3fef81b537
Merge pull request #4028 from povik/cmp2softlogic 
synth_lattice: Optionally do constant comparisons in soft logic
 2023-11-13 16:53:04 +01:00
Lofty 7ae4041e20 ice40, ecp5, gowin: enable ABC9 by default 2023-11-13 15:28:13 +00:00
Martin Povišer 3ffa4b5e5d synth_lattice: Wire up `cmp2softlogic` as an option 2023-11-13 10:42:12 +01:00
Martin Povišer f7d4a855c6 techlibs: Add `cmp2softlogic.v` to common 2023-11-13 10:42:12 +01:00
Krystine Sherwin 83d2f4f334
techlibs: fix typo in help message 2023-11-13 16:29:52 +13:00
Martin Povišer fed2720999 synth_lattice: Optimize flip-flop memories better 
After `memory_map` maps memories to flip-flops we need to let `opt`
remove undef muxes, otherwise we block enable/reset signal inference by
`opt_dff` which is in detriment to QoR.
 2023-11-07 16:29:56 +01:00
Martin Povišer ee3a4ce14d synth_lattice: Merge NOT gates on DFF control signals 
`dfflegalize` will emit NOT gates to drive control signals on flip-flops
when mapping to supported flip-flop polarities. Typically in a design
this will produce a number of NOT gates driven by the same signal. For
one reason or another ABC doesn't fully cancel this redundancy during
LUT mapping. Insert an explicit `opt_merge` pass to improve synthesis
QoR.
 2023-11-07 16:21:39 +01:00
Lofty b8b47f7c6c
Revert "ice40, ecp5: enable ABC9 by default" 2023-11-03 14:52:52 +00:00
Lofty 32082477b5 ice40, ecp5: enable ABC9 by default 2023-11-03 08:52:54 +00:00
Lofty 294844137b gowin: fix abc9 attributes and specify blocks 2023-10-04 00:16:10 +01:00
Martin Povišer 54be4aca90
Merge pull request #3924 from andyfox-rushc/master 
multpass -- create Booth Encoded multipliers for
 2023-09-18 16:46:59 +02:00
Jannis Harder 78ff40d1b2 Run `future` as part of `prep` 2023-09-13 11:32:36 +02:00
Miodrag Milanovic 27ac912709 Support import of $future_ff 2023-09-13 11:32:36 +02:00
Miodrag Milanovic 54050a8c16 Basic support for tag primitives 2023-09-13 11:32:36 +02:00
andyfox-rushc 0fa412502c mult -> booth in synth.cc, to turn on use synth -booth 2023-09-08 16:44:59 -07:00
andyfox-rushc 1d92ea8001 Support for turning on mult pass from generic synth command 2023-09-08 16:16:24 -07:00
Miodrag Milanovic 72bec94ef4 Add missing file for XO3D 2023-09-01 10:15:51 +02:00
Miodrag Milanovic 792cf8326e defult nowidelut for xo2/3/3d 2023-08-29 10:08:55 +02:00
Miodrag Milanovic b168ff99d0 fix generated blackboxes for ecp5 2023-08-28 16:26:26 +02:00
Miodrag Milanovic 0756285710 enable more primitives supported with nextpnr 2023-08-25 11:45:25 +02:00
Miodrag Milanovic 3b9ebfa672 Addressed code review comments 2023-08-25 11:10:20 +02:00
Miodrag Milanovic 541c1ab567 add script for blackbox extraction 2023-08-23 11:51:00 +02:00
Miodrag Milanovic 75fd706487 delete machxo2 since it is now supported in lattice 2023-08-23 10:54:17 +02:00
Miodrag Milanovic e3c15f003e Create synth_lattice 2023-08-23 10:53:21 +02:00
Miodrag Milanovic a8809989c4 ecp5_gsr -> lattice_gsr, change opt_lut_ins to accept lattice as tech 2023-08-22 10:50:11 +02:00
Charlotte d130f7fca2 tests: use /usr/bin/env for bash. 2023-08-12 11:59:39 +10:00
Charlotte f9d38253c5 ast: add `PRIORITY` to `$print` cells 2023-08-11 04:46:52 +02:00
Charlotte 4e94f62116 simlib: blackbox `$print` cell 
It's possible to `generate` the appropriate always blocks per the
triggers, but unlikely to be worth parsing the RTLIL \FORMAT parameter.
 2023-08-11 04:46:52 +02:00
Patrick Urban 61387d78b7 gatemate: Prevent implicit declaration of `ram_{we,en}` 2023-06-05 19:08:44 +02:00
Patrick Urban 2004a9ff4a gatemate: Add CC_FIFO_40K simulation model 2023-05-30 09:06:23 +02:00
Patrick Urban c244a7161b gatemate: Fix SDP read behavior 2023-05-30 09:05:43 +02:00
Lofty fb7af093a8 intel_alm: re-enable 8x40-bit M10K support 2023-05-29 06:42:03 +01:00
Lofty cac1bc6fbe intel_alm: enable M10K initialisation 2023-05-25 18:56:34 +01:00
Lofty 00b0e850db intel_alm: re-enable carry chains for ABC9 2023-05-25 18:28:10 +01:00
Miodrag Milanović 7aab324e85
Merge pull request #3737 from yrabbit/all-primitives-script 
gowin: Add all the primitives.
 2023-05-09 11:13:51 +02:00
Ralf Fuest 30f1d10948 gowin: Fix X output of $alu techmap 2023-05-01 17:56:41 +02:00
YRabbit a1dd794ff8 gowin: Add all the primitives. 
Use selected data (names, ports and parameters) from vendor file for
GW1N series primitives.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-04-22 17:10:53 +10:00
Miodrag Milanović b377a39b73
Merge pull request #3727 from YosysHQ/micko/pll_bram 
MachXO2: Add PLL and EBR related primitives
 2023-04-14 09:34:30 +02:00
gatecat e56dad56c4 fabulous: Add support for LUT6s 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-04-12 18:42:09 +02:00
YRabbit f9a6c0fcbd gowin: Add serialization/deserialization primitives 
Primitives are added to convert parallel signals to serial and vice versa.

IDES4, IDES8, IDES10, IDES16, IVIDEO, OSER4, OSER8, OSER10, OSER16, OVIDEO.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-04-12 09:59:57 +01:00
Miodrag Milanovic ee3162c58d Add PLL and EBR related primitives 2023-04-10 12:39:09 +02:00
gatecat 266f81816b ecp5: Remove TRELLIS_SLICE and add TRELLIS_COMB model 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-04-06 10:18:48 +01:00
Miodrag Milanovic 9e9fae1966 Add more DFF types 2023-04-06 09:10:14 +02:00
Miodrag Milanovic d5a405d3b4 Added proper simulation model for CCU2D 2023-04-06 09:10:14 +02:00
Miodrag Milanovic 6e4c1675e7 Generate TRELLIS_DPR16X4 for lutram 2023-04-06 09:10:14 +02:00
Miodrag Milanovic 6e12da3956 machxo2: Initial support for carry chains (CCU2D) 2023-04-06 09:10:14 +02:00
Miodrag Milanovic f35bdaa527 Update Xilinx cell definitions, fixes #3699 2023-03-23 09:44:36 +01:00
Miodrag Milanovic ff9f1fb86e Start unification effort for machxo2 and ecp5 2023-03-20 09:58:41 +01:00
Miodrag Milanovic 4d7e9e2e5d Add additional iopad_external_pin attributes 2023-03-20 09:17:22 +01:00
Miodrag Milanovic db367bd69e Add iopad_external_pin to some basic io primitives 2023-03-20 09:17:22 +01:00
Miodrag Milanovic 10589c57bf insert IO buffers for ECP5, off by default 2023-03-20 09:17:22 +01:00
Stefan Riesenberger baa3659ea5 ice40: Fix path delay definitions 
Parallel connections do not allow matching different bit widths.
A full connection has to be used instead.
Allows iverilog to parse the simulation library with hardware path delays enabled.
 2023-03-10 10:48:05 +01:00
N. Engelhardt 1a3ff0d926
Merge pull request #3688 from pu-cc/gatemate-reginit 2023-03-01 09:49:14 +01:00
Miodrag Milanović bb28e48136
Merge pull request #3663 from uis246/master 
gowin: Add new types of oscillator
 2023-02-28 06:56:01 +01:00
Miodrag Milanović 4ff9063145
Merge pull request #3652 from martell/elvds 
gowin: Add support for emulated differential output
 2023-02-28 06:55:25 +01:00
gatecat 2ab3747cc9 fabulous: Add support for mapping carry chains 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-02-27 09:50:34 +01:00
Oliver Keszöcze fc56978703
Check DREG attribute 
The DSP48E1 implementation checked the wrong attribute (i.e. CREG) to initialize the D input register. This PR fixes 3680
 2023-02-17 17:54:41 +01:00
gatecat 25e7cb3bbb fabulous: Add CLK to BRAM interface primitives 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-02-16 12:55:53 +01:00
Patrick Urban 2c7ba0e752 gatemate: Enable register initialization 2023-02-15 17:29:01 +01:00
Patrick Urban f37073050b gatemate: Update CC_PLL parameters 2023-02-14 12:02:41 +01:00
Patrick Urban 6a7d5257cd gatemate: Add CC_USR_RSTN primitive 2023-02-14 12:02:41 +01:00