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Commit Graph

104 Commits

Author SHA1 Message Date
Claire Xenia Wolf fe9689c136 Fixed Verific parser error in ice40 cell library 
non-net output port 'Q' cannot be initialized at declaration in SystemVerilog mode
 2021-10-19 12:33:18 +02:00
Sylvain Munaut 3806b07303 ice40: Fix typo in SB_CARRY specify for LP/UltraPlus 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2021-08-17 14:33:30 +02:00
Claire Xenia Wolf 06b99950ed Fix icestorm links 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-06-09 12:39:12 +02:00
Claire Xenia Wolf 46d3f03d27 Add default assignments to other SB_* simulation models 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-04-20 18:52:36 +02:00
Claire Xenia Wolf 8aee80040d Add default assignments to SB_LUT4 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-04-20 12:46:21 +02:00
Xark 9509444ef2 Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTH 2020-06-14 00:45:22 -07:00
Eddie Hung a323881e15 xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cells 2020-05-14 10:33:56 -07:00
Eddie Hung fe7965e0ee ice40: add synth_ice40 -dff option, support with -abc9 2020-05-14 10:33:56 -07:00
Eddie Hung 27b7ffc754 ice40: fix ICESTORM_LC process sensitivity 2020-05-12 15:40:48 -07:00
Sylvain Munaut c15ce5a73e ice40: Fix typos in SPRAM ABC9 timing specs 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2020-03-20 22:19:55 +01:00
Sylvain Munaut acd9eeef7c ice40: Fix SPRAM model to keep data stable if chipselect is low 
According to the official simulation model, and also cross-checked
on real hardware, the data output of the SPRAM when chipselect is
low is kept stable. It doesn't go undefined.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2020-03-14 21:01:42 +01:00
Eddie Hung 69f1555058 ice40: fix specify for ICE40_{LP,U} 2020-03-05 08:11:49 -08:00
Eddie Hung 0930c00f03 ice40: fix implicit signal in specify, also clamp negative times to 0 2020-03-04 15:28:17 -08:00
Eddie Hung 6bd9550100 ice40: add delays to SB_CARRY 2020-02-27 10:17:29 -08:00
Eddie Hung aa969f8778 More +/ice40/cells_sim.v fixes 2020-02-27 10:17:29 -08:00
Eddie Hung 3728ef1765 ice40: fix specify for inverted clocks 2020-02-27 10:17:29 -08:00
Eddie Hung a76520112d ice40: specify fixes 2020-02-27 10:17:29 -08:00
Eddie Hung fb60d82971 ice40: move over to specify blocks for -abc9 2020-02-27 10:17:29 -08:00
Eddie Hung 81e6b040a4 ice40: add SB_SPRAM256KA arrival time 2020-01-24 12:17:09 -08:00
David Shah e135ed5d80 ice40: Add post-pnr ICESTORM_RAM model and fix FFs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-23 18:44:34 +01:00
David Shah 37dd3ad3fe ice40: Support for post-pnr timing simulation 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-23 12:03:31 +01:00
Eddie Hung aae2b9fd9c Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
Eddie Hung 9fef1df3c1 Panic over. Model was elsewhere. Re-arrange for consistency 2019-10-04 10:48:44 -07:00
Eddie Hung e8e3830868 Comment out SB_MAC16 arrival time for now, need to handle all its modes 2019-08-28 19:09:29 -07:00
Eddie Hung 309684af16 Add arrival for SB_MAC16.O 2019-08-28 19:07:28 -07:00
Eddie Hung efa4ee5c0e Add arrival times for U 2019-08-28 19:03:29 -07:00
Eddie Hung 0f4e9f6bc5 Round not floor 2019-08-28 18:57:34 -07:00
Eddie Hung 927f1e3754 Add LP timings 2019-08-28 18:56:25 -07:00
Eddie Hung e3709e5ee6 LX -> LP 2019-08-28 18:51:14 -07:00
Eddie Hung 070f3ac561 Merge remote-tracking branch 'origin/eddie/fix_carry_wrapper' into xaig_arrival 2019-08-28 17:29:25 -07:00
Eddie Hung d46d38e4d5 Trailing comma 2019-08-28 17:25:54 -07:00
Eddie Hung 2421cb3fed Add arrival times for HX devices 2019-08-28 17:21:37 -07:00
Eddie Hung 129df7184a Update to new $__ICE40_CARRY_WRAPPER 2019-08-28 17:07:07 -07:00
Eddie Hung a270af00cc Put abc_* attributes above port 2019-08-23 11:21:44 -07:00
Eddie Hung d81a090d89 Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro 2019-08-19 09:56:17 -07:00
Eddie Hung 1c57b1e7ea Update abc_* attr in ecp5 and ice40 2019-08-16 15:56:57 -07:00
David Shah 79f14c7514 ice40/cells_sim.v: Fix sign of J and K partial products 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-19 17:33:41 +01:00
David Shah 3c84271543 ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-19 17:13:34 +01:00
Eddie Hung 5fb27c071b $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark 2019-07-15 12:03:51 -07:00
Eddie Hung a79ff2501e Add new box to cells_sim.v 2019-07-12 00:52:19 -07:00
Eddie Hung 4daa746797 Remove noise from ice40/cells_sim.v 2019-06-27 16:11:39 -07:00
Eddie Hung 9398921af1 Refactor for one "abc_carry" attribute on module 2019-06-27 16:07:14 -07:00
Eddie Hung 63182ed57d Fix and cleanup ice40 boxes for carry in/out 2019-06-22 14:27:41 -07:00
Eddie Hung ee428f73ab Remove WIP ABC9 flop support 2019-06-14 10:37:52 -07:00
Eddie Hung f9433cc34b Remove abc_flop{,_d} attributes from ice40/cells_sim.v 2019-06-12 09:29:30 -07:00
Eddie Hung 352c532bb2 Merge remote-tracking branch 'origin/master' into xc7mux 2019-06-10 11:02:54 -07:00
Simon Schubert abf90b0403 ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k 2019-06-10 11:49:08 +02:00
Eddie Hung 0092770317 Make SB_LUT4 a whitebox, SB_DFF a blackbox (for now) 2019-06-03 12:34:55 -07:00
Eddie Hung 9f44a71715 Consistent with xilinx 2019-06-03 09:23:43 -07:00
Eddie Hung eb08e71bd1 Merge branch 'xaig' into xc7mux 2019-05-31 13:03:03 -07:00