riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
13,435 Commits 87 Branches 48 Tags 34 MiB
Commit Graph

3 Commits

Author SHA1 Message Date
Martin Povišer 4903f99f85 quicklogic: Add missing `RAM_INIT` param on TDP36K sim model 2023-12-04 15:52:03 +01:00
N. Engelhardt 6682693888 change ql-bram-types pass to use mode parameter; clean up primitive libraries 2023-12-04 15:52:02 +01:00
N. Engelhardt 48c1fdc33d add qlf_k6n10f architecture + bram inference 
(Copied from QuickLogic Yosys plugin repo)
 2023-12-04 15:52:02 +01:00