7 Commits

Author	SHA1	Message	Date
Clifford Wolf	db98a18edb	Enabled AST/Verilog front-end optimizations per default	2013-06-10 13:19:04 +02:00
Johann Glaser	10a195c0a1	added option '-Dname[=definition]' to command 'read_verilog'	2013-05-19 17:07:52 +02:00
Clifford Wolf	7bfc7b61a8	Implemented proper handling of stub placeholder modules	2013-03-28 09:20:10 +01:00
Clifford Wolf	df9753d398	Added mem2reg option to verilog frontend	2013-03-24 11:13:32 +01:00
Clifford Wolf	8a6b0a3520	Added help messages to ilang and verilog frontends	2013-03-01 08:03:00 +01:00
Clifford Wolf	a321a5c412	Moved stand-alone libs to libs/ directory and added libs/subcircuit	2013-02-27 09:32:19 +01:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00