yosys

Commit Graph

Author	SHA1	Message	Date
Zachary Snow	0d8e5d965f	Sign extend port connections where necessary - Signed cell outputs are sign extended when bound to larger wires - Signed connections are sign extended when bound to larger cell inputs - Sign extension is performed in hierarchy and flatten phases - genrtlil indirects signed constants through signed wires - Other phases producing RTLIL may need to be updated to preserve signedness information - Resolves #1418 - Resolves #2265	2020-12-18 20:33:14 -07:00

Author

SHA1

Message

Date

Zachary Snow

0d8e5d965f

Sign extend port connections where necessary

- Signed cell outputs are sign extended when bound to larger wires
- Signed connections are sign extended when bound to larger cell inputs
- Sign extension is performed in hierarchy and flatten phases
- genrtlil indirects signed constants through signed wires
- Other phases producing RTLIL may need to be updated to preserve
  signedness information
- Resolves #1418
- Resolves #2265

2020-12-18 20:33:14 -07:00

1 Commits