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10495 Commits

Author SHA1 Message Date
Dan Ravensloft 3b534a203a intel_alm: fix typo in MISTRAL_MUL27X27 cell name 2020-08-13 17:08:50 +02:00
Yosys Bot f61d62a7bc Bump version 2020-08-13 00:10:08 +00:00
whitequark a74a43d85d
Merge pull request #2340 from andy-knowles/cxxrtl-fix-alu-carryout 
cxxrtl.h: Fix incorrect CarryOut in alu when Bits % 32 != 0 && Invert == False
 2020-08-12 20:02:18 +00:00
Andy Knowles 5829d16fcd
cxxrtl.h: Fix incorrect CarryOut in alu() 2020-08-12 21:04:34 +02:00
Dan Ravensloft 97daf612cb intel_alm: add more megafunctions. NFC. 2020-08-12 18:39:22 +02:00
Andy Knowles 1227c3681b cxxrtl.h: Fix incorrect CarryOut in alu when Bits % 32 != 0 && Invert == False 2020-08-12 11:32:57 +02:00
Yosys Bot 04f6158bf2 Bump version 2020-08-10 09:30:51 +00:00
Zachary Snow 2ee0b8ebea Propagate const_fold through generate blocks and branches 2020-08-09 17:21:08 -04:00
Zachary Snow 96ec9acf84 Allow %0s $display format specifier 2020-08-09 17:19:49 -04:00
Marcelina Kościelnicka 2ab350a7b0 opt_clean: Fix module keep rules. 
- wires with keep attribute now force a module to be kept
- presence of $memwr and $meminit cells no longer forces a module to be
  kept
 2020-08-09 13:57:00 +02:00
Marcelina Kościelnicka 54a0c083a1 Remove now-redundant dff2dffe pass. 2020-08-07 13:21:34 +02:00
Marcelina Kościelnicka 5693386a4e Remove now-redundant dff2dffs pass. 2020-08-07 13:21:34 +02:00
Marcelina Kościelnicka a0e99a9f3f peepopt: Remove now-redundant dffmux pattern. 2020-08-07 13:21:34 +02:00
Marcelina Kościelnicka acd8c5c205 Remove now-redundant opt_rmdff pass. 2020-08-07 13:21:34 +02:00
Marcelina Kościelnicka 9a4f420b4b Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00
Sahand Kashani 5157f5623e Add support for real-valued parameters + preserve type of parameters 
This commit adds support for real-valued parameters in blackboxes. Additionally,
parameters now retain their types are no longer all encoded as strings.

There is a caveat with this implementation due to my limited knowledge of yosys,
more specifically to how yosys encodes bitwidths of parameter values. The example
below can motivate the implementation choice I took. Suppose a verilog component
is declared with the following parameters:

            parameter signed [26:0] test_signed;
            parameter        [26:0] test_unsigned;
            parameter signed [40:0] test_signed_large;

If you instantiate it as follows:

            defparam <inst_name> .test_signed = 49;
            defparam <inst_name> .test_unsigned = 40'd35;
            defparam <inst_name> .test_signed_large = 40'd12;

If you peek in the RTLIL::Const structure corresponding to these params, you
realize that parameter "test_signed" is being considered as a 32-bit value
since it's declared as "49" without a width specifier, even though the parameter
is defined to have a maximum width of 27 bits.

A similar issue occurs for parameter "test_unsigned" where it is supposed to take
a maximum bit width of 27 bits, but if the user supplies a 40-bit value as above,
then yosys considers the value to be 40 bits.

I suppose this is due to the type being defined by the RHS rather than the definition.
Regardless of this, I emit the same widths as what the user specifies on the RHS when
generating firrtl IR.
 2020-08-06 00:49:55 +02:00
Marcelina Kościelnicka c1ed1c28be peeopt.shiftmul: Add a signedness check. 
Fixes #2332.
 2020-08-05 21:01:20 +02:00
Marcelina Kościelnicka b4a4cb081d techmap.CONSTMAP: Handle outputs before inputs. 
Fixes #2321.
 2020-08-05 12:28:18 +02:00
Marcelina Kościelnicka e89cc9c02f peepopt.muldiv: Add a signedness check. 
Fixes #2318.
 2020-08-04 16:30:24 +02:00
Lukasz Dalek daee2d967f Add test for subarray access on multidimensional arrays 
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
 2020-08-03 17:07:33 +02:00
Lukasz Dalek ba08c25133 Fix subarray access condition 
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
 2020-08-03 16:16:04 +02:00
Lukasz Dalek 6e78f3a197 Test multirange (unpacked) arrays size 
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
 2020-08-03 15:34:55 +02:00
Lukasz Dalek 83ddc62034 Rewrite multirange arrays sizes [n] as [n-1:0] 
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
 2020-08-03 14:48:27 +02:00
Marcelina Kościelnicka 522788f016 techmap: Add support for [] wildcards in techmap_celltype. 
Fixes #1826.
 2020-08-02 22:46:48 +02:00
Zachary Snow c3e95eb1ab Fix generate scoping issues 
- expand_genblock defers prefixing of items within named sub-blocks
- Allow partially-qualified references to local scopes
- Handle shadowing within generate blocks
- Resolve generate scope references within tasks and functions
- Apply generate scoping to genvars
- Resolves #2214, resolves #1456
 2020-07-31 20:32:47 -06:00
Claire Wolf c39ebe6ae0 Bump YOSYS_VER 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-07-31 20:57:41 +02:00
Marcelina Kościelnicka 18ad56ef41 Add dffunmap pass. 
To be used with backends that cannot deal with fancy FF types (like blif
or smt).
 2020-07-31 00:59:51 +02:00
Marcelina Kościelnicka 6cd135a5eb opt_expr: Remove -clkinv option, make it the default. 
Adds -noclkinv option just in case the old behavior was actually useful
to someone.
 2020-07-31 00:08:15 +02:00
Marcelina Kościelnicka cf60699884 synth_ice40: Use opt_dff. 
The main part is converting ice40_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the mux patterns on
its own.

The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.
 2020-07-30 22:26:20 +02:00
Marcelina Kościelnicka 8501342fc5 synth_xilinx: Use opt_dff. 
The main part is converting xilinx_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the patterns on its
own.

The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.
 2020-07-30 22:26:09 +02:00
Marcelina Kościelnicka 4a05cad7f8 async2sync: Support all FF types. 2020-07-30 20:22:03 +02:00
Marcelina Kościelnicka af6623ebb8 Add opt_dff pass. 2020-07-30 18:27:04 +02:00
Marcelina Kościelnicka 8fd43515c5 verilog_backend: Add handling for all FF types. 2020-07-30 18:22:36 +02:00
Miodrag Milanović 2f50c5af48
Merge pull request #2314 from YosysHQ/verifix_errorfix 
Verific - prevent exit yosys due to stored error
 2020-07-29 15:41:26 +02:00
Miodrag Milanovic cc02d58194 Clear last error message 2020-07-29 15:28:33 +02:00
Marcelina Kościelnicka dc18bf1969 opt_expr: Fix handling of $_XNOR_ cells with A = B. 
Fixes #2311.
 2020-07-29 12:41:43 +02:00
Marcelina Kościelnicka 773b056ffb ffinit: Fortify the code a bit. 
This fixes handling of messy cases involving repeatedly setting and
removing the same init bit.
 2020-07-28 17:21:15 +02:00
clairexen 45e96d5d87
Merge pull request #2301 from zachjs/for-loop-errors 
Clearer for loop error messages
 2020-07-28 14:07:26 +02:00
clairexen 66afed6f55
Merge pull request #2306 from YosysHQ/mwk/equiv_induct-undef 
equiv_induct: Fix up assumption for $equiv cells in -undef mode.
 2020-07-28 12:56:22 +02:00
Marcelina Kościelnicka a1a0abf52a equiv_induct: Fix up assumption for $equiv cells in -undef mode. 
Before this fix, equiv_induct only assumed that one of the following is
true:

- defined value of A is equal to defined value of B
- A is undefined

This lets through valuations where A is defined, B is undefined, and
the defined (meaningless) value of B happens to match the defined value
of A.  Instead, tighten this up to OR of the following:

- defined value of A is equal to defined value of B, and B is not
  undefined
- A is undefined
 2020-07-27 18:36:13 +02:00
Dan Ravensloft a2fb84fd0c intel_alm: direct M10K instantiation 
This reverts commit a3a90f6377.
 2020-07-27 15:39:06 +02:00
Dan Ravensloft 62311b7ec0 intel_alm: increase abc9 -W 2020-07-26 23:56:54 +02:00
clairexen 9bcde4d82b
Merge pull request #2299 from zachjs/arg-loop 
Avoid generating wires for function args which are constant
 2020-07-26 21:34:55 +02:00
Zachary Snow 58da181af9 Clearer for loop error messages 2020-07-25 10:37:16 -06:00
Zachary Snow f69daf4830 Allow blocks with declarations within constant functions 2020-07-25 10:16:12 -06:00
Zachary Snow 59c4ad8ed3 Avoid generating wires for function args which are constant 2020-07-24 21:18:24 -06:00
Marcelina Kościelnicka bd959d5d9e async2sync: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka c9251eb26b memory_dff: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka 557f81cb49 proc_dlatch: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka 31d6107521 pmux2shift: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00