yosys

Commit Graph

Author	SHA1	Message	Date
Pepijn de Vos	c2d358484f	Gowin: deal with active-low tristate (#2971 ) * deal with active-low tristate * remove empty port * update sim models * add expected lut1 to tests	2021-08-20 21:21:06 +02:00
Konrad Beckmann	5b9a975eba	synth_gowin: Add rPLL blackbox	2020-11-11 17:06:54 +01:00
Dan Ravensloft	7f45cab27a	synth_gowin: ABC9 support This adds ABC9 support for synth_gowin; drastically improving synthesis quality.	2020-07-05 22:07:17 +02:00
Marcelina Kościelnicka	9beed4d771	gowin: Fix INIT values in sim library.	2020-07-05 03:03:48 +02:00
Pepijn de Vos	0f6269b04c	add IOBUF	2019-10-28 15:33:05 +01:00
Pepijn de Vos	903f997391	add tristate buffer and test	2019-10-28 15:18:01 +01:00
Pepijn de Vos	f88335a8a5	add wide luts	2019-10-28 12:49:08 +01:00
Pepijn de Vos	8226f2db0b	ALU sim tweaks	2019-10-24 13:39:43 +02:00
Pepijn de Vos	8a2699c40c	add negedge DFF	2019-10-21 12:31:11 +02:00
Pepijn de Vos	af7bdd598e	use ADDSUB ALU mode to remove inverters	2019-10-21 12:00:27 +02:00
Pepijn de Vos	72323e11a4	remove duplicate DFFR	2019-10-16 11:24:56 +02:00
Pepijn de Vos	2fb20f184a	Revert "add MUX support" It turns out that they make everything worse and they don't PnR. This reverts commit `3eff2271d0`.	2019-09-06 11:28:17 +02:00
Pepijn de Vos	1b9f7f49b5	add more DFF to sim lib	2019-09-06 09:01:07 +02:00
Pepijn de Vos	5168b6ffa4	WIP aditional DFF primitives	2019-09-05 19:12:47 +02:00
Pepijn de Vos	3eff2271d0	add MUX support	2019-09-05 13:36:41 +02:00
Diego	f9272fc56d	GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow	2019-04-12 23:40:02 -05:00
Diego H	819ca73096	Changes in GoWin synth commands and ALU primitive support	2018-12-03 20:08:35 -06:00
Clifford Wolf	e9d73d2ee0	Indenting fixes in gowin sim cell lib	2016-11-08 18:54:00 +01:00
Clifford Wolf	cae5131bac	Added initial version of "synth_gowin"	2016-11-01 11:31:13 +01:00

19 Commits