Commit Graph

1200 Commits

Author SHA1 Message Date
N. Engelhardt 4af04be0b7 add IdString::isPublic() 2020-09-03 17:37:58 +02:00
whitequark 00e7dec7f5 Replace "ILANG" with "RTLIL" everywhere.
The only difference between "RTLIL" and "ILANG" is that the latter is
the text representation of the former, as opposed to the in-memory
graph representation. This distinction serves no purpose but confuses
people: it is not obvious that the ILANG backend writes RTLIL graphs.

Passes `write_ilang` and `read_ilang` are provided as aliases to
`write_rtlil` and `read_rtlil` for compatibility.
2020-08-26 17:29:32 +00:00
Xiretza 916028906a Ensure \A_SIGNED is never used with $shiftx
It has no effect on the output ($shiftx doesn't perform any sign
extension whatsoever), so an attempt to use it should be caught early.
2020-08-18 19:36:24 +02:00
Xiretza 928fd40c2e Respect \A_SIGNED for $shift
This reflects the behaviour of $shr/$shl, which sign-extend their A
operands to the size of their output, then do a logical shift (shift in
0-bits).
2020-08-18 19:36:24 +02:00
Marcelina Kościelnicka 4a05cad7f8 async2sync: Support all FF types. 2020-07-30 20:22:03 +02:00
Marcelina Kościelnicka 773b056ffb ffinit: Fortify the code a bit.
This fixes handling of messy cases involving repeatedly setting and
removing the same init bit.
2020-07-28 17:21:15 +02:00
Marcelina Kościelnicka 0c6d0d4b5d satgen: Add support for dffe, sdff, sdffe, sdffce cells. 2020-07-24 03:19:21 +02:00
Marcelina Kościelnicka dafe04d559 Add utility module for representing flip-flops. 2020-07-23 23:39:46 +02:00
Marcelina Kościelnicka 022af4f0ca Add utility module for dealing with init attributes. 2020-07-23 20:49:48 +02:00
Marcelina Kościelnicka dc07ae9677 techmap: Add _TECHMAP_CELLNAME_ special parameter.
This parameter will resolve to the name of the cell being mapped.  The
first user of this parameter will be synth_intel_alm's Quartus output,
which requires a unique (and preferably descriptive) name passed as
a cell parameter for the memory cells.
2020-07-21 15:00:54 +02:00
Marcelina Kościelnicka 3cb401db8c celltypes: Fix EN port name for some FF types. 2020-07-20 23:04:10 +02:00
Marcelina Kościelnicka 85a1bb17ed satgen: Move importCell out of the header.
This function has no hope of ever getting inlined anyway, and it speeds
up yosys compile time by 7%.
2020-07-19 00:17:02 +02:00
whitequark d9f680b236 verilog_backend: add `-sv` option, make `-o <filename>.sv` work.
See #2271.
2020-07-16 10:44:08 +00:00
clairexen c7d71f436d
Merge pull request #2168 from whitequark/assert-unused-exprs
Use (and ignore) the expression provided to log_assert in NDEBUG builds
2020-06-25 18:21:51 +02:00
clairexen 21209d632e
Merge pull request #2135 from boqwxp/qbfsat-timeinfo
log and qbfsat: Also include child process usage in `PerformanceTimer::query()` and report the time for each call to the QBF-SAT solver
2020-06-25 18:18:09 +02:00
Marcelina Kościelnicka e71d827590 Add add* functions for the new FF types 2020-06-23 15:40:02 +02:00
Marcelina Kościelnicka b0bee396a8 Add new builtin FF types
The new types include:

- FFs with async reset and enable (`$adffe`, `$_DFFE_[NP][NP][01][NP]_`)
- FFs with sync reset (`$sdff`, `$_SDFF_[NP][NP][01]_`)
- FFs with sync reset and enable, reset priority (`$sdffs`, `$_SDFFE_[NP][NP][01][NP]_`)
- FFs with sync reset and enable, enable priority (`$sdffce`, `$_SDFFCE_[NP][NP][01][NP]_`)
- FFs with async reset, set, and enable (`$dffsre`, `$_DFFSRE_[NP][NP][NP][NP]_`)
- latches with reset or set (`$adlatch`, `$_DLATCH_[NP][NP][01]_`)

The new FF types are not actually used anywhere yet (this is left
for future commits).
2020-06-23 15:40:02 +02:00
Alberto Gonzalez 28c2dd470b
log: Remove unused `_POSIX_TIMERS` branch in `PerformanceTimer::query()`. 2020-06-21 02:16:52 +00:00
Alberto Gonzalez a564cc806f
log, qbfsat: Include child process time in `PerformanceTimer::query()` and report the time for each call to the QBF-SAT solver. 2020-06-21 02:16:52 +00:00
Alberto Gonzalez 08cede4669
qbfsat: Simplify solution format and replace `SigBit::str()` with `log_signal()`.
Co-Authored-By: Claire Wolf <claire@symbioticeda.com>
2020-06-21 02:16:11 +00:00
Alberto Gonzalez a3d1f8637a
qbfsat: Use bit precise mapping for hole value wires and a more robust hole spec for writing to and specializing from a solution file. 2020-06-21 02:16:11 +00:00
whitequark 992d694d39
Merge pull request #2177 from boqwxp/dict-iterator-jump
hashlib, rtlil: Add `operator+()` and `operator+=()` to `dict` iterators
2020-06-21 02:05:12 +00:00
Alberto Gonzalez d71a9badda
dict: Remove guard for past-the-end iterators that might mask problems in static analysis.
Co-Authored-By: whitequark <whitequark@whitequark.org>
2020-06-19 21:04:29 +00:00
Alberto Gonzalez 3ccdab940c
rtlil: Add `Design::select()` for selecting whole modules. 2020-06-19 18:16:33 +00:00
Alberto Gonzalez e5a2d17b5d
hashlib, rtlil: Add `operator+=()` to `dict<>::iterator` and `dict<>::const_iterator` and add `operator+()` and `operator+=()` to `ObjIterator`. 2020-06-19 17:44:29 +00:00
whitequark c8c3c7af87 Use [[maybe_unused]] instead of YS_ATTRIBUTE(unused).
[[maybe_unused]] is available since C++17, so this commit adds
a polyfill YS_MAYBE_UNUSED. Once we require C++17 we can drop it.
2020-06-19 15:48:58 +00:00
whitequark 118e4caa37 Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug(). 2020-06-19 15:48:58 +00:00
whitequark 21692c4a2e Use (and ignore) the expression provided to log_debug in NDEBUG builds. 2020-06-19 15:48:58 +00:00
whitequark 2ffdb74fb1 Use (and ignore) the expression provided to log_assert in NDEBUG builds.
This avoids warnings in NDEBUG builds emitted when a variable is only
used in log_assert, but is always defined.
2020-06-19 15:48:58 +00:00
Xiretza 817411044a
Add missing [[noreturn]] to log_file_error()
Previously this was tagged only with YS_ATTRIBUTE(noreturn), but not
YS_NORETURN, so it got lost in #2173, resulting in warnings in
frontends/ast/simplify.cc:

frontends/ast/simplify.cc:267:1: warning: function declared 'noreturn' should not return [-Winvalid-noreturn]
}
^
frontends/ast/simplify.cc:379:1: warning: function declared 'noreturn' should not return [-Winvalid-noreturn]
}
^
2020-06-19 11:46:06 +02:00
whitequark 60478a8e3a Use C++11 [[noreturn]] attribute. 2020-06-19 01:06:48 +00:00
whitequark 7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
Anonymous Maarten c9c13c29df MSVC defines TRANSPARENT too 2020-06-17 15:10:08 +02:00
whitequark 7137f99658 kernel: guard include of signal.h more precisely.
Upgrading to WASI SDK 11.0 caused the WASM build to fail because WASM
does not have signals. (Arguably Yosys was broken even before, it was
just broken silently.)
2020-06-13 22:37:04 +00:00
whitequark 483a1081e7 RTLIL: add Module::addProcess, use it in Module::cloneInto. NFC. 2020-06-09 09:55:48 +00:00
whitequark fbb346ea91 flatten: preserve original object names via hdlname attribute. 2020-06-08 20:19:41 +00:00
whitequark e558905598 RTLIL: use {get,set}_string_attribute in {get,set}_strpool_attribute.
The only difference in behavior is that this removes the attribute
when the pool becomes empty.
2020-06-08 20:19:41 +00:00
clairexen 369dcb4e82
Merge pull request #2085 from rswarbrick/select
Silence warning in select.cc and pass some more args by ref
2020-06-08 15:55:52 +02:00
clairexen fbd0d8d5f0
Merge pull request #2105 from whitequark/split-flatten-off-techmap
Split `flatten` from `techmap` and simplify it
2020-06-08 15:27:15 +02:00
whitequark 3bffd09d64
Merge pull request #2006 from jersey99/signed-in-rtlil-wire
Preserve 'signed'-ness of a verilog wire through RTLIL
2020-06-04 11:23:06 +00:00
N. Engelhardt 44f1e65155
Merge pull request #2070 from hackfin/master
Pyosys API: idict type handling
2020-06-04 11:17:08 +02:00
whitequark 9338ff66b9 RTLIL: factor out RTLIL::Module::addMemory. NFC. 2020-06-04 00:02:12 +00:00
clairexen ff785cdb46
Merge pull request #1862 from boqwxp/cleanup_techmap
Clean up `passes/techmap/techmap.cc`
2020-05-31 20:40:48 +02:00
clairexen 94c1035389
Merge pull request #1885 from Xiretza/mod-rem-cells
Fix modulo/remainder semantics
2020-05-29 16:37:23 +02:00
clairexen af36afe722
Merge pull request #2092 from whitequark/rtlil-no-space-control
Restrict RTLIL::IdString to not contain whitespace or control chars
2020-05-29 16:31:44 +02:00
whitequark efa7424fb9 Restrict RTLIL::IdString to not contain whitespace or control chars.
This is an existing invariant (most backends can't cope with these)
but one that was not checked or documented.
2020-05-29 06:43:18 +00:00
Xiretza 7c89738382
Add comments for mod/div semantics to rtlil.h 2020-05-28 22:59:04 +02:00
Xiretza edd8ff2c07
Add flooring division operator
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $divfloor cell provides this flooring division.

This commit also fixes the handling of $div in opt_expr, which was
previously optimized as if it was $divfloor.
2020-05-28 22:59:04 +02:00
Xiretza 17163cf43a
Add flooring modulo operator
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $modfloor cell provides this flooring modulo (also known as "remainder"
in several languages, but this name is ambiguous).

This commit also fixes the handling of $mod in opt_expr, which was
previously optimized as if it was $modfloor.
2020-05-28 22:59:03 +02:00
whitequark 02bb52eef1
Merge pull request #2088 from rswarbrick/count-at
Minor optimisation in Module::wire() and Module::cell()
2020-05-28 09:41:17 +00:00
whitequark 8a44a46806
Merge pull request #2086 from rswarbrick/sigbit
Use default copy constructor for RTLIL::SigBit
2020-05-28 09:40:49 +00:00
Rupert Swarbrick d681c9df85 Pass some more args by reference in select.cc
Before this patch, the code passed around std::string objects by
value. It's probably not a hot-spot, but it can't hurt to avoid the
copying.

Removing the copy and clean-up code means the resulting code is ~6.1kb
smaller when compiled with GCC 9.3 and standard settings.
2020-05-27 09:42:23 +01:00
Rupert Swarbrick 7ff306ccdb Minor optimisation in Module::wire() and Module::cell()
The existing code does a search to figure out whether id is in the
dict (with the call to count()), and then looks it up again to get the
result (with the call to at()). This version calls find() instead,
avoiding the double lookup.

Code size increases slightly (6kb). I think this is because the
contents of find() are getting inlined, and then inlined into lots of
the callsites for cell() and wire().

Looking at the compiled code before this patch, you just get
a (non-inlined) call to count() followed by a call to at(). After the
patch, the contents of find() have been inlined (so you see do_hash,
then do_lookup). The result for each function is about 30 bytes / 40%
bigger, which presumably also enlarges call-sites that inline it.
2020-05-26 16:07:36 +01:00
Rupert Swarbrick 17b5f23f20 Use default copy constructor for RTLIL::SigBit
There was a handwritten copy constructor, which I'm not sure was
actually legal C++ (it unconditionally read from the 'data' member of
a union, which wouldn't have been written if wire was true). It was
also a bit less efficient than the constructor you get from the
compiler by default (which is allowed to just copy the memory).

This gives a marginal (~0.25%) decrease in code size when compiled
with GCC 9.3.
2020-05-26 13:18:01 +01:00
Rupert Swarbrick 8f87ccec9b Use c_str(), not str() for IdString/std::string == and != operators
These operators work by fetching the string from the global string
table and then comparing with the std::string that was passed in as
rhs.

Using str() means that we create a std::string (strlen; malloc;
memcpy), compare for equality (another memcmp if they have the same
length) and then finally free the string.

Using c_str() means that we pass the const char* straight to
std::string's equality operator. This ends up as a call to
std::string::compare (the const char* flavour), which is essentially
strcmp.
2020-05-26 12:27:15 +01:00
Miodrag Milanović 637650597b
Merge pull request #2059 from boqwxp/logger-vector-to-dict
log: Use `dict` instead of `std::vector<std::pair>` for `log_expect_{error, warning, log}` to better express the intent that each element is unique.
2020-05-21 15:36:30 +02:00
N. Engelhardt 026fed3135
Merge pull request #2046 from PeterCrozier/trap
Extend YS_DEBUGTRAP to MacOS.
2020-05-20 10:12:24 +02:00
Alberto Gonzalez 6eea4b3d79
kernel: Try an order-independent approach to hashing `dict`.
Co-Authored-By: David Shah <dave@ds0.me>
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-05-19 23:32:53 +00:00
Martin 43c34a7828 idict handling in wrapper
- Also, re-applied no-line-break workaround to rtlil.h to make parser
  catch all methods.
2020-05-19 11:13:49 +02:00
Marcelina Kościelnicka aee439360b Add force_downto and force_upto wire attributes.
Fixes #2058.
2020-05-19 01:42:40 +02:00
Alberto Gonzalez 8297afe925
log: Use `dict` instead of `std::vector<std::pair>` for `log_expect_{error, warning, log}` to better express the intent that each element is unique. 2020-05-15 00:55:32 +00:00
Eddie Hung 67fc0c3698 abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_
instead of moving them to $__ prefix
2020-05-14 16:44:35 -07:00
Alberto Gonzalez 976edb7597
kernel: Ensure `dict` always hashes to the same value given the same contents. 2020-05-14 20:06:55 +00:00
Alberto Gonzalez 35b94d1f66
kernel: Re-implement `dict` hash code as a `dict` member function instead of a specialized template for `hash_ops`. 2020-05-14 20:06:55 +00:00
Eddie Hung dabeb1e8a1
techmap: prefix special wires with backslash for use as IdString 2020-05-14 20:06:55 +00:00
Alberto Gonzalez 2fb4931e5b
Add specialized `hash()` for type `dict` and use a `dict` instead of a `std::map` for `techmap_cache` and `techmap_do_cache`. 2020-05-14 20:06:53 +00:00
Eddie Hung 7146c0339e timinginfo: ignore $specify2 cells if EN is false 2020-05-14 10:33:56 -07:00
Eddie Hung b3e2538a14 abc9_ops: fix bypass boxes using (* abc9_bypass *) 2020-05-14 10:33:56 -07:00
Eddie Hung 7812a2959b kernel: TimingInfo to clamp -ve setup/edge-sensitive delays to zero 2020-05-14 10:33:56 -07:00
Eddie Hung b66904e9cd Revert "Merge branch 'eddie/kernel_makeblackbox' into eddie/abc9_auto_dff"
This reverts commit e08497c7c9d8a6f7a3eccddf2149c45d9ecff207, reversing
changes made to e366fd55122236a21c6daee6765724add840a1f9.
2020-05-14 10:33:56 -07:00
Eddie Hung 039c3a5982 kernel: Module::makeblackbox() to clear connections + delete wires last 2020-05-14 10:33:56 -07:00
Peter Crozier 495dcfc812 Consolidate Linux and Mac version of YS_DEBUGTRAP_IF_DEBUGGING. 2020-05-13 14:17:00 +01:00
Peter Crozier 3988f935b8 Extend YS_DEBUGTRAP to MacOS. 2020-05-13 13:11:49 +01:00
Claire Wolf 8ec3b6db1c Fix clang compiler warning
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-08 10:13:39 +02:00
whitequark ebfdf61eb9
Merge pull request #2022 from Xiretza/fallthroughs
Avoid switch fall-through warnings
2020-05-08 05:30:32 +00:00
Claire Wolf 0610424940
Merge pull request #2005 from YosysHQ/claire/fix1990
Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
2020-05-07 18:11:48 +02:00
Xiretza 695150b037
Add YS_FALLTHROUGH macro to mark case fall-through
C++17 introduced [[fallthrough]], GCC and clang had their own vendored
attributes before that. MSVC doesn't seem to have such a warning at all.
2020-05-07 13:39:34 +02:00
Eddie Hung 22bf22fab4 frontend: cleanup to use more ID::*, more dict<> instead of map<> 2020-05-04 10:48:37 -07:00
whitequark d1c8837572
Merge pull request #2000 from whitequark/log_error-trap
kernel: Trap in `log_error()` when a debugger is attached
2020-05-03 16:19:42 +00:00
whitequark e9f2d3f009 kernel: Trap in `log_error()` when a debugger is attached.
The workflow of debugging fatal pass errors in Yosys is flawed in
three ways:
 1. Running Yosys under a debugger is sufficient for the debugger
    to catch some fatal errors (segfaults, aborts, STL exceptions)
    but not others (`log_error()`, `log_cmd_error()`). This is
    neither obvious nor easy to remember.
 2. To catch Yosys-specific fatal errors, it is necessary to set
    a breakpoint at `logv_error_with_prefix()`, or at least,
    `logv_error()`. This is neither obvious nor easy to remember,
    and GDB's autocomplete takes many seconds to suggest function
    names due to the large amount of symbols in Yosys.
 3. If a breakpoint is not set and Yosys encounters with such
    a fatal error, the process terminates. When debugging a crash
    that takes a long time to reproduce (or a nondeterministic crash)
    this can waste a significant amount of time.

To solve this problem, add a macro `YS_DEBUGTRAP` that acts as a hard
breakpoint (if available), and a macro `YS_DEBUGTRAP_IF_DEBUGGING`
that acts as a hard breakpoint only if debugger is present.

Then, use `YS_DEBUGTRAP_IF_DEBUGGING` in `logv_error_with_prefix()`
to obviate the need for a breakpoint on nearly every platform.

Co-Authored-By: Alberto Gonzalez <boqwxp@airmail.cc>
2020-05-03 12:02:34 +00:00
Claire Wolf bbbce0d1c5 Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset, fixes #1990
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
whitequark b43c282e4e Add WASI platform support.
This includes the following significant changes:
  * Patching ezsat and minisat to disable resource limiting code
    on WASM/WASI, since the POSIX functions they use are unavailable.
  * Adding a new definition, YOSYS_DISABLE_SPAWN, present if platform
    does not support spawning subprocesses (i.e. Emscripten or WASI).
    This definition hides the definition of `run_command()`.
  * Adding a new Makefile flag, DISABLE_SPAWN, present in the same
    condition. This flag disables all passes that require spawning
    subprocesses for their function.
2020-04-30 18:56:25 +00:00
Eddie Hung eabc00de8b
Merge pull request #1992 from YosysHQ/eddie/bugpoint_help
bugpoint: improve help text
2020-04-27 11:12:17 -07:00
Vamsi K Vytla 5f9cd2e2f6 Preserve 'signed'-ness of a verilog wire through RTLIL
As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now:

RTLIL::wire holds an is_signed field.
This is exported in JSON backend
This is exported via dump_rtlil command
This is read in via ilang_parser
2020-04-27 09:44:24 -07:00
Eddie Hung e602184856 bugpoint: (* keep *) to (* bugpoint_keep *); also apply to modules/cells 2020-04-24 13:26:04 -07:00
Eddie Hung d3555c667c verific: do not assert if wire not found; warn instead 2020-04-23 16:28:11 -07:00
Eddie Hung 86ab7d3a6e kernel: Cell::getParam() to throw exception again if not found
As it did before #1945
2020-04-22 16:25:23 -07:00
Eddie Hung bf22cda912
Merge pull request #1969 from boqwxp/pool_emplace
kernel: Add `pool` support for rvalue references and C++11 move semantics.
2020-04-22 12:10:42 -07:00
Eddie Hung a7c66fdc61 pool: add emplace() function 2020-04-22 08:14:07 -07:00
Alberto Gonzalez 746c29b171
kernel: Rename arguments to rvalue-reference-accepting functions. 2020-04-21 17:17:47 +00:00
Marcelina Kościelnicka b4d76309e1 Use default parameter value in getParam
Fixes #1822.
2020-04-21 19:09:00 +02:00
Marcelina Kościelnicka 06a344efcb ilang, ast: Store parameter order and default value information.
Fixes #1819, #1820.
2020-04-21 19:09:00 +02:00
Marcelina Kościelnicka 79efaa65ad idict: Make iterator go forward.
Previously, iterating over an idict returned its contents in reverse.
2020-04-21 19:09:00 +02:00
Alberto Gonzalez ecaa892e35
Add rvalue-reference-accepting `entry_t` constructor for `pool`. 2020-04-20 05:37:10 +00:00
Alberto Gonzalez 95b94ad19b
In `pool`, construct `entry_t`s in-place and add an rvalue-accepting-and-forwarding `insert()` method. 2020-04-20 02:18:30 +00:00
whitequark b6f624b56b rtlil: add AttrObject::has_attribute. 2020-04-16 21:49:49 +00:00
whitequark ff7a1a1568 rtlil: add AttrObject::{get,set}_string_attribute.
And make {get,set}_src_attribute use those functions.
2020-04-16 21:45:29 +00:00
whitequark c2804a68c2
Merge pull request #1896 from boqwxp/read_stdin_repl
Frontend: allow reading file input from stdin, like a REPL heredoc mode
2020-04-16 17:18:29 +00:00
Eddie Hung aa552cefa3
Merge pull request #1927 from YosysHQ/eddie/design_remove_assert
kernel: Design::remove(RTLIL::Module *) to check refcount_modules_
2020-04-16 08:06:12 -07:00
whitequark 90a1c6b6a4
Merge pull request #1915 from boqwxp/dict_move_semantics
kernel: Add `dict` support for rvalue references and C++11 move semantics.
2020-04-16 13:29:13 +00:00
Alberto Gonzalez 5eb1f83d2d
Rename overloaded `insert()` to `emplace()` and add overloaded versions for all possible lvalue/rvalue combinationsfor its arguments. 2020-04-16 03:54:33 +00:00
Alberto Gonzalez 76c9e1c265
Use script-style heredoc syntax for REPL heredocs. 2020-04-15 16:15:51 +00:00
Alberto Gonzalez b5ecbbef94
Allow reading file input from stdin, improving REPL experience. 2020-04-15 16:15:50 +00:00
Miodrag Milanović 3c4758c60e
Merge pull request #1894 from YosysHQ/mingw_fix
Fix compile for mingw
2020-04-15 17:43:31 +02:00
Eddie Hung dc3d432aaa
Merge pull request #1916 from YosysHQ/eddie/kernel_makeblackbox
kernel: Module::makeblackbox() to clear connections too
2020-04-15 08:42:39 -07:00
N. Engelhardt 0b7a5879e5
Merge pull request #1830 from boqwxp/qbfsat
Add `qbfsat` command to integrate exists-forall solving and specialization
2020-04-15 17:33:50 +02:00
Miodrag Milanovic bc21e58bb5 Fix compile for mingw 2020-04-15 16:38:09 +02:00
Eddie Hung 635b2b8939 kernel: Design::remove(RTLIL::Module *) to check refcount_modules_ 2020-04-14 09:31:06 -07:00
Eddie Hung 9547d8c13e kernel: Module::makeblackbox() to clear connections too 2020-04-13 20:37:22 -07:00
Alberto Gonzalez c479fdeb85
Add `dict` support for rvalue references and C++11 move semantics. 2020-04-13 23:52:16 +00:00
Miodrag Milanovic 0d789c5a3b Support custom PROGRAM_PREFIX 2020-04-10 10:38:40 +02:00
whitequark 7c06cb6157
Merge pull request #1562 from whitequark/write_cxxrtl
write_cxxrtl: new backend
2020-04-10 01:24:31 +00:00
Eddie Hung 371af7da38
Merge pull request #1858 from YosysHQ/eddie/fix1856
kernel: include "kernel/constids.inc"
2020-04-09 14:23:47 -07:00
Eddie Hung 60ffc21e64 kernel: include "kernel/constids.inc" instead of "constids.inc" 2020-04-09 09:14:03 -07:00
Marcelina Kościelnicka 516857f3ba [NFCI] Deduplicate builtin FF cell types list
A few passes included the same list of FF cell types.  Make it a global
const instead.

The zinit pass also seems to include a list like that, but given that
it seems to be completely broken at the time (see #1568 discussion),
I'm going to pretend I didn't see that.
2020-04-09 18:05:06 +02:00
whitequark d20e971725 write_cxxrtl: new backend.
This commit adds a basic implementation that isn't very performant
but implements most of the planned features.
2020-04-09 04:08:36 +00:00
Alberto Gonzalez a4598d64ef
Hole value recovery and specialization implementation for `qbfsat` command. 2020-04-04 22:13:25 +00:00
Eddie Hung 956ecd48f7 kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
Eddie Hung 2d86563bb2 kernel: IdString::in(const IdString &) as per @Tjoppen 2020-04-02 07:14:08 -07:00
Eddie Hung 18d85b88ae kernel: fix formatting (thanks @boqwxp) 2020-04-02 07:14:08 -07:00
Eddie Hung 7bcbf0c9d1 kernel: use C++11 fold hack to prevent recursion 2020-04-02 07:14:08 -07:00
Eddie Hung ba13a40ef4 Revert "kernel: IdString:in() to use perfect forwarding"
This reverts commit 7b2a85aedf24affc2e1202c78e70e6a317f5bf29.
2020-04-02 07:14:08 -07:00
Eddie Hung 6d4f01c3fa kernel: separate IdString::put_reference() out to help inlining 2020-04-02 07:14:08 -07:00
Eddie Hung 4a8cecf03e kernel: IdString:in() to use perfect forwarding 2020-04-02 07:14:08 -07:00
Eddie Hung 164dd0f6b2 kernel: Use constids.inc for global/constant IdStrings 2020-04-02 07:14:08 -07:00
Eddie Hung 37f42fe102
Merge pull request #1845 from YosysHQ/eddie/kernel_speedup
kernel: speedup by using more pass-by-const-ref
2020-04-02 07:13:33 -07:00
Eddie Hung c90324662c
Merge pull request #1828 from YosysHQ/eddie/celltypes_speedup
kernel: share a single CellTypes within a pass
2020-04-01 14:17:45 -07:00
Alberto Gonzalez ae05795f54
Clean up pseudo-private member usage in `kernel/yosys.cc`. 2020-04-01 02:53:56 +00:00
Eddie Hung 348e892314 kernel: pass-by-value into Design::scratchpad_set_string() too 2020-03-27 12:21:09 -07:00
Rupert Swarbrick 044ca9dde4 Add support for SystemVerilog-style `define to Verilog frontend
This patch should support things like

  `define foo(a, b = 3, c)   a+b+c

  `foo(1, ,2)

which will evaluate to 1+3+2. It also spots mistakes like

  `foo(1)

(the 3rd argument doesn't have a default value, so a call site is
required to set it).

Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.

Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.

Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
2020-03-27 16:08:26 +00:00
Eddie Hung 6ca7844cec kernel: const Wire* overload -> Wire* !!! 2020-03-26 16:21:30 -07:00
Eddie Hung f97b90e40b kernel: Cell::set{Port,Param}() to pass by value, but use std::move
Otherwise cell->setPort(ID::A, cell->getPort(ID::B)) could be invalid
2020-03-26 14:33:06 -07:00
Eddie Hung 7ad7f41bc5 kernel: share a single CellTypes within a pass 2020-03-18 12:21:40 -07:00
Eddie Hung 940640ac44 kernel: SigSpec copies to not trigger pack() 2020-03-18 11:51:00 -07:00
Eddie Hung 4555b5b819 kernel: more pass by const ref, more speedups 2020-03-18 11:21:53 -07:00
Eddie Hung 8b12e97153 kernel: speedup 2020-03-18 08:48:36 -07:00
Eddie Hung 8c45ea9f0e kernel: use const reference for SigSet too 2020-03-17 10:22:33 -07:00
Eddie Hung bc51e609cb kernel: fix DeleteWireWorker 2020-03-17 10:22:16 -07:00
Claire Wolf ed4fa19ba2 Update Copyright
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-03-16 16:28:25 +01:00
Waldir Pimenta 418c069561 License: bump year and add title 2020-03-14 16:46:07 +00:00
Miodrag Milanovic 395daf6ced exclude clang from checking 2020-03-13 17:23:27 +01:00
Miodrag Milanovic 8f221118d2 Add YS_ prefix to macros, add explanation and apply to older version as well 2020-03-13 17:19:54 +01:00
Eddie Hung 432a09af80 kernel: SigSpec use more const& + overloads to prevent implicit SigSpec 2020-03-13 08:17:39 -07:00
Miodrag Milanovic 7c54e61979 Use boost xpressive for gcc 4.8 2020-03-13 14:58:35 +01:00
Eddie Hung b567f03c26 kernel: optimise Module::remove(const pool<RTLIL::Wire*>() 2020-03-12 16:00:34 -07:00
Eddie Hung a076052fe4 kernel: SigPool to use const& + overloads to prevent implicit SigSpec 2020-03-12 16:00:34 -07:00
jiegec 7b679eecb3 Fix compilation for emcc 2020-03-11 22:09:24 +08:00
David Shah b8abf14376 Add ScriptPass::run_nocheck and use for abc9
Signed-off-by: David Shah <dave@ds0.me>
2020-03-09 14:34:22 +00:00
Claire Wolf b597f85b13
Merge pull request #1718 from boqwxp/precise_locations
Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
2020-03-03 08:38:32 -08:00
Eddie Hung 0f4c1906bb Small fixes 2020-02-27 10:29:53 -08:00