Commit Graph

1257 Commits

Author SHA1 Message Date
Marcelina Kościelnicka 56e7791760 verilog backend: Emit a `wire` for ports as well.
Fixes #3177.
2022-01-31 01:08:41 +01:00
Marcelina Kościelnicka 93508d58da Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00
Catherine fc049e84a9 cxxrtl: don't reset elided wires with \init attribute. 2021-12-25 01:06:10 +00:00
Catherine 7f2ea7d222 cxxrtl: demote wires not inlinable only in debug_eval to locals.
Fixes #3112.

Co-authored-by: Irides <irides@irides.network>
2021-12-15 09:14:33 +00:00
Marcelina Kościelnicka 0aad88a2fb Add clean_zerowidth pass, use it for Verilog output.
This should remove instances of zero-width sigspecs in the netlist,
avoiding problems in the Verilog backend with emitting them.

See #3103.
2021-12-12 19:56:50 +01:00
Catherine bdc6ba019c
Merge pull request #3105 from whitequark/cxxrtl-reset-memories-2
cxxrtl: preserve interior memory pointers across reset
2021-12-12 01:23:03 +00:00
Marcelina Kościelnicka d019b4e681 rtlil: Dump empty connections when whole module is selected.
Without this, empty connections will be always skipped by `dump`, since
they contain no selected wires.  This makes debugging rather confusing.
2021-12-12 01:22:06 +01:00
Catherine 55c9fb3b18 cxxrtl: preserve interior memory pointers across reset.
Before this commit, values, wires, and memories with an initializer
were value-initialized in emitted C++ code. After this commit, all
values, wires, and memories are default-initialized, and the default
constructor of generated modules calls the reset() method, which
assigns the members that have an initializer.
2021-12-11 16:40:06 +00:00
whitequark 7c9e498662 cxxrtl: use unique_ptr<value<>[]> to store memory contents.
This makes the depth properly immutable.
2021-12-11 14:52:37 +00:00
whitequark 86f2804dc3 write_verilog: dump zero width sigspecs correctly.
Before this commit, zero width sigspecs were dumped as "" (empty
string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty
string is equivalent to "\0", and is 8 bits wide, so that's wrong.

After this commit, a replication operation with a count of zero is
used instead, which is explicitly permitted per 1364-2005 5.1.14,
and is defined to have size zero. (Its operand has to have a non-zero
size for it to be legal, though.)

PR #1203 has addressed this issue before, but in an incomplete way.
2021-12-11 12:01:52 +00:00
Lofty 77327b2544 sta: very crude static timing analysis pass
Co-authored-by: Eddie Hung <eddie@fpgeh.com>
2021-11-25 17:20:27 +01:00
Miodrag Milanovic c081c683a4 Give initial wire unique ID, fixes #2914 2021-11-17 12:19:06 +01:00
Miodrag Milanovic ff8e999a71 Split module ports, 20 per line 2021-10-09 13:40:55 +02:00
Marcelina Kościelnicka e7d89e653c Hook up $aldff support in various passes. 2021-10-02 21:01:21 +02:00
Marcelina Kościelnicka 63b9df8693 kernel/ff: Refactor FfData to enable FFs with async load.
- *_en is split into *_ce (clock enable) and *_aload (async load aka
  latch gate enable), so both can be present at once
- has_d is removed
- has_gclk is added (to have a clear marker for $ff)
- d_is_const and val_d leftovers are removed
- async2sync, clk2fflogic, opt_dff are updated to operate correctly on
  FFs with async load
2021-10-02 20:19:48 +02:00
Claire Xenia Wolf 89df26e4bc Add optimization to rtlil back-end for all-x parameter values
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-09-27 16:02:20 +02:00
the6p4c c25122e339 Fix protobuf backend build dependencies
backends/protobuf/protobuf.cc depends on the source and header files
generated by protoc, but this dependency wasn't explicitly declared. Add
a rule to the Makefile to fix intermittent build failures when the
protobuf header/source file isn't built before protobuf.cc.
2021-09-17 13:36:39 +10:00
Marcelina Kościelnicka 33749f1e3a yosys-smtbmc: Fix reused loop variable.
Fixes #2999.
2021-09-10 13:34:58 +02:00
Marcelina Kościelnicka e6f3d1c225 kernel/mem: Introduce transparency masks. 2021-08-11 00:04:16 +02:00
Marcelina Kościelnicka ec2a468bd3 backend/verilog: Add alternate mode for transparent read port output.
This mode will be used whenever read port cannot be handled in the
"extract address register" way, ie. whenever it has enable, reset,
init functionality or (in the future) mixed transparency mask.
2021-08-01 19:11:29 +02:00
Marcelina Kościelnicka e9effd58d2 backends/verilog: Support meminit with mask. 2021-07-28 23:18:38 +02:00
whitequark a04844bdf8
Merge pull request #2885 from whitequark/cxxrtl-fix-2883
cxxrtl: treat wires with multiple defs as not inlinable
2021-07-20 13:12:11 +00:00
whitequark 1a6ddf7892 cxxrtl: treat wires with multiple defs as not inlinable.
Fixes #2883.
2021-07-20 10:30:39 +00:00
whitequark 225af830c1 cxxrtl: treat assignable internal wires used only for debug as locals.
This issue was introduced in commit 4aa65f40 while fixing #2739.

Fixes #2882.
2021-07-20 10:10:42 +00:00
whitequark fc84f23001 cxxrtl: escape colon in variable names in VCD writer.
The following VCD file crashes GTKWave's VCD loader:

    $var wire 1 ! x:1 $end
    $enddefinitions $end

In practice, a colon can be a part of a variable name that is
translated from a Verilog function, something like:

    update$func$.../hdl/hazard3_csr.v:350$2534.$result
2021-07-19 16:22:55 +00:00
whitequark 948fc10d7b cxxrtl: add debug_item::{get,set}.
Fixes #2877.
2021-07-18 06:20:45 +00:00
whitequark 4aa65f406f cxxrtl: treat internal wires used only for debug as constants.
Fixes #2739 (again).
2021-07-17 14:23:57 +00:00
whitequark 2db4137514
Merge pull request #2874 from whitequark/cxxrtl-fix-2589
cxxrtl: run hierarchy pass regardless of (*top*) attribute presence
2021-07-16 11:12:19 +00:00
whitequark efc43270fa
Merge pull request #2873 from whitequark/cxxrtl-fix-2500
cxxrtl: emit debug items for unused public wires
2021-07-16 11:01:10 +00:00
whitequark 5b003d6e5c cxxrtl: run hierarchy pass regardless of (*top*) attribute presence.
The hierarchy pass does a lot more than just finding the top module,
mainly resolving implicit (positional, wildcard) module connections.

Fixes #2589.
2021-07-16 10:27:47 +00:00
whitequark 09218896d6 cxxrtl: emit debug items for unused public wires.
This greatly improves debug information coverage.

Fixes #2500.
2021-07-16 10:14:40 +00:00
whitequark b28ca7f5ac cxxrtl: don't expect user cell inputs to be wires.
Ports can be connected to constants, too. (Usually resets.)

Fixes #2521.
2021-07-16 09:51:52 +00:00
whitequark 44a3d924ce cxxrtl: don't mark buffered internal wires as UNUSED for debug.
Public wires may alias buffered internal wires, so keep BUFFERED
wires in debug information even if they are private. Debug items are
only created for public wires, so this does not otherwise affect how
debug information is emitted.

Fixes #2540.
Fixes #2841.
2021-07-16 07:54:49 +00:00
whitequark 54b6cb645f cxxrtl: mark dead local wires as unused even with inlining disabled.
Fixes #2739.
2021-07-15 22:27:27 +00:00
Marcelina Kościelnicka 8bf9cb407d kernel/mem: Add a coalesce_inits helper.
While this helper is already useful to squash sequential initializations
into one in cxxrtl, its main purpose is to squash overlapping masked memory
initializations (when they land) and avoid having to deal with them in
cxxrtl runtime.
2021-07-13 15:59:11 +02:00
GCHQDeveloper560 4379375d89 Add support for the Bitwuzla solver 2021-07-12 22:07:58 +02:00
Marcelina Kościelnicka 37506d737c cxxrtl: Support memory writes in processes. 2021-07-12 18:27:48 +02:00
Marcelina Kościelnicka af7fa62251 cxxrtl: Add support for memory read port reset. 2021-07-12 18:27:48 +02:00
Marcelina Kościelnicka be5cf29699 cxxrtl: Add support for mem read port initial data. 2021-07-12 18:27:48 +02:00
Marcelina Kościelnicka d5c9595668 cxxrtl: Convert to Mem helpers.
This *only* does conversion, but doesn't add any new functionality —
support for memory read port init/reset is still upcoming.
2021-07-12 18:27:48 +02:00
Claire Xenia Wolf 2d95a7da9c Intersynth URL
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-06-09 12:42:52 +02:00
Claire Xenia Wolf 72787f52fc Fixing old e-mail addresses and deadnames
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
2021-06-08 00:39:36 +02:00
Marcelina Kościelnicka cbf6b719fe Make a few passes auto-call Mem::narrow instead of rejecting wide ports.
This essentially adds wide port support for free in passes that don't
have a usefully better way of handling wide ports than just breaking
them up to narrow ports, avoiding "please run memory_narrow" annoyance.
2021-05-28 00:40:56 +02:00
Marcelina Kościelnicka 055ba748bc backends/verilog: Add support for memory read port reset and init value. 2021-05-27 23:47:42 +02:00
Marcelina Kościelnicka aabe1c382e backends/verilog: Add wide port support. 2021-05-27 16:15:46 +02:00
Marcelina Kościelnicka 64ba3c3842 backends/verilog: Try to preserve mem write port priorities. 2021-05-26 00:19:31 +02:00
Marcelina Kościelnicka 69bf5c81c7 Reject wide ports in some passes that will never support them. 2021-05-25 02:07:25 +02:00
Marcelina Kościelnicka b6721aa9d8 backend/firrtl: Convert to use Mem helpers. 2021-05-24 14:00:33 +02:00
Marcelina Kościelnicka 33513d923a btor: Use is_mem_cell in one more place. 2021-05-23 20:34:52 +02:00
Marcelina Kościelnicka c4cc888b2c kernel/rtlil: Extract some helpers for checking memory cell types.
There will soon be more (versioned) memory cells, so handle passes that
only care if a cell is memory-related by a simple helper call instead of
a hardcoded list.
2021-05-22 21:43:00 +02:00