1306 Commits

Author	SHA1	Message	Date
Clifford Wolf	80aefb3eaa	Added intersynth backend	2013-03-23 10:58:14 +01:00
Clifford Wolf	87c7717566	Avoid verilog-2k in verilog backend	2013-03-21 09:51:25 +01:00
Clifford Wolf	11789db206	More support code for $sr cells	2013-03-14 11:15:00 +01:00
Clifford Wolf	441e5fbfca	Fixed a gcc compiler warning [-Wparentheses]	2013-03-03 22:45:06 +01:00
Clifford Wolf	7fccad92f7	Added more help messages	2013-03-01 00:36:19 +01:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00