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14541 Commits

Author SHA1 Message Date
Roland Coeurjoly 762f8dd822 Add readme explaining how to create test files 2024-08-21 11:02:31 +01:00
Roland Coeurjoly 73ed514623 Check that there are not other solutions other than the first given 2024-08-21 11:02:31 +01:00
Roland Coeurjoly cb5f08364c ´SMT success only if simulation is equivalent 2024-08-21 11:02:31 +01:00
Emily Schmidt 9700df50d6 add generic writer class with formatting function to FunctionalTools 2024-08-21 11:02:31 +01:00
Roland Coeurjoly 32cdf25838 Use FunctionalTools::Scope instead of replaceCharacters 2024-08-21 11:02:31 +01:00
Roland Coeurjoly ee6bd59436 Removed unnecesary nested_lets variable, use writer.print instead 2024-08-21 11:02:31 +01:00
Roland Coeurjoly e235fc704d Create std::mt19937 only once 2024-08-21 11:02:31 +01:00
Emily Schmidt 21bb1cf1bc rewrite functional c++ simulation library 2024-08-21 11:02:31 +01:00
Emily Schmidt eb2bb8c45b tidy up generic functional backend, add generic scope class, tidy up c++ functional backend 2024-08-21 11:02:31 +01:00
Roland Coeurjoly 39bf4f04f7 Create VCD file from SMT file 2024-08-21 11:02:31 +01:00
Roland Coeurjoly 4109fcedcf clang-format smtlib.cc 2024-08-21 11:02:31 +01:00
Roland Coeurjoly 94ddbc9577 Fix reduce_or 2024-08-21 11:02:31 +01:00
Roland Coeurjoly b98210d8ac Valid SMT is emitted, improved test script 2024-08-21 11:02:31 +01:00
Roland Coeurjoly 71aaa1c80d Consolidate tests scripts into one 2024-08-21 11:02:31 +01:00
Roland Coeurjoly 547c5466ec Ignore smt2 files, generated by the execution of the tests 2024-08-21 11:02:31 +01:00
Roland Coeurjoly c6e112686c Remove unused includes 2024-08-21 11:02:31 +01:00
Roland Coeurjoly 54225b5c42 Add test for SMT backend. Tests if SMT is valid and compares simulation with yosys sim 2024-08-21 11:02:31 +01:00
Roland Coeurjoly 4e370f4426 Initial functional SMT backend using functional IR 2024-08-21 11:02:31 +01:00
Emily Schmidt 6f9e21219b add new generic compute graph and rewrite c++ functional backend to use it 2024-08-21 11:02:29 +01:00
Emily Schmidt 248d5f72d4 add support for std::variant to hashlib 2024-08-21 11:01:09 +01:00
Emily Schmidt dbf2bc3b1d need unsigned comparison when checking shift widths for overflow in functional backend 2024-08-21 11:01:09 +01:00
Roland Coeurjoly 3552a8a2b2 sim.h cannot use log_assert because does not include yosys headers 2024-08-21 11:01:09 +01:00
Emily Schmidt 7b29d177ac add support for memories to c++ and smtlib functional backends 2024-08-21 11:01:09 +01:00
Roland Coeurjoly 76371d177f Change assert to log_assert 2024-08-21 11:01:09 +01:00
Roland Coeurjoly 720429b1fd Add test_cell tests for C++ functional backend 2024-08-21 11:01:09 +01:00
Emily Schmidt 7611dda2eb add initial version of functional smtlib backend 2024-08-21 11:01:09 +01:00
Emily Schmidt 63dea89fac add initial version of functional C++ backend 2024-08-21 11:01:09 +01:00
Emily Schmidt dd5ec84a26 fix bugs in drivertools 2024-08-21 11:01:09 +01:00
Jannis Harder d90268f610 fixup! drivertools: Utility code for indexing and traversing signal drivers 2024-08-21 11:01:09 +01:00
Jannis Harder d4e3daa9d0 ComputeGraph datatype for the upcoming functional backend 2024-08-21 11:01:09 +01:00
Jannis Harder f29422f745 topo_scc: Add sources_first option 2024-08-21 11:01:09 +01:00
Jannis Harder 68c3a47945 WIP temporary drivertools example 2024-08-21 11:01:08 +01:00
Jannis Harder 56572978f5 drivertools: Utility code for indexing and traversing signal drivers 
It adds `DriveBit`, `DriveChunk` and `DriveSpec` types which are similar
to `SigBit`, `SigChunk` and `SigSpec` but can also directly represent
cell ports, undriven bits and multiple drivers. For indexing an RTLIL
module and for querying signal drivers it comes with a `DriverMap` type
which is somewhat similar to a `SigMap` but is guaranteed to produce
signal drivers as returned representatives.

A `DriverMap` can also optionally preserve connections via intermediate
wires (e.g. querying the driver of a cell input port will return a
connected intermediate wire, querying the driver of that wire will
return the cell output port that's driving the wire).
 2024-08-21 11:00:21 +01:00
Jannis Harder f24e2536c6 kernel/rtlil: Add `SigBit operator[](int offset)` to `SigChunk` 
This is already supported by `SigSpec` and since both `SigChunk` and
`SigSpec` implement `extract` which is the multi-bit variant of this,
there is no good reason for `SigChunk` to not support
`SigBit operator[](int offset)`.
 2024-08-21 10:58:39 +01:00
Jannis Harder c73c8a39cf kernel/log: Add log_str helper for custom log_* functions/overloads 
When implementing custom log_... functions or custom overloads for the
core log functions like log_signal it is necessary to return `char *`
that are valid long enough.

The log_... functions implemented in log.cc use either `log_id_cache` or
`string_buf` which both are cleared on log_pop.

This commit adds a public `log_str` function which stores its argument
in the `log_id_cache` and returns the stored copy, such that custom
log functions outside of log.cc can also create strings that remain
valid until the next `log_pop`.
 2024-08-21 10:58:39 +01:00
Jannis Harder 0922142567 Add generic topological sort and SCC detection 
This adds a generic non-recursive implementation of Tarjan's linear time
SCC algorithm that produces components in topological order. It can be
instantiated to work directly on any graph representation for which the
enumerate_nodes and enumerate_successors interface can be implemented.
 2024-08-21 10:58:39 +01:00
github-actions[bot] 4cddc19994 Bump version 2024-08-20 00:18:24 +00:00
Miodrag Milanović e4c8bb0ac5
Merge pull request #4552 from YosysHQ/krys/rtd_on_main 
docs: Only trigger RTDs on main
 2024-08-19 20:11:55 +02:00
Krystine Sherwin 7d779c64a3
docs: Only trigger RTDs on main 2024-08-20 04:26:58 +12:00
Emil J d901b28d2c
Merge pull request #4546 from NachtSpyder04/main 
[Docs]:Add new cell type help messages
 2024-08-19 15:50:41 +02:00
Emil J 9de534892e
Merge pull request #4515 from RCoeurjoly/nix_on_macos 
Run nix build also on macos. Build with more logs
 2024-08-19 15:49:23 +02:00
Emil J e0d3bbf3c3
Merge pull request #4452 from phsauter/shiftadd-underflow-fix 
peepopt: avoid shift-amount underflow
 2024-08-19 15:45:46 +02:00
Emil J 0dfa4962d1
Merge pull request #4547 from leviathanch/fix_apicula1 
Add DQS and related primitives to Gowin tech files
 2024-08-19 15:44:48 +02:00
Emil J. Tywoniak 4847caac49 driver: print maximum memory usage on macOS as well 2024-08-19 12:50:12 +02:00
Krystine Sherwin 6df0c3d9ec
docs: Fix synth_flow generation 2024-08-19 21:25:51 +12:00
Krystine Sherwin 8773cf7721
test-verific: Use fast runner 2024-08-19 21:24:48 +12:00
N. Engelhardt 7f08a298a4
Merge pull request #4542 from YosysHQ/krys/rtd 
Local readthedocs
 2024-08-19 10:04:38 +02:00
David Lanzendörfer d1b767ea8b Adding missing to Gowin tech files 
Without OSER4_MEM, IDES4_MEM and DQS the synthesis of my Rocket Chip
design for my Sipeed Tang FPGA fails.
 2024-08-18 19:38:31 +01:00
NachtSpyder04 aa60255e0e update help messages that went beyond line length limit 2024-08-18 20:27:35 +05:30
Saish Karole 34aabd56cc
Apply suggestions from code review 
Co-authored-by: Martin Povišer <povik@cutebit.org>
 2024-08-18 20:12:53 +05:30