Commit Graph

1810 Commits

Author SHA1 Message Date
Miodrag Milanović e8ce9442a6
Merge pull request #3452 from ALGCDG/master
Add BLIF names command input plane size check
2022-10-10 16:29:27 +02:00
Claire Xenia Wolf 090228a6a1 Fix handling of verific -L options, add implicit "-L work"
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-10-10 00:47:42 +02:00
Miodrag Milanovic 1a6f10e8ba Add support for EDIF file reading using Verific 2022-10-04 09:18:44 +02:00
Archie d29606532a Changing error reason string to be based on lut input plane limit constant. 2022-10-02 22:05:51 +02:00
Miodrag Milanovic 43267dec99 support file content redirection for verific frontened 2022-09-28 15:56:46 +02:00
Miodrag Milanovic b45517f7b7 Add comment for future self 2022-09-28 14:45:39 +02:00
Miodrag Milanovic f54ac8a6d6 Handle attributes imported from verific 2022-09-28 08:51:26 +02:00
Miodrag Milanovic 8fb498744f Import memory attributes 2022-09-21 15:48:40 +02:00
Miodrag Milanovic 3f94f9313a verific: better fix for read callback 2022-09-07 09:48:19 +02:00
Miodrag Milanovic 06a9c7499a verific: fix crash when using prep right after read 2022-09-07 09:40:14 +02:00
KrystalDelusion 9465b2af95 Fitting help messages to 80 character width
Uses the regex below to search (using vscode):
	^\t\tlog\("(.{10,}(?<!\\n)|.{81,}\\n)"\);

Finds any log messages double indented (which help messages are)
and checks if *either* there are is no newline character at the end,
*or* the number of characters before the newline is more than 80.
2022-08-24 10:40:57 +12:00
Archie 15a0697c70 Adding check for BLIF names command input plane size. 2022-08-21 23:18:20 -05:00
Miodrag Milanovic b76c72056b set default_nettype to wire for resetall 2022-08-10 13:28:19 +02:00
Miodrag Milanovic 545a3417c8 resetall does not affect text defines, but undefineall does 2022-08-10 11:38:50 +02:00
Miodrag Milanovic 6c65ca4e50 Encode filename unprintable chars 2022-08-08 16:13:33 +02:00
Miodrag Milanovic 2b1aeb44d9 verific - make filepath handling compatible with verilog frontend 2022-08-08 11:57:28 +02:00
Miodrag Milanović 15393442d6
Merge pull request #3089 from YosysHQ/gatecat/liberty_wb
Add read_liberty -wb
2022-08-01 17:08:04 +02:00
Miodrag Milanovic 52a4a89265 Setting wire upto in verific import 2022-07-29 17:10:31 +02:00
Miodrag Milanović d19f9d0b66
Update README 2022-07-28 12:32:19 +02:00
Miodrag Milanovic 59b96bb1f8 Upadte documentation and changelog 2022-07-04 11:09:06 +02:00
Miodrag Milanovic b80976b543 Update to new verific extensions inteface 2022-06-30 11:19:01 +02:00
Archie 7eeb656e2a Add check for BLIF with no model name 2022-06-22 00:34:49 +01:00
Miodrag Milanovic 1fdbb42fdd Revert "use new verific extensions library"
This reverts commit 607e957657.
2022-06-21 18:07:47 +02:00
Miodrag Milanovic 607e957657 use new verific extensions library 2022-06-17 16:04:22 +02:00
Miodrag Milanovic ddc8044655 removed deprecated features code 2022-06-13 10:50:24 +02:00
Miodrag Milanovic 6e8e4b4550 verific: Added "-vlog-libext" option to specify search extension for libraries 2022-06-09 08:57:48 +02:00
Miodrag Milanovic e35a166353 verific: proper file location for readmem commands 2022-06-04 08:39:50 +02:00
Zachary Snow a650d9079f verilog: fix width/sign detection for functions 2022-05-30 16:45:39 -04:00
Jannis Harder 4bfaaea0d5 verilog: fix size and signedness of array querying functions
genrtlil.cc and simplify.cc had inconsistent and slightly broken
handling of signedness for array querying functions. These functions are
defined to return a signed result. Simplify always produced an unsigned
and genrtlil always a signed 32-bit result ignoring the context.

Includes tests for the the relvant edge cases for context dependent
conversions.
2022-05-30 09:11:31 -04:00
Jannis Harder b75fa62e9b verilog: fix $past's signedness 2022-05-25 16:32:08 -04:00
Jannis Harder cffec1f95f verilog: fix signedness when removing unreachable cases 2022-05-24 23:03:31 -04:00
Miodrag Milanovic fdb393b6ce fix text to fit 80 columns 2022-05-23 19:57:21 +02:00
Miodrag Milanovic 4a5790d404 Update verific command file documentation 2022-05-23 19:35:14 +02:00
Miodrag Milanovic a6ec5754c6 Use analysis mode if set in file 2022-05-23 19:13:45 +02:00
Jannis Harder fada77b8cf verific: Use new value change logic also for $stable of wide signals.
I missed this in the previous PR.
2022-05-11 13:05:27 +02:00
Jannis Harder 587e09d551
Merge pull request #3305 from jix/sva_value_change_logic
verific: Improve logic generated for SVA value change expressions
2022-05-09 16:40:34 +02:00
Jannis Harder a855d62b42 verific: Improve logic generated for SVA value change expressions
The previously generated logic assumed an unconstrained past value in
the initial state and did not handle 'x values. While the current formal
verification flow uses 2-valued logic, SVA value change expressions
require a past value of 'x during the initial state to behave in the
expected way (i.e. to consider both an initial 0 and an initial 1 as
$changed and an initial 1 as $rose and an initial 0 as $fell).

This patch now generates logic that at the same time

	a) provides the expected behavior in a 2-valued logic setting, not
	   depending on any dont-care optimizations, and

	b) properly handles 'x values in yosys simulation
2022-05-09 15:04:01 +02:00
Jannis Harder 96f64f4788 verific: Fix conditions of SVAs with explicit clocks within procedures
For SVAs that have an explicit clock and are contained in a procedure
which conditionally executes the assertion, verific expresses this using
a mux with one input connected to constant 1 and the other output
connected to an SVA_AT. The existing code only handled the case where
the first input is connected to 1. This patch also handles the other
case.
2022-05-03 14:13:08 +02:00
Miodrag Milanovic 422db937d4 Ignore merging past ffs that we are not properly merging 2022-04-29 14:35:02 +02:00
Miodrag Milanovic 1cc281ca6f verific: allow memories to be inferred in loops (vhdl) 2022-04-18 09:10:28 +02:00
N. Engelhardt 57bc29c64a verific: allow memories to be inferred in loops 2022-04-15 15:10:48 +02:00
Zachary Snow bf15dbd0f7 sv: fix always_comb auto nosync for nested and function blocks 2022-04-05 14:43:48 -06:00
Miodrag Milanovic 1a1f529099 Preserve internal wires for external nets 2022-04-01 12:07:15 +02:00
Miodrag Milanovic bbf65702a1 Fix valgrind tests when using verific 2022-03-30 17:25:53 +02:00
Miodrag Milanovic 703769e494 Properly mark modules imported 2022-03-26 09:43:51 +01:00
Miodrag Milanovic 245ecb0529 Import verific netlist in consistent order 2022-03-25 13:44:16 +01:00
Miodrag Milanović 13655ddccf
Merge pull request #3206 from YosysHQ/micko/quote_remove
Remove quotes if any from attribute
2022-03-04 16:39:01 +01:00
N. Engelhardt 8fd1b06249 fix handling of escaped chars in json backend and frontend 2022-02-18 17:13:09 +01:00
Miodrag Milanovic 29293a57bb Remove quotes if any from attribute 2022-02-16 19:10:13 +01:00
Zachary Snow 15a4e900b2 verilog: support for time scale delay values 2022-02-14 15:58:31 +01:00
Kamil Rakoczy 68c67c40ec
Fix access to whole sub-structs (#3086)
* Add support for accessing whole struct
* Update tests

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2022-02-14 14:34:20 +01:00
Zachary Snow 15eb66b99d verilog: fix dynamic dynamic range asgn elab 2022-02-11 22:54:55 +01:00
Zachary Snow 90bb47d181 verilog: fix const func eval with upto variables 2022-02-11 21:01:51 +01:00
Miodrag Milanović fc7d78f071
Merge pull request #3164 from zachjs/fix-ast-warn
fix dumpAst() compilation warning
2022-02-11 16:43:35 +01:00
Miodrag Milanovic 2cef48bf2c Add ability to override verilog mode for verific -f command 2022-02-09 09:19:25 +01:00
Miodrag Milanovic 0b633b6c2e Use bmux for NTO1MUX 2022-02-02 16:16:08 +01:00
Zachary Snow 342927732e fix dumpAst() compilation warning 2022-01-18 00:17:08 -07:00
Zachary Snow aa35f24290 sv: auto add nosync to certain always_comb local vars
If a local variable is always assigned before it is used, then adding
nosync prevents latches from being needlessly generated.
2022-01-07 22:53:22 -07:00
Zachary Snow 828e85068f sv: fix size cast internal expression extension 2022-01-07 21:21:02 -07:00
Zachary Snow 8c509a5659 sv: fix size cast clipping expression width 2022-01-03 08:17:35 -07:00
Zachary Snow 7608985d2c fix width detection of array querying function in case and case item expressions
I also removed the unnecessary shadowing of `width_hint` and `sign_hint`
in the corresponding case in `simplify()`.
2021-12-17 21:22:08 -07:00
Thomas Sailer 4cd2f03e36 preprocessor: do not destroy double slash escaped identifiers
The preprocessor currently destroys double slash containing escaped
identifiers (for example \a//b ). This is due to next_token trying to
convert single line comments (//) into /* */ comments. This then leads
to an unintuitive error message like this:
ERROR: syntax error, unexpected '*'

This patch fixes the error by recognizing escaped identifiers and
returning them as single token. It also adds a testcase.
2021-12-15 18:06:02 -07:00
Claire Xenia Wolf 313340aed5 Add YOSYS to the implicitly defined verilog macros in verific
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-12-13 18:20:08 +01:00
Miodrag Milanović 2412497c26
Merge pull request #3102 from YosysHQ/claire/enumxz
Fix verific import of enum values with x and/or z
2021-12-10 19:36:37 +01:00
Claire Xenia Wolf 2da214d721 Fix verific import of enum values with x and/or z
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-12-10 14:52:27 +01:00
Claire Xen 19773d093f
Update verific.cc
Ad-hoc fixes/improvements
2021-12-10 14:27:18 +01:00
Miodrag Milanovic b06f547993 If direction NONE use that from first bit 2021-12-08 11:50:10 +01:00
Miodrag Milanovic 3ebfa3fb84 Make sure cell names are unique for wide operators 2021-12-03 09:49:05 +01:00
gatecat b506f398dd Add read_liberty -wb
Signed-off-by: gatecat <gatecat@ds0.me>
2021-11-25 19:13:08 +00:00
Kamil Rakoczy fdb19a5b3a
Support parameters using struct as a wiretype (#3050)
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2021-11-16 10:59:54 +01:00
Miodrag Milanovic 15a35f5584 No need to alocate more memory than used 2021-11-10 10:50:44 +01:00
Kamil Rakoczy f4f5acf396 genrtlil: Fix displaying debug info in packages
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2021-11-10 01:31:39 +01:00
Claire Xenia Wolf 2ea757da51 Add "verific -cfg" command
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-11-01 10:41:51 +01:00
Claire Xenia Wolf 83118bfb9e Fix verific gclk handling for async-load FFs
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-10-31 17:12:29 +01:00
Miodrag Milanovic f7cc388bb5 Enable async load dff emit by default in Verific 2021-10-27 15:56:56 +02:00
Miodrag Milanovic 32673edfea Revert "Compile option for enabling async load verific support"
This reverts commit b8624ad2ae.
2021-10-27 15:55:43 +02:00
Zachary Snow e833c6a418 verilog: use derived module info to elaborate cell connections
- Attempt to lookup a derived module if it potentially contains a port
  connection with elaboration ambiguities
- Mark the cell if module has not yet been derived
- This can be extended to implement automatic hierarchical port
  connections in a future change
2021-10-25 18:25:50 -07:00
Rupert Swarbrick bd16d01c0e Split out logic for reprocessing an AstModule
This will enable other features to use same core logic for replacing an
existing AstModule with a newly elaborated version.
2021-10-25 18:25:50 -07:00
Miodrag Milanovic b8624ad2ae Compile option for enabling async load verific support 2021-10-25 09:04:43 +02:00
Claire Xenia Wolf 90b440f870 Fix verific.cc PRIM_DLATCH handling
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-10-21 12:13:35 +02:00
Claire Xenia Wolf 16a177560f Initial Verific impoter support for {PRIM,WIDE_OPER}_DLATCH{,RS}
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-10-21 05:42:47 +02:00
Miodrag Milanovic 17269ae59b Option to disable verific VHDL support 2021-10-20 10:02:58 +02:00
Miodrag Milanovic 1aa6896966 Support PRIM_BUFIF1 primitive 2021-10-14 13:04:32 +02:00
Claire Xen 2d3c79458d
Merge pull request #3039 from YosysHQ/claire/verific_aldff
Add support for $aldff flip-flops to verific importer
2021-10-11 10:01:56 +02:00
Claire Xenia Wolf c8074769b0 Add Verific adffe/dffsre/aldffe FIXMEs
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-10-11 10:00:20 +02:00
Miodrag Milanovic 93fbc9fba4 Import module attributes from Verific 2021-10-10 10:01:45 +02:00
Claire Xenia Wolf 34f1df8435 Fixes and add comments for open FIXME items
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-10-08 17:24:45 +02:00
Claire Xenia Wolf 1602a03864 Add support for $aldff flip-flops to verific importer
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-10-08 16:21:25 +02:00
Miodrag Milanovic abc5700628 verific set db_infer_set_reset_registers 2021-10-04 16:48:33 +02:00
Zachary Snow fbd70f28f0 Specify minimum bison version 3.0+
Yosys works with bison 3.0 (or newer), but not bison 2.7 (the previous
release). Ideally, we would require "3" rather than "3.0" to give a
better error message, but bison 2.3, which still ships with macOS, does
not support major-only version requirements. With this change, building
with an outdated bison yields: `frontends/rtlil/rtlil_parser.y:25.10-14:
require bison 3.0, but have 2.3`.
2021-10-01 21:18:33 -06:00
Claire Xen 0146d83ed8
Merge pull request #3014 from YosysHQ/claire/fix-vgtest
Fix "make vgtest"
2021-09-24 17:50:34 +02:00
Zachary Snow 9658d2e337 Fix TOK_ID memory leak in for_initialization 2021-09-23 13:33:55 -04:00
Zachary Snow d6fe6d4fb6 sv: support wand and wor of data types
This enables the usage of declarations of wand or wor with a base type
of logic, integer, or a typename. Note that declarations of nets with
2-state base types is still permitted, in violation of the spec.
2021-09-21 14:52:28 -04:00
Zachary Snow 6b7267b849 verilog: fix multiple AST_PREFIX scope resolution issues
- Root AST_PREFIX nodes are now subject to genblk expansion to allow
  them to refer to a locally-visible generate block
- Part selects on AST_PREFIX member leafs can now refer to generate
  block items (previously would not resolve and raise an error)
- Add source location information to AST_PREFIX nodes
2021-09-21 12:10:59 -04:00
Marcelina Kościelnicka 551ef85cd7 verilog: Squash flex-triggered warning. 2021-09-13 18:58:17 +02:00
Miodrag Milanovic c3d4bb4cc9 update required verific version 2021-09-02 14:59:16 +02:00
Zachary Snow b2e9717419 sv: support declaration in generate for initialization
This is accomplished by generating a unique name for the genvar,
renaming references to the genvar only in the loop's initialization,
guard, and incrementation, and finally adding a localparam inside the
loop body with the original name so that the genvar can be shadowed as
expected.
2021-08-31 12:34:55 -06:00
Zachary Snow f0a52e3dd2 sv: support declaration in procedural for initialization
In line with other tools, this adds an extra wrapping block around such
for loops to appropriately scope the variable.
2021-08-30 15:19:21 -06:00
Miodrag Milanovic b59c427348 Make Verific extensions optional 2021-08-20 10:19:04 +02:00
Rupert Swarbrick ee2b5b7ed1 Generate an RTLIL representation of bind constructs
This code now takes the AST nodes of type AST_BIND and generates a
representation in the RTLIL for them.

This is a little tricky, because a binding of the form:

    bind baz foo_t foo_i (.arg (1 + bar));

means "make an instance of foo_t called foo_i, instantiate it inside
baz and connect the port arg to the result of the expression 1+bar".
Of course, 1+bar needs a cell for the addition. Where should that cell
live?

With this patch, the Binding structure that represents the construct
is itself an AST::AstModule module. This lets us put the adder cell
inside it. We'll pull the contents out and plonk them into 'baz' when
we actually do the binding operation as part of the hierarchy pass.

Of course, we don't want RTLIL::Binding to contain an
AST::AstModule (since kernel code shouldn't depend on a frontend), so
we define RTLIL::Binding as an abstract base class and put the
AST-specific code into an AST::Binding subclass. This is analogous to
the AST::AstModule class.
2021-08-13 17:11:35 -06:00
Brett Witherspoon 979053855c sv: improve support for wire and var with user-defined types
- User-defined types must be data types. Using a net type (e.g. wire) is
  a syntax error.
- User-defined types without a net type are always variables (i.e.
  logic).
- Nets and variables can now be explicitly declared using user-defined
  types:

    typedef logic [1:0] W;
    wire W w;

    typedef logic [1:0] V;
    var V v;

Fixes #2846
2021-08-12 22:41:41 -06:00
Michael Singer 681a1c07e5 Allow optional comma after last entry in enum 2021-08-09 22:25:57 -06:00
Marcelina Kościelnicka 52cbf1bea5 verilog: Support tri/triand/trior wire types.
These are, by the standard, just aliases for wire/wand/wor.

Fixes #2918.
2021-08-06 21:35:43 +02:00
Miodrag Milanovic be04d8834e Require latest verific 2021-08-02 10:29:58 +02:00
Zachary Snow 4fec3a85cd genrtlil: add width detection for AST_PREFIX nodes 2021-07-29 20:55:31 -04:00
Zachary Snow 3156226233 verilog: save and restore overwritten macro arguments 2021-07-28 21:52:16 -04:00
Marcelina Kościelnicka 8bdc019730 verilog: Emit $meminit_v2 cell.
Fixes #2447.
2021-07-28 23:18:38 +02:00
Miodrag Milanovic 987fca5297 Update to latest verific 2021-07-21 09:46:53 +02:00
Rupert Swarbrick 414154dd27 Add support for parsing the SystemVerilog 'bind' construct
This doesn't do anything useful yet: the patch just adds support for
the syntax to the lexer and parser and adds some tests to check the
syntax parses properly. This generates AST nodes, but doesn't yet
generate RTLIL.

Since our existing hierarchical_identifier parser doesn't allow bit
selects (so you can't do something like foo[1].bar[2].baz), I've also
not added support for a trailing bit select (the "constant_bit_select"
non-terminal in "bind_target_instance" in the spec). If we turn out to
need this in future, we'll want to augment hierarchical_identifier and
its other users too.

Note that you can't easily use the BNF from the spec:

    bind_directive ::=
        "bind" bind_target_scope [ : bind_target_instance_list]
               bind_instantiation ;
      | "bind" bind_target_instance bind_instantiation ;

even if you fix the lookahead problem, because code like this matches
both branches in the BNF:

    bind a b b_i (.*);

The problem is that 'a' could either be a module name or a degenerate
hierarchical reference. This seems to be a genuine syntactic
ambiguity, which the spec resolves (p739) by saying that we have to
wait until resolution time (the hierarchy pass) and take whatever is
defined, treating 'a' as an instance name if it names both an instance
and a module.

To keep the parser simple, it currently accepts this invalid syntax:

    bind a.b : c d e (.*);

This is invalid because we're in the first branch of the BNF above, so
the "a.b" term should match bind_target_scope: a module or interface
identifier, not an arbitrary hierarchical identifier.

This will fail in the hierarchy pass (when it's implemented in a
future patch).
2021-07-16 09:31:39 -04:00
Zachary Snow a9c8ca21d5 sv: fix two struct access bugs
- preserve signedness of struct members
- fix initial width detection of struct members (e.g., in case expressions)
2021-07-15 11:57:20 -04:00
Marcelina Kościelnicka 009940f56c rtlil: Make Process handling more uniform with Cell and Wire.
- add a backlink to module from Process
- make constructor and destructor protected, expose Module functions
  to add and remove processes
2021-07-12 00:47:34 +02:00
Miodrag Milanovic 7a5ac90985 Update to latest Verific with extensions for initial assertions 2021-07-09 09:02:27 +02:00
Zachary Snow 4446cfa524 sv: fix a few struct and enum memory leaks 2021-07-06 12:15:08 -04:00
Claire Xen 676c544abe
Merge pull request #2835 from YosysHQ/verific_command
Support command files in Verific
2021-07-05 16:59:37 +02:00
Miodrag Milanovic 0dbb05a75e Add additional help 2021-07-05 09:16:54 +02:00
Zachary Snow f2c2d73f36 sv: fix up end label checking
- disallow [gen]blocks with an end label but not begin label
- check validity of module end label
- fix memory leak of package name and end label
- fix memory leak of module end label
2021-06-16 21:48:05 -04:00
Miodrag Milanovic c0d8da20d5 Support command files in Verific 2021-06-16 11:21:44 +02:00
Xiretza c6681508f1 verilog: fix leaking of type names in parser 2021-06-14 13:56:51 -04:00
Xiretza b57e47fad8 verilog: fix wildcard port connections leaking memory 2021-06-14 13:56:51 -04:00
Xiretza 62a42c317c ast: delete wires and localparams after finishing const evaluation 2021-06-14 13:56:51 -04:00
Xiretza 091295a5a5 verilog: fix leaking ASTNodes 2021-06-14 13:56:51 -04:00
Xiretza 9ca5a91724 ast: fix error condition causing assert to fail
type2str returns a string that doesn't start with $ or \, so it can't be
assigned to an IdString.
2021-06-14 13:56:51 -04:00
Marcelina Kościelnicka 801ecc0e1d verilog: Squash a memory leak.
That was added in ecc22f7fed
2021-06-14 17:07:41 +02:00
Claire Xen 55e8f5061a
Merge pull request #2817 from YosysHQ/claire/fixemails
Fixing old e-mail addresses and deadnames
2021-06-09 13:22:52 +02:00
Zachary Snow 2e697f5655 verilog: check for module scope identifiers during width detection
The recent fix for case expression width detection causes the width of
the expressions to be queried before they are simplified. Because the
logic supporting module scope identifiers only existed in simplify,
looking them up would fail during width detection. This moves the logic
to a common helper used in both simplify() and detectSignWidthWorker().
2021-06-08 15:03:16 -04:00
Zachary Snow c79fbfe0a1 mem2reg: tolerate out of bounds constant accesses
This brings the mem2reg behavior in line with the nomem2reg behavior.
2021-06-08 15:02:57 -04:00
Claire Xenia Wolf 72787f52fc Fixing old e-mail addresses and deadnames
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
2021-06-08 00:39:36 +02:00
Zachary Snow 8cfed1a979 sv: support tasks and functions within packages 2021-06-01 13:17:41 -04:00
Zachary Snow 0795b3ec07 verilog: fix case expression sign and width handling
- The case expression and case item expressions are extended to the
  maximum width among them, and are only interpreted as signed if all of
  them are signed
- Add overall width and sign detection for AST_CASE
- Add sign argument to genWidthRTLIL helper
- Coverage for both const and non-const case statements
2021-05-25 16:16:46 -04:00
Zachary Snow 15f35d6754 sv: support remaining assignment operators
- Add support for: *=, /=, %=, <<=, >>=, <<<=, >>>=
- Unify existing support for: +=, -=, &=, |=, ^=
2021-05-25 16:15:57 -04:00
Rupert Swarbrick 3421979f00 Change the type of current_module to Module
The current_module global is needed so that genRTLIL has somewhere to
put cells and wires that it generates as it makes sense of expressions
that it sees. However, that doesn't actually need to be an AstModule:
the Module base class is enough.

This patch should cause no functional change, but the point is that
it's now possible to call genRTLIL with a module that isn't an
AstModule as "current_module". This will be needed for 'bind' support.
2021-05-13 23:44:48 -04:00
Rupert Swarbrick 51ed4a7149 Use range-based for loop in AST::process
No functional change: just get rid of the explicit iterator and
replace (*it)-> with child->. It's even the same number of characters,
but is hopefully a little easier to read.
2021-05-13 23:37:27 -04:00
Zachary Snow 4452080861 sv: check validity of package end label 2021-05-10 14:37:32 -04:00
Marcelina Kościelnicka 32a0ce9d68 blif: Use library cells' start_offset and upto for wideports.
Fixes #2729.
2021-05-08 15:50:03 +02:00
Claire Xenia Wolf 58290c0c77 Remove duplicates from conns array in JSON front-end, fixes #2736 2021-04-26 16:32:12 +02:00
Zachary Snow ba2ff1ea98 verilog: revise hot comment warnings 2021-03-30 09:21:18 -04:00
Marcelina Kościelnicka 0505c604e7 preproc: Fix up conditional handling.
Fixes #2710.
Fixes #2711.
2021-03-30 02:29:26 +02:00
Zachary Snow c58bb1d2e1 ast: make design available to process_module() 2021-03-24 10:21:00 -04:00
Xiretza 92d5550a90 verilog: check entire user type stack for type definition 2021-03-21 19:35:13 -04:00
Zachary Snow 4f4e70876f sv: allow typenames as function return types 2021-03-19 12:08:43 -04:00
Xiretza 0c66141ed2 verilog: rebuild user_type_stack from globals before parsing file
This was actually a ticking UB bomb: after running the parser, the type
maps contain pointers to children of the current AST, which is
recursively deleted after the pass has executed. This leaves the
pointers in user_type_stack dangling, which just happened to never be a
problem due to another bug that causes typedefs from higher-level type
maps to never be considered.

Rebuilding the type stack from the design's globals ensures the AstNode
pointers are valid.
2021-03-18 20:52:36 -04:00
Marcelina Kościelnicka 8740fdf1d7 ast: Use better parameter serialization for paramod names.
Calling log_signal is problematic for several reasons:

- with recent changes, empty string is serialized as { }, which violates
  the "no spaces in IdString" rule
- the type (plain / real / signed / string) is dropped, wrongly conflating
  functionally different values and potentially introducing a subtle
  elaboration bug

Instead, use a custom simple serialization scheme.
2021-03-18 00:52:00 +01:00
Zachary Snow f71c2dcca6 sv: carry over global typedefs from previous files
This breaks the ability to use a global typename as a standard
identifier in a subsequent input file. This is otherwise backwards
compatible, including for sources which previously included conflicting
typedefs in each input file.
2021-03-17 15:53:52 -04:00
Xiretza 092e923330 verilog: fix buf/not primitives with multiple outputs
From IEEE1364-2005, section 7.3 buf and not gates:

> These two logic gates shall have one input and one or more outputs.
> The last terminal in the terminal list shall connect to the input of the
> logic gate, and the other terminals shall connect to the outputs of
> the logic gate.

yosys does not follow this and instead interprets the first argument as
the output, the second as the input and ignores the rest.
2021-03-17 11:44:03 -04:00
Zachary Snow 4f187d53c5 verilog: support module scope identifiers in parametric modules 2021-03-16 11:01:30 -04:00
Marcelina Kościelnicka 3d9698153f json: Add support for memories.
Previously, memories were silently discarded by the JSON backend, making
round-tripping modules with them crash.

Since there are already some users using JSON to implement custom
external passes that use memories (and infer width/size from memory
ports), let's fix this by just making JSON backend and frontend support
memories as first-class objects.

Processes are still not supported, and will now cause a hard error.

Fixes #1908.
2021-03-15 17:19:19 +01:00
Zachary Snow 640b9927fa sv: allow globals in one file to depend on globals in another
This defers the simplification of globals so that globals in one file
may depend on globals in other files. Adds a simplify() call downstream
because globals are appended at the end.
2021-03-12 11:22:41 -05:00
Zachary Snow cb9f3b6abf verilog: disallow overriding global parameters
It was previously possible to override global parameters on a
per-instance basis. This could be dangerous when using positional
parameter bindings, hiding oversupplied parameters.
2021-03-11 12:36:51 -05:00
whitequark 26e01a67db
Merge pull request #2643 from zachjs/fix-param-no-default-log
Fix param without default log line
2021-03-08 16:36:03 -08:00
Marcelina Kościelnicka 89c74ffd71 verilog: Use proc memory writes in the frontend. 2021-03-08 20:16:29 +01:00
Marcelina Kościelnicka 4e03865d5b Add support for memory writes in processes. 2021-03-08 20:16:29 +01:00
Zachary Snow bdc4fd0e92 Fix param without default log line 2021-03-07 16:06:25 -05:00
whitequark 9bb839c613
Merge pull request #2626 from zachjs/param-no-default
sv: support for parameters without default values
2021-03-07 05:48:03 -08:00
whitequark 72ae15c77c
Merge pull request #2632 from zachjs/width-limit
verilog: impose limit on maximum expression width
2021-03-07 03:45:41 -08:00
Zachary Snow b1a8e73a60 sv: fix some edge cases for unbased unsized literals
- Fix explicit size cast of unbased unsized literals
- Fix unbased unsized literal bound directly to port
- Output `is_unsized` flag in `dumpAst`
2021-03-06 15:20:34 -05:00
Zachary Snow c18ddbcd82 verilog: impose limit on maximum expression width
Designs with unreasonably wide expressions would previously get stuck
allocating memory forever.
2021-03-04 15:20:52 -05:00
Claire Xen 6c56c083f8
Update README 2021-03-04 16:43:30 +01:00
Zachary Snow d738b2c127 sv: support for parameters without default values
- Modules with a parameter without a default value will be automatically
  deferred until the hierarchy pass
- Allows for parameters without defaults as module items, rather than
  just int the `parameter_port_list`, despite being forbidden in the LRM
- Check for parameters without defaults that haven't been overriden
- Add location info to parameter/localparam declarations
2021-03-02 10:43:53 -05:00
Zachary Snow 10a6bc9b81 verilog: fix sizing of ports with int types in module headers
Declaring the ports as standard module items already worked as expected.
This adds a missing usage of `checkRange()` so that headers such as
`module m(output integer x);` now work correctly.
2021-03-01 13:39:05 -05:00
Zachary Snow 1ec5994100 verilog: fix handling of nested ifdef directives
- track depth so we know whether to consider higher-level elsifs
- error on unmatched endif/elsif/else
2021-03-01 12:28:33 -05:00
Claire Xen 004b780b8a
Merge pull request #2523 from tomverbeure/define_synthesis
Add -nosynthesis flag for read_verilog command
2021-03-01 18:00:48 +01:00
whitequark ca5f5ffcd6
Merge pull request #2615 from zachjs/genrtlil-conflict
genrtlil: improve name conflict error messaging
2021-03-01 08:10:19 -08:00
Zachary Snow 0f5b646ab8 sv: extended support for integer types
- Standard data declarations can now use any integer type
- Parameters and localparams can now use any integer type
- Function returns types can now use any integer type
- Fix `parameter logic`, `localparam reg`, etc. to be 1 bit (previously 32 bits)
- Added longint type (64 bits)
- Unified parser source for integer type widths
2021-02-28 16:31:56 -05:00
Zachary Snow bbff844acd genrtlil: improve name conflict error messaging 2021-02-26 18:08:23 -05:00
Michael Singer 04b41ed04a Implement $countones, $isunknown and $onehot{,0} 2021-02-26 12:28:58 -05:00
Michael Singer 8434ba5a3b Implement $countbits function 2021-02-26 12:28:58 -05:00
Zachary Snow 22bed38540 Extend simplify() recursion warning 2021-02-26 12:11:23 -05:00
whitequark 58a5755187
Merge pull request #2554 from hzeller/master
Fix digit-formatting calculation for small numbers.
2021-02-25 13:54:16 -08:00
Marcelina Kościelnicka a651204efa Fix handling of unique/unique0/priority cases in the frontend.
Basically:

- priority converts to (* full_case *)
- unique0 converts to (* parallel_case *)
- unique converts to (* parallel_case, full_case *)

Fixes #2596.
2021-02-25 21:53:58 +01:00
TimRudy dcd9f0af23
Extend "delay" expressions to handle pair and triplet, i.e. rise, fall and turn-off (#2566) 2021-02-24 15:48:15 -05:00
Marcelina Kościelnicka f4f471f342 frontend: Make helper functions for printing locations. 2021-02-23 23:51:52 +01:00
whitequark ad2960adb7
Merge pull request #2594 from zachjs/func-arg-width
verilog: fix sizing of constant args for tasks/functions
2021-02-23 21:46:16 +00:00
Karol Gugala cc7d18d29a frontend: json: parse negative values
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2021-02-23 00:26:11 +01:00
whitequark 01ccb80b70
Merge pull request #2586 from zachjs/tern-recurse
verilog: support recursive functions using ternary expressions
2021-02-21 20:56:04 +00:00
Zachary Snow b6af90fe20 verilog: fix sizing of constant args for tasks/functions
- Simplify synthetic localparams for normal calls to update their width
    - This step was inadvertently removed alongside `added_mod_children`
- Support redeclaration of constant function arguments
    - `eval_const_function` never correctly handled this, but the issue
      was not exposed in the existing tests until the recent change to
      always attempt constant function evaluation when all-const args
      are used
- Check asserts in const_arg_loop and const_func tests
- Add coverage for width mismatch error cases
2021-02-21 15:44:43 -05:00
Zachary Snow 220cb1f7bb verilog: error on macro invocations with missing argument lists
This would previously complain about an undefined internal macro if the
unapplied macro had not already been used. If it had, it would
incorrectly use the arguments from the previous invocation.
2021-02-19 09:18:41 -05:00
Claire Xen 27d7741540
Merge pull request #2574 from dh73/master
Accept disable case for SVA liveness properties.
2021-02-15 17:49:11 +01:00
Zachary Snow 8de2e863af verilog: support recursive functions using ternary expressions
This adds a mechanism for marking certain portions of elaboration as
occurring within unevaluated ternary branches. To enable elaboration of
the overall ternary, this also adds width detection for these
unelaborated function calls.
2021-02-12 14:43:42 -05:00
Miodrag Milanovic 13c2fd7137 Ganulate Verific support 2021-02-12 10:08:43 +01:00
whitequark 326f1c9db4
Merge pull request #2573 from zachjs/repeat-call
verilog: refactored constant function evaluation
2021-02-11 19:56:41 +00:00
Zachary Snow 73d611990d
Merge pull request #2578 from zachjs/genblk-port
verlog: allow shadowing module ports within generate blocks
2021-02-11 10:26:49 -05:00
Kamil Rakoczy 7533534429 Add missing is_signed to type_atom
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2021-02-11 15:05:38 +01:00
Zachary Snow 1d5f3fe506 verlog: allow shadowing module ports within generate blocks
This is a somewhat obscure edge case I encountered while working on test
cases for earlier changes. Declarations in generate blocks should not be
checked against the list of ports. This change also adds a check
forbidding declarations within generate blocks being tagged as inputs or
outputs.
2021-02-07 11:48:39 -05:00
Zachary Snow 4b2f977331 genrtlil: fix signed port connection codegen failures
This fixes binding signed memory reads, signed unary expressions, and
signed complex SigSpecs to ports. This also sets `is_signed` for wires
generated from signed params when -pwires is used. Though not necessary
for any of the current usages, `is_signed` is now appropriately set when
the `extendWidth` helper is used.
2021-02-05 19:51:30 -05:00
Diego H c96eb2fbd7 Accept disable case for SVA liveness properties. 2021-02-04 15:35:35 -06:00
Kamil Rakoczy 98c4feb72f Add check of begin/end labels for genblock
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2021-02-04 17:16:30 +01:00
Zachary Snow b93b6f4285 verilog: refactored constant function evaluation
Elaboration now attempts constant evaluation of any function call with
only constant arguments, regardless of the context or contents of the
function. This removes the concept of "recommended constant evaluation"
which previously applied to functions with `for` loops or which were
(sometimes erroneously) identified as recursive. Any function call in a
constant context (e.g., `localparam`) or which contains a constant-only
procedural construct (`while` or `repeat`) in its body will fail as
before if constant evaluation does not succeed.
2021-02-04 10:18:27 -05:00
whitequark baf1875307
Merge pull request #2529 from zachjs/unnamed-genblk
verilog: significant block scoping improvements
2021-02-04 09:57:28 +00:00
Henner Zeller 5eff0b73ae Provide an integer implementation of decimal_digits().
Signed-off-by: Henner Zeller <h.zeller@acm.org>
2021-02-01 11:23:44 -08:00
Zachary Snow fe74b0cd95 verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.

Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.

1. Unlabled generate blocks are now implicitly named according to the LRM in
   `label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
   synthetic unnamed generate block to avoid creating extra hierarchy levels
   where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
   of the topmost scope, which is necessary because such wires and cells often
   appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
   invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
   scope, completely deferring the inspection and elaboration of nested scopes;
   names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
   to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
   in largely the same manner as other blocks
     before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
      after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
   than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
   prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
   or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode

Addresses the following issues: 656, 2423, 2493
2021-01-31 09:42:09 -05:00
Miodrag Milanovic d99c032c27 Require latest Verific build 2021-01-30 09:23:46 +01:00
Marcelina Kościelnicka a4c04d1b90 ast: fix dump_vlog display of casex/casez
The first child of AST_CASE is the case expression, it's subsequent
childrean that are AST_COND* and can be used to discriminate the type of
the case.
2021-01-29 16:28:15 +01:00
Zachary Snow 27257a419f verilog: strip leading and trailing spaces in macro args 2021-01-28 11:26:35 -05:00
whitequark ffbd813a8c
Merge pull request #2550 from zachjs/macro-arg-spaces
verilog: allow spaces in macro arguments
2021-01-25 10:36:07 +00:00
David Shah 09311b6581 dpi: Support for chandle type
Signed-off-by: David Shah <dave@ds0.me>
2021-01-23 22:24:31 +00:00
Henner Zeller 7d014902ec Fix digit-formatting calculation for small numbers.
Calling log10() on zero causes a non-sensical value to be calculated. On some
compile options, I've observed yosys crashing with an illegal
instruction (SIGILL).

To make it safe, fix the calculation to do a range check; wrap it a
decimal_digits() function, and use it where the previous ceil(log10(n)) call
was used. As a side, it also improves readability.

Signed-off-by: Henner Zeller <h.zeller@acm.org>
2021-01-21 12:20:53 -08:00
Zachary Snow 1096b969ef Allow combination of rand and const modifiers 2021-01-21 08:42:05 -07:00
Claire Xenia Wolf acad7a6e40 Switch verific bindings from Symbiotic EDA flavored Verific to YosysHQ flavored Verific
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-01-20 20:48:10 +01:00
Zachary Snow 006c18fc11 sv: fix support wire and var data type modifiers 2021-01-20 09:16:21 -07:00
Zachary Snow 4fadcc8f25 verilog: allow spaces in macro arguments 2021-01-20 08:49:58 -07:00