yosys

Commit Graph

Author	SHA1	Message	Date
Marcelina Kościelnicka	3209c0762a	intel: Use dfflegalize.	2020-07-13 19:21:05 +02:00
Marcelina Kościelnicka	88e7f90663	Update dff2dffe, dff2dffs, zinit to new FF types.	2020-06-23 18:24:53 +02:00
Marcelina Kościelnicka	aee439360b	Add force_downto and force_upto wire attributes. Fixes #2058.	2020-05-19 01:42:40 +02:00
Diego	643ae9bfc5	Fixing issues in CycloneV cell sim	2019-04-11 19:59:03 -05:00
Larry Doolittle	e2fc18f27b	Reduce amount of trailing whitespace in code base	2019-02-28 14:58:11 -08:00
whitequark	efa278e232	Fix typographical and grammatical errors and inconsistencies. The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.	2019-01-02 13:12:17 +00:00
c60k28	efed2420d6	Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device	2018-03-31 22:48:47 -06:00
Larry Doolittle	50bcd9a728	Clean whitespace and permissions in techlibs/intel	2017-10-05 16:23:49 +02:00
dh73	cbaba62401	Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now	2017-10-01 11:04:17 -05:00

9 Commits