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11541 Commits

Author SHA1 Message Date
Scott Thibault 0a6e2bd5d5 Update comment 2022-02-02 03:21:09 +01:00
Scott Thibault e04ac4e9e9 Fix unextend method for signed constants 2022-02-02 03:21:09 +01:00
Miodrag Milanovic 8ba2000a50 error when no signal found 2022-01-31 17:41:50 +01:00
Miodrag Milanović bf85dfee5e
Merge pull request #3176 from higuoxing/fix-ref-manual 
Fix the help message of synth_quicklogic command.
 2022-01-31 16:11:00 +01:00
Miodrag Milanovic 1b5ff92e62 Cleanup 2022-01-31 13:45:28 +01:00
Miodrag Milanovic eabd0ff115 Compare bits when not all are defined 2022-01-31 13:41:02 +01:00
Miodrag Milanovic 26de52fa09 Cleanup 2022-01-31 12:00:15 +01:00
Miodrag Milanovic 6513300db7 message update 2022-01-31 11:41:52 +01:00
Miodrag Milanovic 543feb75cb Display simulation time data 2022-01-31 10:52:47 +01:00
Miodrag Milanovic a6959d30df Use edges when explicit 2022-01-31 09:38:25 +01:00
Miodrag Milanovic cbadfa0268 Updating initial state and checks 2022-01-31 09:19:34 +01:00
Miodrag Milanovic 190e44f0da Fix scope 2022-01-31 08:56:29 +01:00
github-actions[bot] fc40df0916 Bump version 2022-01-31 00:54:31 +00:00
Marcelina Kościelnicka 56e7791760 verilog backend: Emit a `wire` for ports as well. 
Fixes #3177.
 2022-01-31 01:08:41 +01:00
Xing GUO 0520e99968 Fix the help message of synth_quicklogic. 2022-01-31 02:23:59 +08:00
Marcelina Kościelnicka 07a657fb0c opt_reduce: Add $bmux and $demux optimization patterns. 2022-01-30 03:37:52 +01:00
github-actions[bot] 772d137bfa Bump version 2022-01-29 02:48:50 +00:00
Marcelina Kościelnicka 93508d58da Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00
Miodrag Milanovic f04d1398e5 check if stop before start 2022-01-28 19:41:43 +01:00
Miodrag Milanovic ecbba625c4 set initial state, only flip-flops 2022-01-28 15:59:13 +01:00
Miodrag Milanovic cb12b7c4d8 ignore not found private signals 2022-01-28 14:20:16 +01:00
Miodrag Milanovic f0f3c81c56 preserve VCD mangled names 2022-01-28 14:10:39 +01:00
Miodrag Milanovic 72acce0c82 detect edges even when x 2022-01-28 13:53:27 +01:00
Miodrag Milanovic 81b76155d6 recursive check 2022-01-28 13:24:38 +01:00
Miodrag Milanovic a8d03df173 cleanup 2022-01-28 12:54:16 +01:00
Miodrag Milanovic 4f75a2ca1b Do actual compare 2022-01-28 12:50:41 +01:00
Miodrag Milanovic 7101df62f8 Fix for limit_range_end when not writing vcd 2022-01-28 12:15:14 +01:00
Miodrag Milanovic 3e35de2be1 Add more options and time handling 2022-01-28 10:18:02 +01:00
Marcelina Kościelnicka db33b1e535 opt_dff: Don't mutate muxes while ModWalker is active. 2022-01-28 08:55:56 +01:00
Marcelina Kościelnicka bac750fb99 kernel/mem: Add read-first semantic emulation code. 2022-01-28 08:48:33 +01:00
github-actions[bot] 9a2294f285 Bump version 2022-01-28 02:39:40 +00:00
Marcelina Kościelnicka 0e97c3fd74 manual: Fix a custom pass example. 
Fixes #3156.
 2022-01-27 23:27:45 +01:00
Marcelina Kościelnicka 1759c80a3f memory_bram: Make use of new mem emulation functions to map more RAMs. 2022-01-27 19:31:27 +01:00
Marcelina Kościelnicka 5e4c6915c9 kernel/mem: Add functions to emulate read port enable/init/reset signals. 2022-01-27 19:28:07 +01:00
github-actions[bot] 84f0df1c95 Bump version 2022-01-27 00:56:19 +00:00
Miodrag Milanović 76f7b030ae
change to windows-2019 2022-01-26 18:00:41 +01:00
Miodrag Milanovic ccc3e3d13a update version 2022-01-26 17:24:17 +01:00
Miodrag Milanovic 40018e191b Display values of outputs 2022-01-26 16:52:36 +01:00
Miodrag Milanovic 226dc659f0 Fix tabs/spaces 2022-01-26 16:39:51 +01:00
Miodrag Milanovic be7be63fec Check if stimulated 2022-01-26 15:51:43 +01:00
Miodrag Milanovic 9a8939f0a4 Read fst and use data to set inputs 2022-01-26 15:50:38 +01:00
Miodrag Milanovic 8a02616465 Add fstdata helper class 2022-01-26 10:23:38 +01:00
Miodrag Milanovic c811a71301 Cleanup of config to support platforms 2022-01-26 09:58:27 +01:00
Miodrag Milanovic ccfc00705a Add ability to write to FST file 2022-01-26 09:26:19 +01:00
Miodrag Milanovic 9e9083bbe9 Add FST library 2022-01-25 09:53:41 +01:00
github-actions[bot] bc027b2cae Bump version 2022-01-20 01:06:01 +00:00
gatecat f699c4ba58 nexus: Fix BB sim model 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-01-19 18:14:24 +00:00
Miodrag Milanovic 36482680d5 Removed dbits 8 since 9 will always be picked 2022-01-19 08:51:25 +01:00
Miodrag Milanović 4525e419f6
Merge pull request #3120 from Icenowy/anlogic-bram 
anlogic: support BRAM mapping
 2022-01-19 08:49:58 +01:00
Zachary Snow 342927732e fix dumpAst() compilation warning 2022-01-18 00:17:08 -07:00