Clifford Wolf
|
f1764b4fe9
|
Added $dffe cell type
|
2014-12-08 10:50:19 +01:00 |
Clifford Wolf
|
fad9cec47b
|
Added $_DFFE_??_ cell types
|
2014-12-08 10:43:38 +01:00 |
Clifford Wolf
|
74ef92b9c8
|
Added "abc" label in synth script
|
2014-10-31 03:46:27 +01:00 |
Clifford Wolf
|
ab28491f27
|
Added "opt -full" alias for all more aggressive optimizations
|
2014-10-31 03:36:51 +01:00 |
Clifford Wolf
|
c3e779a65f
|
Added $_BUF_ cell type
|
2014-10-03 10:12:28 +02:00 |
Clifford Wolf
|
f9a307a50b
|
namespace Yosys
|
2014-09-27 16:17:53 +02:00 |
Clifford Wolf
|
4888d61c65
|
Improvements in "synth" script
|
2014-09-18 12:57:55 +02:00 |
Clifford Wolf
|
6644e27cd4
|
Fixed $macc simlib model for zero-config
|
2014-09-16 08:19:35 +02:00 |
Clifford Wolf
|
7815f81c32
|
Added "synth" command
|
2014-09-14 16:09:06 +02:00 |
Clifford Wolf
|
923bbbeaf0
|
Using alumacc in techmap.v
|
2014-09-14 14:50:15 +02:00 |
Clifford Wolf
|
44b5bd4b63
|
Fixed simlib $macc model for xilinx xsim
|
2014-09-08 17:09:39 +02:00 |
Clifford Wolf
|
fcb46138ce
|
Simplified $fa undef model
|
2014-09-08 16:59:39 +02:00 |
Clifford Wolf
|
6dc07eb1f2
|
Fixes and cleanups for blackbox.v
|
2014-09-08 13:31:04 +02:00 |
Clifford Wolf
|
af0c8873bb
|
Added $lcu cell type
|
2014-09-08 13:31:04 +02:00 |
Clifford Wolf
|
d46bac3305
|
Added "$fa" cell type
|
2014-09-08 12:15:39 +02:00 |
Clifford Wolf
|
dd887cc025
|
Using maccmap for $macc and $mul techmap
|
2014-09-07 18:24:08 +02:00 |
Clifford Wolf
|
9329a76818
|
Various bug fixes (related to $macc model testing)
|
2014-09-06 20:30:46 +02:00 |
Clifford Wolf
|
fa64942018
|
Added $macc SAT model
|
2014-09-06 19:44:11 +02:00 |
Clifford Wolf
|
bff4706b62
|
Added $macc simlib model (also use as techmap rule for now)
|
2014-09-06 17:59:12 +02:00 |
Clifford Wolf
|
8927aa6148
|
Removed $bu0 cell type
|
2014-09-04 02:07:52 +02:00 |
Clifford Wolf
|
635b922afe
|
Undef-related fixes in simlib $alu model
|
2014-09-02 23:21:59 +02:00 |
Clifford Wolf
|
c38283dbd0
|
Small bug fixes in $not, $neg, and $shiftx models
|
2014-09-02 17:48:41 +02:00 |
Clifford Wolf
|
9923762461
|
Fixed "test_cell -simlib all"
|
2014-09-01 15:37:56 +02:00 |
Clifford Wolf
|
8649b57b6f
|
Added $lut support in test_cell, techmap, satgen
|
2014-08-31 17:43:31 +02:00 |
Clifford Wolf
|
4724d94fbc
|
Added $alu cell type
|
2014-08-30 18:59:05 +02:00 |
Clifford Wolf
|
eb571cba6a
|
Replaced $__alu CO/CS outputs with full-width CO output
|
2014-08-30 15:12:39 +02:00 |
Clifford Wolf
|
a92a68ce52
|
Using "via_celltype" in $mul carry-save-acc implementation
|
2014-08-18 14:30:20 +02:00 |
Clifford Wolf
|
6f33fc3e87
|
Performance fix for new $__lcu techmap rule
|
2014-08-18 00:27:54 +02:00 |
Clifford Wolf
|
4b3834e0cc
|
Replaced recursive lcu scheme with bk adder
|
2014-08-18 00:03:33 +02:00 |
Clifford Wolf
|
976bda7102
|
Multiply using a carry-save accumulator
|
2014-08-16 21:07:29 +02:00 |
Clifford Wolf
|
47c2637a96
|
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
|
2014-08-16 18:29:39 +02:00 |
Clifford Wolf
|
1ddf150c35
|
Changes in techmap $__alu interface
|
2014-08-16 16:01:58 +02:00 |
Clifford Wolf
|
b64b38eea2
|
Renamed $lut ports to follow A-Y naming scheme
|
2014-08-15 14:18:40 +02:00 |
Clifford Wolf
|
f092b50148
|
Renamed $_INV_ cell type to $_NOT_
|
2014-08-15 14:11:40 +02:00 |
Clifford Wolf
|
5602cbde9f
|
Simplified $__arraymul techmap rule
|
2014-08-14 20:53:21 +02:00 |
Clifford Wolf
|
13f2f36884
|
RIP $safe_pmux
|
2014-08-14 11:39:46 +02:00 |
Clifford Wolf
|
7e758d5fbb
|
Added techmap support for actual lookahead carry unit
|
2014-08-13 18:40:57 +02:00 |
Clifford Wolf
|
9a065509ac
|
Preparations for lookahead ALU support in techmap.v
|
2014-08-13 16:36:30 +02:00 |
Clifford Wolf
|
c27120fcbc
|
New interface for $__alu in techmap.v
|
2014-08-13 13:04:28 +02:00 |
Clifford Wolf
|
312ee00c9e
|
Added adff2dff.v (for techmap -share_map)
|
2014-08-07 16:14:38 +02:00 |
Clifford Wolf
|
014a41fcf3
|
Implemented recursive techmap
|
2014-08-03 12:40:43 +02:00 |
Clifford Wolf
|
1202f7aa4b
|
Renamed "stdcells.v" to "techmap.v"
|
2014-07-31 02:32:00 +02:00 |
Clifford Wolf
|
41555cde10
|
Reorganized stdcells.v (no actual code change, just moved and indented stuff)
|
2014-07-31 02:21:06 +02:00 |
Clifford Wolf
|
2541489105
|
Added techmap CONSTMAP feature
|
2014-07-30 22:04:30 +02:00 |
Clifford Wolf
|
6c05badc43
|
New techmap default rules for $shr $sshr $shl $sshl
|
2014-07-30 18:49:12 +02:00 |
Clifford Wolf
|
2145e57ef0
|
Bugfix in simlib.v for iverilog
|
2014-07-29 19:23:31 +02:00 |
Clifford Wolf
|
397b00252d
|
Added $shift and $shiftx cell types (needed for correct part select behavior)
|
2014-07-29 16:35:13 +02:00 |
Clifford Wolf
|
b17d6531c8
|
Added "make PRETTY=1"
|
2014-07-24 17:15:01 +02:00 |
Clifford Wolf
|
f1ca93a0a3
|
Fixed simlib.v model for $mem
|
2014-07-17 16:48:36 +02:00 |
Clifford Wolf
|
dcdd5c11b4
|
Updated simlib to new $mem/$memwr interface
|
2014-07-16 11:46:40 +02:00 |
Clifford Wolf
|
7370ae01e9
|
Added SIMLIB_NOLUT to simlib.v
|
2014-04-02 21:28:33 +02:00 |
Clifford Wolf
|
e24797add0
|
Added SIMLIB_NOSR to simlib.v
|
2014-04-02 21:06:55 +02:00 |
Clifford Wolf
|
d4a1b0af5b
|
Added support for dlatchsr cells
|
2014-03-31 14:14:40 +02:00 |
Clifford Wolf
|
7aa2d746b7
|
Merged addition of SED makefile variable from github.com/Siesh1oo/yosys
(see https://github.com/cliffordwolf/yosys/pull/28)
|
2014-03-11 14:42:58 +01:00 |
Clifford Wolf
|
973507d85b
|
Fixes for improved techmap of shifts with large B inputs
|
2014-03-06 13:33:12 +01:00 |
Clifford Wolf
|
8406e7f7b6
|
Strictly zero-extend unsigned A-inputs of shift operations in techmap
|
2014-03-06 12:15:44 +01:00 |
Clifford Wolf
|
d7f29bb23f
|
Improved techmap of shift with wide B inputs
|
2014-03-06 12:14:20 +01:00 |
Clifford Wolf
|
fc3b3c4ec3
|
Added $slice and $concat cell types
|
2014-02-07 17:44:57 +01:00 |
Clifford Wolf
|
a6750b3753
|
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
|
2014-02-03 13:01:45 +01:00 |
Clifford Wolf
|
ed8ad99960
|
More changes to techlibs/common/simlib.v for LEC
|
2014-01-31 11:21:29 +01:00 |
Clifford Wolf
|
6a7d7e847d
|
Added test comments to techlibs/cmos/cmos_cells.lib
|
2014-01-29 10:51:02 +01:00 |
Clifford Wolf
|
a86f33653d
|
Major rewrite of techlibs/common/simlib.v for LEC (cadance conformal)
|
2014-01-29 00:36:03 +01:00 |
Clifford Wolf
|
1e67099b77
|
Added $assert cell
|
2014-01-19 14:03:40 +01:00 |
Clifford Wolf
|
3d7a1491aa
|
Fixed $lut simlib model for a wider range of tools
|
2014-01-18 19:31:40 +01:00 |
Clifford Wolf
|
2fbaaaca7a
|
More changes to simlib to make it friendlier to a wider range of tools
|
2014-01-18 19:13:43 +01:00 |
Clifford Wolf
|
4a9e133fab
|
Fixed a type in $mem model in simlib.v
|
2014-01-18 18:54:50 +01:00 |
Clifford Wolf
|
bef17eeb10
|
Removed cases of trailing comma in stdcells.v
|
2014-01-18 15:36:17 +01:00 |
Clifford Wolf
|
5b96675696
|
Added $bu0 cell to simlib.v
|
2014-01-18 15:35:15 +01:00 |
Clifford Wolf
|
db9cf544b8
|
Added techlibs/common/pmux2mux.v
|
2014-01-17 20:06:15 +01:00 |
Clifford Wolf
|
b3b00f1bf4
|
Various small cleanups in stdcells.v techmap code
|
2013-12-31 15:41:40 +01:00 |
Clifford Wolf
|
c69c416d28
|
Added $bu0 cell (for easy correct $eq/$ne mapping)
|
2013-12-28 12:02:14 +01:00 |
Clifford Wolf
|
369bf81a70
|
Added support for non-const === and !== (for miter circuits)
|
2013-12-27 14:20:15 +01:00 |
Clifford Wolf
|
76f7c10cfc
|
Using simplemap mappers from techmap
|
2013-11-24 23:31:14 +01:00 |
Clifford Wolf
|
1afe6589df
|
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
|
2013-11-24 20:44:00 +01:00 |
Clifford Wolf
|
20175afd29
|
Added "techmap -share_map" option
|
2013-11-24 19:50:25 +01:00 |
Clifford Wolf
|
ae798d3fd5
|
Fixed xilinx/example_sim_counter test bench
|
2013-11-24 17:55:46 +01:00 |
Clifford Wolf
|
532091afcb
|
Added more generic _TECHMAP_ wire mechanism to techmap pass
|
2013-11-23 15:58:06 +01:00 |
Clifford Wolf
|
1c4a6411af
|
Updated abc
|
2013-11-21 22:39:10 +01:00 |
Clifford Wolf
|
0c91f890c9
|
Install simlib in datdir
|
2013-11-19 23:05:46 +01:00 |
Clifford Wolf
|
97f2979bba
|
Added commented-out osu025 maping commands to cmos techmap example
|
2013-11-18 12:01:00 +01:00 |
Clifford Wolf
|
e5b974fa2a
|
Cleanups and bugfixes in response to new internal cell checker
|
2013-11-11 00:39:45 +01:00 |
Clifford Wolf
|
404b46674b
|
Fixed techmap of $reduce_xnor with multi-bit outputs
|
2013-11-07 00:58:06 +01:00 |
Clifford Wolf
|
b41740060b
|
Fixed techmap of $gt and $ge with multi-bit outputs
|
2013-11-06 22:59:45 +01:00 |
Clifford Wolf
|
6fcbc79b5c
|
Improved width extension with regard to undef propagation
|
2013-11-06 21:05:11 +01:00 |
Clifford Wolf
|
0b4a64ac6a
|
Added DFFSR cell to techlibs/cmos/cmos_cells.lib
|
2013-10-31 12:27:35 +01:00 |
James Walmsley
|
40b3551b45
|
[EXAMPLES] Ported the mojo counter example to Zynq ZED board.
Will be adding a tutorial on this to verilog.james.walms.co.uk in a few days.
|
2013-10-27 21:48:39 +01:00 |
Clifford Wolf
|
88cd2eadf5
|
Cleanups in xilinx examples
|
2013-10-27 09:58:53 +01:00 |
Clifford Wolf
|
4a3669d871
|
Added synth_xilinx command
|
2013-10-27 09:51:06 +01:00 |
Clifford Wolf
|
90b016716b
|
Moved simple xilinx counter sim example to subdir
|
2013-10-27 09:30:17 +01:00 |
Clifford Wolf
|
02f321b6fc
|
Xilinx mojo_counter example is now working
|
2013-10-27 08:21:56 +01:00 |
Clifford Wolf
|
d635f8adaa
|
Renamed techlibs/xilinx7 to techlibs/xilinx
|
2013-10-26 22:29:40 +02:00 |
Clifford Wolf
|
4007b41d40
|
Improved xilinx mojo_counter example
|
2013-10-26 22:28:42 +02:00 |
Clifford Wolf
|
b934a2d209
|
Added another xilinx example (not funcional yet)
|
2013-10-26 17:22:29 +02:00 |
Clifford Wolf
|
0836a1f2ba
|
Bugfix in dffsr techmap rules
|
2013-10-18 13:24:44 +02:00 |
Clifford Wolf
|
8197169f8d
|
Added techmap rules for $sr, $dffsr and $dlatch
|
2013-10-18 12:29:21 +02:00 |
Clifford Wolf
|
e0f693cbb0
|
Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_
|
2013-10-18 12:13:34 +02:00 |
Clifford Wolf
|
5998c101a4
|
Added $sr, $dffsr and $dlatch cell types
|
2013-10-18 11:56:16 +02:00 |
Clifford Wolf
|
5745d3de9a
|
Added map, par and bitgen to xlinx7 example
|
2013-10-16 10:57:18 +02:00 |
Clifford Wolf
|
288ba9618a
|
Moved common techlib files to techlibs/common
|
2013-09-15 11:52:57 +02:00 |
Clifford Wolf
|
2c9bd23801
|
Added spice testbench to techlibs/cmos
|
2013-09-14 13:29:11 +02:00 |
Clifford Wolf
|
bbe5aa446b
|
Added spice backend
|
2013-09-14 11:23:45 +02:00 |
Clifford Wolf
|
6685ad436e
|
Added mapping to techlibs/xilinx7 testbench (exposes EDIF backend todos)
|
2013-08-27 13:12:26 +02:00 |
Clifford Wolf
|
5059b31660
|
Added simple xilinx7 technology mapping files
|
2013-08-22 20:31:04 +02:00 |
Clifford Wolf
|
a860efa8ac
|
Implemented same div-by-zero behavior as found in other synthesis tools
|
2013-08-15 21:00:06 +02:00 |
Clifford Wolf
|
c8763301b4
|
Added $div and $mod technology mapping
|
2013-08-09 17:09:24 +02:00 |
Clifford Wolf
|
ad9bbcbf40
|
Added $lut cells and abc lut mapping support
|
2013-07-23 16:19:34 +02:00 |
Clifford Wolf
|
7daeee340a
|
Fixed shift ops with large right hand side
|
2013-07-09 18:59:59 +02:00 |
Clifford Wolf
|
0c6ffc4c65
|
More fixes for bugs found using xsthammer
|
2013-06-13 11:18:45 +02:00 |
Clifford Wolf
|
7f3f25841e
|
More sign-extension related fixes
|
2013-06-10 21:04:04 +02:00 |
Clifford Wolf
|
29d6ebd961
|
Implemented technology mapping for multipliers (using array multiplier)
|
2013-06-03 12:48:44 +02:00 |
Clifford Wolf
|
32dbf7752d
|
Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v
|
2013-04-07 16:42:29 +02:00 |
Clifford Wolf
|
d60fbaf664
|
Added EXTRA_TARGETS Makefile variable
|
2013-03-28 16:53:40 +01:00 |
Clifford Wolf
|
26f2439551
|
Tiny bugfix in simlib.v
|
2013-03-26 19:06:28 +01:00 |
Clifford Wolf
|
6960df7285
|
Fixed stdcells.v for $adff with undef reset value
|
2013-03-24 10:43:05 +01:00 |
Clifford Wolf
|
11789db206
|
More support code for $sr cells
|
2013-03-14 11:15:00 +01:00 |
Clifford Wolf
|
6543917fb8
|
added .gitignore files
|
2013-01-05 11:19:11 +01:00 |
Clifford Wolf
|
7764d0ba1d
|
initial import
|
2013-01-05 11:13:26 +01:00 |