Commit Graph

21 Commits

Author SHA1 Message Date
Marcelina Kościelnicka f4d1426229 anlogic: Use `memory_libmap` pass. 2022-05-18 17:32:56 +02:00
Icenowy Zheng c2b7ad3b28 anlogic: support BRAM mapping
Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being
true dual port (or 18bit*512 when simple dual port), the other is
16bit*2K.

Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and
32Kbit BRAM with 8bit width are not support yet.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2021-12-17 20:28:22 +08:00
Claire Xenia Wolf 72787f52fc Fixing old e-mail addresses and deadnames
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
2021-06-08 00:39:36 +02:00
gatecat cae905f551 Blackbox all whiteboxes after synthesis
This prevents issues like processes in whiteboxes triggering an error in
the JSON backend.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-17 21:07:20 +00:00
Marcelina Kościelnicka 3050454d6e anlogic: Use dfflegalize. 2020-07-14 05:02:50 +02:00
whitequark 7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
Marcelina Kościelnicka 38a0c30d65 Get rid of dffsr2dff.
This pass is a proper subset of opt_rmdff, which is called by opt, which
is called by every synth flow in the coarse part.  Thus, it never
actually does anything and can be safely removed.
2020-04-15 16:22:37 +02:00
Eddie Hung 0b0148399c synth_*: call 'opt -fast' after 'techmap' 2020-02-05 18:39:01 -08:00
whitequark f8d5920a7e
Merge pull request from whitequark/unify-ram-naming
Harmonize BRAM/LUTRAM descriptions across all of Yosys
2020-01-02 21:06:17 +00:00
whitequark 550310e264 Harmonize BRAM/LUTRAM descriptions across all of Yosys.
This commit:
  * renames all remaining instances of "DRAM" (which is ambiguous)
    to "LUTRAM" (which is not), finishing the work started in
    the commit 698ab9be;
  * renames memory rule files to brams.txt/lutrams.txt;
  * adds/renames script labels map_bram/map_lutram;
  * extracts where necessary script labels map_ffram and map_gates;
  * adds where necessary options -nobram/-nolutram.

The end result is that BRAM/LUTRAM/FFRAM aspects of every target
are now consistent with each other.

Per architecture:
  * anlogic: rename drams.txt→lutrams.txt, add -nolutram, add
    :map_lutram, :map_ffram, :map_gates
  * ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt
  * efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram,
    :map_gates
  * gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt,
    rename -nodram→-nolutram (-nodram still recognized), rename
    :bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
2020-01-01 12:30:00 +00:00
Eddie Hung 79448f9be0 Update doc that "-retime" calls abc with "-dff -D 1" 2019-12-30 13:28:29 -08:00
Eddie Hung aa6d06c1b5 Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""
This reverts commit 6008bb7002.
2019-12-30 13:28:29 -08:00
Miodrag Milanovic 5f561bdcb1 Proper arith for Anlogic and use standard pass 2019-08-12 20:21:36 +02:00
Clifford Wolf 56ca1e6afc
Merge pull request from Icenowy/anlogic-dram-init
anlogic: implement DRAM initialization
2019-01-02 16:28:18 +01:00
Clifford Wolf 979de95cf6
Merge pull request from Icenowy/anlogic-ff-init
Initialization of Anlogic DFFs
2019-01-02 15:52:22 +01:00
whitequark efa278e232 Fix typographical and grammatical errors and inconsistencies.
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.
2019-01-02 13:12:17 +00:00
Icenowy Zheng 90d00182cf anlogic: implement DRAM initialization
As the TD tool doesn't accept the DRAM cell to contain unknown values in
the initial value, the initialzation support of DRAM is previously
skipped.

Now add the support by add a new pass to determine unknown values in the
initial value.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-20 07:56:15 +08:00
Icenowy Zheng c9513c695a Anlogic: let LUT5/6 have more cost than LUT4-
According to the datasheet of Anlogic Eagle FPGAs, The LUTs natively
in an Anlogic FPGA is LUT4 (in MSLICEs) and "Enhanced LUT5" (in
LSLICEs). An "Enhanced LUT5" can be divided into two LUT4s.

So a LUT5 will cost around 2x resource of a LUT4, and a LUT6 will cost
2x resource of a LUT5.

Change the -lut parameter passed to the abc command to pass this cost
info to the ABC process.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-19 09:36:53 +08:00
Icenowy Zheng 4bf8ac728c anlogic: set the init value of DFFs
As dffinit has already supported for different initialization strings
for DFFs and check for re-initialization, initialization of Anlogic
DFFs are now ready to go.

Support for set the init values of Anlogic DFFs.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-18 23:16:37 +08:00
Icenowy Zheng d53a2bd1d3 anlogic: add support for Eagle Distributed RAM
The MSLICEs on the Eagle series of FPGA can be configured as Distributed
RAM.

Enable to synthesis to DRAM.

As the Anlogic software suite doesn't support any 'bx to exist in the
initializtion data of DRAM, do not enable the initialization support of
the inferred DRAM.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-17 23:20:40 +08:00
Miodrag Milanovic 83bce9f59c Initial support for Anlogic FPGA 2018-12-01 18:28:54 +01:00