Eddie Hung
|
5939ffdc07
|
Forgot to slice
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2019-08-23 13:06:59 -07:00 |
Eddie Hung
|
242b3083ea
|
Cope with possibility that D could connect to Q on same cell
|
2019-08-23 13:06:31 -07:00 |
Eddie Hung
|
18b64609c2
|
xilinx_srl to use 'slice' features of pmgen for word level
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2019-08-23 12:22:06 -07:00 |
Eddie Hung
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f4fd41d5d2
|
Merge remote-tracking branch 'origin/clifford/pmgen' into eddie/xilinx_srl
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2019-08-23 11:35:06 -07:00 |
Clifford Wolf
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55bf8f69e0
|
Fix port hanlding in pmgen
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-23 16:26:54 +02:00 |
Clifford Wolf
|
adb81ba386
|
Add pmgen slices and choices
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-23 16:15:50 +02:00 |
Eddie Hung
|
6e8fda8bf0
|
Add doc
|
2019-08-22 11:52:24 -07:00 |
Eddie Hung
|
cabadb85e2
|
Add copyright
|
2019-08-22 11:25:19 -07:00 |
Eddie Hung
|
9f3ed1726e
|
pmgen to also iterate over all module ports
|
2019-08-22 11:15:16 -07:00 |
Eddie Hung
|
74bd190d3b
|
Remove output_bits
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2019-08-22 11:14:59 -07:00 |
Eddie Hung
|
231ddbf95c
|
Forgot to set ud_variable.minlen
|
2019-08-22 11:02:17 -07:00 |
Eddie Hung
|
61639d5387
|
Do not run xilinx_srl_pm in fixed loop
|
2019-08-22 10:51:04 -07:00 |
Eddie Hung
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d0b2973413
|
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
|
2019-08-22 10:32:06 -07:00 |
Eddie Hung
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7d02d17b16
|
Reuse var
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2019-08-21 19:18:40 -07:00 |
Eddie Hung
|
5c8344363f
|
Revert "Trim shiftx_width when upper bits are 1'bx"
This reverts commit 7e7965ca7b .
|
2019-08-21 19:18:27 -07:00 |
Eddie Hung
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7e7965ca7b
|
Trim shiftx_width when upper bits are 1'bx
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2019-08-21 18:43:17 -07:00 |
Eddie Hung
|
ed7be3e6b6
|
Add comment
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2019-08-21 17:36:38 -07:00 |
Eddie Hung
|
15188033da
|
Add variable length support to xilinx_srl
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2019-08-21 17:34:40 -07:00 |
Eddie Hung
|
6d76ae4c65
|
Rename pattern to fixed
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2019-08-21 15:46:58 -07:00 |
Eddie Hung
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b0a3b430bf
|
attribute -> attr
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2019-08-21 15:44:07 -07:00 |
Eddie Hung
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61b4d7ae13
|
Use Cell::has_keep_attribute()
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2019-08-21 15:41:46 -07:00 |
Eddie Hung
|
6fa9e03e4c
|
xilinx_srl to support FDRE and FDRE_1
|
2019-08-21 15:35:29 -07:00 |
Eddie Hung
|
3c8e8521a6
|
Fix polarity of EN_POL
|
2019-08-21 14:42:11 -07:00 |
Eddie Hung
|
a980f0d4be
|
Add CLKPOL == 0
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2019-08-21 14:35:40 -07:00 |
Eddie Hung
|
1c7d721558
|
Reject if not minlen from inside pattern matcher
|
2019-08-21 14:26:24 -07:00 |
Eddie Hung
|
cab2bd083e
|
Get wire via SigBit
|
2019-08-21 13:47:47 -07:00 |
Eddie Hung
|
52fea5b658
|
Respect \keep on cells or wires
|
2019-08-21 13:42:03 -07:00 |
Eddie Hung
|
5ce0c31d0e
|
Add init support
|
2019-08-21 13:05:10 -07:00 |
Eddie Hung
|
df53fe12e7
|
Fix spacing
|
2019-08-21 12:54:11 -07:00 |
Eddie Hung
|
0250712486
|
Initial progress on xilinx_srl
|
2019-08-21 12:50:49 -07:00 |
Miodrag Milanovic
|
948b6f91a1
|
Fix test_pmgen deps
|
2019-08-21 17:00:24 +02:00 |
Eddie Hung
|
4cc74346f1
|
Fix compile error
|
2019-08-20 20:27:05 -07:00 |
Eddie Hung
|
9b9d759451
|
Fix copy-paste typo
|
2019-08-20 20:18:51 -07:00 |
Eddie Hung
|
b7a48e3e0f
|
Merge remote-tracking branch 'origin/master' into xc7dsp
|
2019-08-20 20:18:17 -07:00 |
Clifford Wolf
|
d0117d7d12
|
Merge branch 'master' into clifford/pmgen
|
2019-08-20 11:39:23 +02:00 |
Clifford Wolf
|
1e3dd0a2da
|
Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen
|
2019-08-19 13:04:06 +02:00 |
Miodrag Milanovic
|
dbe3cb9708
|
Ignore all generated headers for pmgen pass
|
2019-08-18 10:49:17 +02:00 |
Clifford Wolf
|
f3405fb048
|
Refactor pmgen rollback mechanism
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-17 13:54:18 +02:00 |
Clifford Wolf
|
318ae0351c
|
Improvements in "test_pmgen -generate"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-17 13:53:55 +02:00 |
Clifford Wolf
|
f95853c822
|
Add pmgen "fallthrough" statement
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-17 11:29:37 +02:00 |
Eddie Hung
|
cd5a372cd1
|
Add help() call
|
2019-08-16 13:00:12 -07:00 |
Clifford Wolf
|
64bd414e54
|
Minor bugfix in "test_pmgen -generate"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-16 14:35:13 +02:00 |
Clifford Wolf
|
20910fd7c8
|
Add pmgen finish statement, return number of matches
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-16 14:16:35 +02:00 |
Clifford Wolf
|
f45dad8220
|
Redesign pmgen backtracking for recursive matching
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-16 13:47:50 +02:00 |
Clifford Wolf
|
c710df181c
|
Add pmgen "generate" feature
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-16 13:26:36 +02:00 |
Clifford Wolf
|
4a57b7e1ab
|
Refactor demo_reduce into test_pmgen
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-16 11:47:51 +02:00 |
Clifford Wolf
|
016036f247
|
Add doc for pmgen semioptional statement, Add pmgen changes to CHANGELOG
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-15 23:02:37 +02:00 |
Clifford Wolf
|
969ab9027a
|
Update pmgen documentation
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-15 22:48:13 +02:00 |
Clifford Wolf
|
eb80d3d43f
|
Change pmgen default rule to reject, switch peepopt behavior to accept
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-15 22:47:59 +02:00 |
Eddie Hung
|
c320abc3f4
|
xilinx_dsp to be sensitive to keep attribute
|
2019-08-15 12:34:11 -07:00 |
Eddie Hung
|
96ee7b9cf7
|
Simplify
|
2019-08-15 12:30:46 -07:00 |
Eddie Hung
|
27d5df9467
|
ffH -> ffFJKG
|
2019-08-15 12:19:34 -07:00 |
Clifford Wolf
|
03f98d9176
|
Add demo_reduce pass to demonstrace recursive pattern matching
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-15 18:36:39 +02:00 |
Clifford Wolf
|
73bf453929
|
Improvements in pmgen for recursive patterns
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-15 18:35:56 +02:00 |
Eddie Hung
|
aad97168b0
|
Fixes for reverting SigSpec helper functions
|
2019-08-14 10:22:33 -07:00 |
Eddie Hung
|
2f04beeeb5
|
Perform C -> PCIN optimisation after pattern matcher
|
2019-08-13 17:11:35 -07:00 |
Eddie Hung
|
1b0e68db94
|
Revert changes to RTLIL::SigSpec methods
|
2019-08-13 17:09:28 -07:00 |
Eddie Hung
|
0597a3ea23
|
Rename to XilinxDspPass
|
2019-08-13 10:23:07 -07:00 |
Eddie Hung
|
12c692f6ed
|
Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
This reverts commit c851dc1310 , reversing
changes made to f54bf1631f .
|
2019-08-12 12:06:45 -07:00 |
David Shah
|
f9020ce2b3
|
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"
|
2019-08-10 17:14:48 +01:00 |
Eddie Hung
|
ab1d63a565
|
Check nusers of DSP output, not whole flop
|
2019-08-09 17:35:13 -07:00 |
Eddie Hung
|
3dd3ab98c2
|
Improve ice40_dsp for non-fully-32-bit adders
|
2019-08-09 17:23:12 -07:00 |
Eddie Hung
|
dfc878deb4
|
Another filter -> if
|
2019-08-09 16:23:32 -07:00 |
Eddie Hung
|
e83f231927
|
Cleanup
|
2019-08-09 15:47:40 -07:00 |
Eddie Hung
|
0b5b56c1ec
|
Pack partial-product adder DSP48E1 packing
|
2019-08-09 15:19:33 -07:00 |
Eddie Hung
|
a002eba14a
|
Fix check
|
2019-08-09 14:27:08 -07:00 |
Eddie Hung
|
82cbfada1b
|
Revert "Fix typo"
This reverts commit e3c39cc450 .
|
2019-08-09 14:14:28 -07:00 |
Eddie Hung
|
747690a6df
|
Remove muxY and ffY for now
|
2019-08-08 16:33:37 -07:00 |
Eddie Hung
|
2c0be7aa5d
|
Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing
|
2019-08-08 12:56:05 -07:00 |
Eddie Hung
|
07e50b9c25
|
Only pack registers if {A,B,P}REG = 0, do not pack $dffe
|
2019-08-08 10:51:19 -07:00 |
Eddie Hung
|
911129e3ef
|
Disable $dffe
|
2019-08-08 10:44:49 -07:00 |
Eddie Hung
|
675c1d4218
|
Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER
|
2019-08-07 16:29:38 -07:00 |
Eddie Hung
|
fb568ddb4e
|
Fix compile error
|
2019-08-07 14:31:55 -07:00 |
Eddie Hung
|
d90b8b081a
|
Do not SigSpec::extract() beyond bounds
|
2019-08-07 13:58:26 -07:00 |
Eddie Hung
|
cdf9c80134
|
Do not pack registers if (* keep *)
|
2019-08-07 12:57:10 -07:00 |
Eddie Hung
|
c39b1a6fcf
|
Add comment about supporting $dffe in ice40_dsp
|
2019-08-01 15:13:18 -07:00 |
Eddie Hung
|
ed7540a46f
|
Pack P register properly
|
2019-08-01 15:10:43 -07:00 |
Eddie Hung
|
e19d33b003
|
Cope with sign extension in mul2dsp
|
2019-08-01 12:44:56 -07:00 |
Eddie Hung
|
c54a39069d
|
CO is sign extension only if signed multiplier
|
2019-08-01 10:00:49 -07:00 |
Eddie Hung
|
e3c39cc450
|
Fix typo
|
2019-08-01 10:00:01 -07:00 |
Eddie Hung
|
e4a638c292
|
Restore old CO behaviour
|
2019-07-31 15:45:15 -07:00 |
Eddie Hung
|
4c25d1a76f
|
Pop the CO bit from O
|
2019-07-26 10:27:30 -07:00 |
Eddie Hung
|
c1a05f4557
|
Allow adders/accumulators with 33 bits using CO output
|
2019-07-26 10:15:36 -07:00 |
Eddie Hung
|
79fd6edc5a
|
Eliminate warnings by sizing O correctly
|
2019-07-23 15:13:30 -07:00 |
Eddie Hung
|
a37574ccbf
|
Fix muxAB logic
|
2019-07-23 14:52:14 -07:00 |
Eddie Hung
|
0dd2a125f6
|
Remove debug print
|
2019-07-23 14:21:45 -07:00 |
Eddie Hung
|
dc0c853abe
|
Simplify and fix for MACs
|
2019-07-23 14:20:34 -07:00 |
Eddie Hung
|
4f11ff8ebd
|
Fix typo
|
2019-07-23 13:58:56 -07:00 |
Eddie Hung
|
33c984a044
|
Fix spacing
|
2019-07-22 16:37:13 -07:00 |
Eddie Hung
|
068617f094
|
Pack hi and lo registers separately
|
2019-07-22 16:12:57 -07:00 |
Eddie Hung
|
4d71ab384d
|
Rename according to vendor doc TN1295
|
2019-07-22 15:08:26 -07:00 |
Eddie Hung
|
304cefbbe2
|
Pack Y register
|
2019-07-22 15:05:16 -07:00 |
Eddie Hung
|
5a14b6e1f6
|
Pack adders not just accumulators
|
2019-07-22 13:01:49 -07:00 |
Eddie Hung
|
e0720a8018
|
Restore old ffY behaviour
|
2019-07-19 22:47:08 -07:00 |
Eddie Hung
|
f9d08a5e5e
|
Cleanup
|
2019-07-19 20:25:28 -07:00 |
Eddie Hung
|
9ad11ea2cc
|
Fine tune ice40_dsp.pmg, add support for packing subsets of registers
|
2019-07-19 10:57:32 -07:00 |
Eddie Hung
|
8f0e796be1
|
Add support for ice40 signed multipliers
|
2019-07-19 10:38:13 -07:00 |
Eddie Hung
|
09411dd996
|
ice40_dsp to accept $__MUL16X16 too
|
2019-07-18 15:38:28 -07:00 |
Eddie Hung
|
802470746c
|
Check if RHS is empty first
|
2019-07-18 15:22:00 -07:00 |
Eddie Hung
|
90ac147eb2
|
Do not autoremove ffP aor muxP
|
2019-07-18 15:02:41 -07:00 |