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12432 Commits

Author SHA1 Message Date
Catherine 5d9bd0af92 Update abc. 2023-02-23 01:48:21 +00:00
github-actions[bot] 0f2d226ae9 Bump version 2023-02-21 00:17:40 +00:00
N. Engelhardt c8966722d2
Merge pull request #3403 from KrystalDelusion/mem-tests 2023-02-20 18:27:24 +01:00
KrystalDelusion f80920bd9f Genericising bug1836.ys 2023-02-21 05:23:16 +13:00
KrystalDelusion 445a801a85 bug3205.ys removed 
Made redundant by TDP test(s) in memories.ys
 2023-02-21 05:23:16 +13:00
KrystalDelusion 51c2d476c2 Removing extra `default_nettype` lines 2023-02-21 05:23:16 +13:00
KrystalDelusion 8f6a06951c Fix for sync_ram_sdp not being final module 
Explicitly declare -top in synth_intel_alm.
 2023-02-21 05:23:16 +13:00
KrystalDelusion 7f033d3c1f More tests in memlib/generate.py 
Covers most of the todo list, at least functionally.  Some minor issues with not always using hardware features.
 2023-02-21 05:23:15 +13:00
KrystalDelusion af1b9c9e07 Tests for ram_style = "huge" 
iCE40 SPRAM and Xilinx URAM
 2023-02-21 05:23:15 +13:00
KrystalDelusion de2f140c09 Testing TDP synth mapping 
New common sync_ram_tdp.
Used in ecp5 and gatemate mem*.ys.
 2023-02-21 05:23:15 +13:00
KrystalDelusion 48f4e09202 Asymmetric port ram tests with Xilinx 
Uses verilog code from User Guide 901 (2021.1)
 2023-02-21 05:23:14 +13:00
KrystalDelusion ac5fa9a838 Addings tests for #1836 and #3205 2023-02-21 05:23:14 +13:00
Dag Lem 79043cb849 Out of bounds checking for struct/union members 
Currently, only constant indices are checked.
 2023-02-19 23:25:08 +01:00
github-actions[bot] f0116330bc Bump version 2023-02-18 00:17:33 +00:00
N. Engelhardt f30b539cc2
Merge pull request #3681 from keszocze/keszocze-patch-dsp48e1-init-dreg 2023-02-17 18:40:22 +01:00
Oliver Keszöcze fc56978703
Check DREG attribute 
The DSP48E1 implementation checked the wrong attribute (i.e. CREG) to initialize the D input register. This PR fixes 3680
 2023-02-17 17:54:41 +01:00
github-actions[bot] 1cfedc90ce Bump version 2023-02-17 00:18:18 +00:00
gatecat 25e7cb3bbb fabulous: Add CLK to BRAM interface primitives 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-02-16 12:55:53 +01:00
github-actions[bot] a20804c6ed Bump version 2023-02-16 00:17:37 +00:00
Patrick Urban 2c7ba0e752 gatemate: Enable register initialization 2023-02-15 17:29:01 +01:00
Jannis Harder 1c667fab2b
Merge pull request #3672 from jix/yw-cosim-hierarchy-fixes 
sim: For yw cosim, drive parent module's signals for input ports
 2023-02-15 13:45:00 +01:00
Jannis Harder 1cedad7a68
Merge pull request #3675 from daglem/struct-item-queries 
Support for data and array queries on struct/union item expressions
 2023-02-15 13:33:34 +01:00
Jannis Harder 68480dfa19
Merge pull request #3671 from zachjs/master 
Add test for typenames using constants shadowed later on
 2023-02-15 13:04:43 +01:00
N. Engelhardt b562b54c14 dfflegalize: allow setting mince and minsrst args from scratchpad 2023-02-15 12:53:46 +01:00
Dag Lem f8219289b2 Corrected tests for data and array queries on struct/union item expressions 2023-02-15 12:36:29 +01:00
Dag Lem c1e12877f0 Support for data and array queries on struct/union item expressions 
For now, $bits, $left, $right, $low, $high, and $size are supported.
 2023-02-15 11:44:24 +01:00
Jannis Harder 53bda9de54
Merge pull request #3661 from daglem/struct-array-range-offset 
Handle range offsets in packed arrays within packed structs
 2023-02-15 11:21:56 +01:00
github-actions[bot] 59de4a0e7f Bump version 2023-02-15 00:17:48 +00:00
Jannis Harder ec94703619
Merge pull request #2995 from georgerennie/cover_precond 
chformal: Add -coverenable option
 2023-02-14 17:46:31 +01:00
Jannis Harder 85f611fb23
Merge pull request #3126 from georgerennie/equiv_make_assertions 
equiv_make: Add -make_assert option
 2023-02-14 17:15:55 +01:00
Jannis Harder b636af9751 chformal: Note about using -coverenable with the Verific frontend 2023-02-14 17:10:43 +01:00
Patrick Urban f37073050b gatemate: Update CC_PLL parameters 2023-02-14 12:02:41 +01:00
Patrick Urban 6a7d5257cd gatemate: Add CC_USR_RSTN primitive 2023-02-14 12:02:41 +01:00
Patrick Urban 4cb27b1a3a gatemate: Ensure compatibility of LVDS ports with VHDL 2023-02-14 12:02:41 +01:00
github-actions[bot] e0bc25f1af Bump version 2023-02-14 00:17:45 +00:00
Jannis Harder d2032ac6fd
Merge pull request #3669 from jix/fix-xprop-tests-yosys-call 
tests: Fix path of yosys invocation in xprop tests
 2023-02-13 17:55:36 +01:00
Miodrag Milanovic 550a5b7b6b Update license 2023-02-13 17:23:26 +01:00
Miodrag Milanovic 713b7d3e26 added support for latched output reset 2023-02-13 17:23:26 +01:00
Miodrag Milanovic 131b557727 Initial implementation of synthesizable assertions 2023-02-13 17:23:26 +01:00
Jannis Harder 55ad3fe6c7 xprop tests: Make iverilog invocation more portable 2023-02-13 16:54:11 +01:00
Jannis Harder 2a68eee5f1 xprop: Test fixes and abort on test failure 
Use `$finish(0)` to silently exit even when using recent iverlog
versions. Run `write_verilog -noexpr` before `write_verilog` as the
latter can modify the design.

This also enables checking the tests results, as xprop should be in a
state where the existing tests pass.
 2023-02-13 14:05:16 +01:00
Jannis Harder 9f20beb7df xprop: Smaller subset of tests to run by default 2023-02-13 14:02:02 +01:00
Jannis Harder 160eeab2bb verilog_backend: Do not run bwmuxmap even if in expr mode 
While bwmuxmap generates equivalent logic, it doesn't propagate x bits
in the same way, which can be relevant when writing verilog.
 2023-02-13 14:00:38 +01:00
Jannis Harder 1698202ccc sim: For yw cosim, drive parent module's signals for input ports 2023-02-13 12:26:06 +01:00
github-actions[bot] 4c334b905f Bump version 2023-02-13 00:17:46 +00:00
Dag Lem 615adc4253
Resolve package types in interfaces (#3658) 
* Resolve package types in interfaces
* Added test for resolving of package types in interfaces
 2023-02-12 18:25:39 -05:00
Zachary Snow 26a6c60478 Add test for typenames using constants shadowed later on 
This possible edge case came up while reviewing #3555. It is currently
handled correctly, but there is no clear test coverage.
 2023-02-12 17:03:37 -05:00
github-actions[bot] 5ea2c290a5 Bump version 2023-02-11 00:14:42 +00:00
Jannis Harder 6d021f04d4 tests: Fix path of yosys invocation in xprop tests 
For now xprop test failures are still expected and ignored, but without
this change, they did not even run unless the yosys build was in path.
 2023-02-10 19:17:16 +01:00
Jannis Harder f3c4e93d24
Merge pull request #3667 from jix/xprop-test-make-fix 
tests: in xprop tests, use MAKE variable if set
 2023-02-10 16:06:16 +01:00