riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
13,808 Commits 81 Branches 48 Tags 64 MiB
Commit Graph

3 Commits

Author SHA1 Message Date
Miodrag Milanovic bbf65702a1 Fix valgrind tests when using verific 2022-03-30 17:25:53 +02:00
Claire Xenia Wolf 15fb0107dc Fix "make vgtest" so it runs to the end (but now it fails ;) 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-09-23 14:54:28 +02:00
Zachary Snow 4f187d53c5 verilog: support module scope identifiers in parametric modules 2021-03-16 11:01:30 -04:00