Commit Graph

1408 Commits

Author SHA1 Message Date
Zachary Snow 4452080861 sv: check validity of package end label 2021-05-10 14:37:32 -04:00
Marcelina Kościelnicka 32a0ce9d68 blif: Use library cells' start_offset and upto for wideports.
Fixes #2729.
2021-05-08 15:50:03 +02:00
Marcelina Kościelnicka 5c1e6a0e20 opt_dff: Fix NOT gates wired in reverse. 2021-05-04 21:03:40 +02:00
Claire Xenia Wolf 8aee80040d Add default assignments to SB_LUT4
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-04-20 12:46:21 +02:00
Lofty dce037a62c quicklogic: ABC9 synthesis 2021-04-17 20:54:58 +02:00
Zachary Snow 0ccc7229c0 preproc: test coverage for #2712 2021-03-30 12:23:18 -04:00
Eddie Hung 8c5f379435
abc9: uniquify blackboxes like whiteboxes (#2695)
* abc9_ops: uniquify blackboxes too

* abc9_ops: update comment

* abc9_ops: allow bypass for param-less blackboxes

* Add tests
2021-03-29 22:02:06 -07:00
Eddie Hung 55dc5a4e4f
abc9: fix SCC issues (#2694)
* xilinx: add SCC test for DSP48E1

* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1

Have a test that checks it works through ABC9 when enabled

* abc9 to break SCCs using $__ABC9_SCC_BREAKER module

* Add test

* abc9_ops: remove refs to (* abc9_keep *) on wires

* abc9_ops: do not bypass cells in an SCC

* Add myself to CODEOWNERS for abc9*

* Fix compile

* abc9_ops: run -prep_hier before scc

* Fix tests

* Remove bug reference pending fix

* abc9: fix for -prep_hier -dff

* xaiger: restore PI handling

* abc9_ops: -prep_xaiger sigmap

* abc9_ops: -mark_scc -> -break_scc

* abc9: eliminate hard-coded abc9.box from tests

Also tidy up

* Address review
2021-03-29 22:01:57 -07:00
Marcelina Kościelnicka 4a35f244aa quicklogic: Add .gitignore file for test outputs. 2021-03-23 17:35:00 +01:00
Xiretza 92d5550a90 verilog: check entire user type stack for type definition 2021-03-21 19:35:13 -04:00
Zachary Snow 4f4e70876f sv: allow typenames as function return types 2021-03-19 12:08:43 -04:00
Lofty f4298b057a quicklogic: PolarPro 3 support
Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com>
Co-authored-by: Maciej Kurc <mkurc@antmicro.com>
Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com>
Co-authored-by: Lalit Sharma <lsharma@quicklogic.com>
Co-authored-by: kkumar23 <kkumar@quicklogic.com>
2021-03-18 13:28:16 +01:00
Marcelina Kościelnicka 8740fdf1d7 ast: Use better parameter serialization for paramod names.
Calling log_signal is problematic for several reasons:

- with recent changes, empty string is serialized as { }, which violates
  the "no spaces in IdString" rule
- the type (plain / real / signed / string) is dropped, wrongly conflating
  functionally different values and potentially introducing a subtle
  elaboration bug

Instead, use a custom simple serialization scheme.
2021-03-18 00:52:00 +01:00
gatecat cae905f551 Blackbox all whiteboxes after synthesis
This prevents issues like processes in whiteboxes triggering an error in
the JSON backend.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-17 21:07:20 +00:00
Zachary Snow f71c2dcca6 sv: carry over global typedefs from previous files
This breaks the ability to use a global typename as a standard
identifier in a subsequent input file. This is otherwise backwards
compatible, including for sources which previously included conflicting
typedefs in each input file.
2021-03-17 15:53:52 -04:00
Xiretza 092e923330 verilog: fix buf/not primitives with multiple outputs
From IEEE1364-2005, section 7.3 buf and not gates:

> These two logic gates shall have one input and one or more outputs.
> The last terminal in the terminal list shall connect to the input of the
> logic gate, and the other terminals shall connect to the outputs of
> the logic gate.

yosys does not follow this and instead interprets the first argument as
the output, the second as the input and ignores the rest.
2021-03-17 11:44:03 -04:00
gatecat dd6d34f461 blackbox: Include whiteboxed modules
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-17 13:58:04 +00:00
Zachary Snow 4f187d53c5 verilog: support module scope identifiers in parametric modules 2021-03-16 11:01:30 -04:00
Marcelina Kościelnicka a55bf6375b proc_arst: Add special-casing of clock signal in conditionals.
The already-existing special case for conditionals on clock has been
remade as follows:

- now triggered for the last remaining edge trigger after all others
  have been converted to async reset, not just when there is only one
  sync rule in the first place
- does not require all contained assignments to be constant, as opposed
  to a reset conditional — merely const-folds the condition

In addition, the code has been refactored a bit; as a bonus, the
priority order of async resets found is now preserved in resulting sync
rule ordering (though this is not yet respected by proc_dff).

Fixes #2656.
2021-03-15 17:17:29 +01:00
Marcelina Kościelnicka 3af871f969 opt_clean: Remove init attribute bits together with removed DFFs.
Fixes #2546.
2021-03-15 17:16:53 +01:00
Marcelina Kościelnicka f965b3fa54 rtlil: Disallow 0-width chunks in SigSpec.
Among other problems, this also fixes equality comparisons between
SigSpec by enforcing a canonical form.

Also fix another minor issue with possible non-canonical SigSpec.

Fixes #2623.
2021-03-15 17:16:24 +01:00
Zachary Snow 640b9927fa sv: allow globals in one file to depend on globals in another
This defers the simplification of globals so that globals in one file
may depend on globals in other files. Adds a simplify() call downstream
because globals are appended at the end.
2021-03-12 11:22:41 -05:00
Zachary Snow cb9f3b6abf verilog: disallow overriding global parameters
It was previously possible to override global parameters on a
per-instance basis. This could be dangerous when using positional
parameter bindings, hiding oversupplied parameters.
2021-03-11 12:36:51 -05:00
Marcelina Kościelnicka a3528649c8 memory_dff: Remove now-useless write port handling. 2021-03-08 20:16:29 +01:00
Marcelina Kościelnicka 760284033d proc_dff: Fix emitted FF when a register is not assigned in async reset
Fixes #2619.
2021-03-08 17:01:43 +01:00
Marcelina Kościelnicka d555454969 tests/bram: Do not generate write address collisions.
These have no defined semantics, making the tests non-deterministic.
2021-03-08 16:53:03 +01:00
whitequark 9bb839c613
Merge pull request #2626 from zachjs/param-no-default
sv: support for parameters without default values
2021-03-07 05:48:03 -08:00
whitequark 72ae15c77c
Merge pull request #2632 from zachjs/width-limit
verilog: impose limit on maximum expression width
2021-03-07 03:45:41 -08:00
Zachary Snow b1a8e73a60 sv: fix some edge cases for unbased unsized literals
- Fix explicit size cast of unbased unsized literals
- Fix unbased unsized literal bound directly to port
- Output `is_unsized` flag in `dumpAst`
2021-03-06 15:20:34 -05:00
Zachary Snow c18ddbcd82 verilog: impose limit on maximum expression width
Designs with unreasonably wide expressions would previously get stuck
allocating memory forever.
2021-03-04 15:20:52 -05:00
Zachary Snow d738b2c127 sv: support for parameters without default values
- Modules with a parameter without a default value will be automatically
  deferred until the hierarchy pass
- Allows for parameters without defaults as module items, rather than
  just int the `parameter_port_list`, despite being forbidden in the LRM
- Check for parameters without defaults that haven't been overriden
- Add location info to parameter/localparam declarations
2021-03-02 10:43:53 -05:00
Zachary Snow 10a6bc9b81 verilog: fix sizing of ports with int types in module headers
Declaring the ports as standard module items already worked as expected.
This adds a missing usage of `checkRange()` so that headers such as
`module m(output integer x);` now work correctly.
2021-03-01 13:39:05 -05:00
Zachary Snow 1ec5994100 verilog: fix handling of nested ifdef directives
- track depth so we know whether to consider higher-level elsifs
- error on unmatched endif/elsif/else
2021-03-01 12:28:33 -05:00
Zachary Snow b6904a8e53 Set aside extraneous tests in simple_abc9 test suite
New test cases on one branch may be automatically copied from simple/ to
simple_abc9/, causing failures when switching to another branch. This
updates the simple_abc9 script to set aside extraneous tests in a
non-destructive way.
2021-03-01 12:13:11 -05:00
whitequark ca5f5ffcd6
Merge pull request #2615 from zachjs/genrtlil-conflict
genrtlil: improve name conflict error messaging
2021-03-01 08:10:19 -08:00
Zachary Snow 0f5b646ab8 sv: extended support for integer types
- Standard data declarations can now use any integer type
- Parameters and localparams can now use any integer type
- Function returns types can now use any integer type
- Fix `parameter logic`, `localparam reg`, etc. to be 1 bit (previously 32 bits)
- Added longint type (64 bits)
- Unified parser source for integer type widths
2021-02-28 16:31:56 -05:00
Zachary Snow bbff844acd genrtlil: improve name conflict error messaging 2021-02-26 18:08:23 -05:00
Michael Singer d56b76bd7c Add tests for $countbits 2021-02-26 12:28:58 -05:00
TimRudy dcd9f0af23
Extend "delay" expressions to handle pair and triplet, i.e. rise, fall and turn-off (#2566) 2021-02-24 15:48:15 -05:00
Marcelina Kościelnicka b05b98521c Add tests for some common techmap files. 2021-02-24 01:07:34 +01:00
whitequark ad2960adb7
Merge pull request #2594 from zachjs/func-arg-width
verilog: fix sizing of constant args for tasks/functions
2021-02-23 21:46:16 +00:00
William D. Jones ae07298a6b machxo2: Switch to LUT4 sim model which propagates less undefined/don't care values. 2021-02-23 17:39:58 +01:00
William D. Jones 353ace5034 machxo2: Update tribuf test to reflect active-low OE. 2021-02-23 17:39:58 +01:00
William D. Jones c31b17a2e2 machxo2: Add believed-to-be-correct tribuf test. 2021-02-23 17:39:58 +01:00
William D. Jones c7aaa88f58 machxo2: Add passing fsm, mux, and shifter tests. 2021-02-23 17:39:58 +01:00
William D. Jones 453904dd00 machxo2: Add add_sub test. Fix tests to include FACADE_IO primitives. 2021-02-23 17:39:58 +01:00
William D. Jones 19b043344c machxo2: Add dffe test. 2021-02-23 17:39:58 +01:00
William D. Jones 84937e9689 machxo2: Add dff.ys test, fix another cells_map.v typo. 2021-02-23 17:39:58 +01:00
William D. Jones 9cb0bae1b2 machxo2: Add test/arch/machxo2 directory (test does not pass). 2021-02-23 17:39:58 +01:00
Marcelina Kościelnicka 4746ffd7b2 assertpmux: Fix crash on unused $pmux output.
Fixes #2595.
2021-02-22 23:30:28 +01:00