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11529 Commits

Author SHA1 Message Date
clairexen 7e2fc2eaeb
Merge pull request #2378 from udif/pr_dollar_high_low 
Added $high(), $low(), $left(), $right()
 2020-10-01 18:17:36 +02:00
clairexen 2412e75495
Merge pull request #2380 from Xiretza/parallel-tests 
Clean up and parallelize testsuite
 2020-10-01 18:12:31 +02:00
David Shah c4bfbecca6 Update .gitignore 
Signed-off-by: David Shah <dave@ds0.me>
 2020-10-01 15:53:14 +01:00
clairexen 492bd3c4c2
Merge pull request #2395 from YosysHQ/sha1_if_contain_spaces 
Use sha1 for parameter list in case if they contain spaces
 2020-10-01 14:32:43 +02:00
Yosys Bot f9ed9786bf Bump version 2020-10-01 00:10:08 +00:00
Miodrag Milanovic a44c5df259 use sha1 for parameter list in case if they contain spaces 2020-09-30 09:16:59 +02:00
Miodrag Milanovic 9e00f3f141 Fixed installation dir override for Python scripts 2020-09-30 07:47:36 +02:00
Yosys Bot 5a3ac39f5f Bump version 2020-09-30 00:10:09 +00:00
clairexen 7b9a93aa2e
Merge pull request #2393 from nakengelhardt/no_const_sensitivity 
write_verilog: emit intermediate wire for constant values in sensitivity list
 2020-09-29 17:31:01 +02:00
clairexen e8c9e541a7
Merge pull request #2392 from YosysHQ/mmicko/hierarchy_fix 
Validate parameters only when they are used
 2020-09-29 17:21:08 +02:00
Yosys Bot dfc43c38f8 Bump version 2020-09-29 00:10:05 +00:00
N. Engelhardt dc4a617694 add tests 2020-09-28 18:16:08 +02:00
N. Engelhardt 8f1d53e66f write_verilog: emit intermediate wire for constant values in sensitivity list 2020-09-28 18:11:18 +02:00
Miodrag Milanović 08eb0821c9
Merge pull request #2386 from btut/fix/pyinstallpath 
Fixed python installation path
 2020-09-28 12:54:38 +02:00
N. Engelhardt bddd56d0c6
Merge pull request #2387 from btut/fix/pythonWrappersCXXFlags 
Use CXXFLAGS to enable pyosys specific code before generating wrappers
 2020-09-28 12:45:52 +02:00
Xiretza bed14241ef
tests: add gitignores for auto-generated makefiles 2020-09-26 16:28:24 +02:00
Benedikt Tutzer 4892ec853b Use CXXFLAGS to enable pyosys specific code before generating wrappers 
The .pyh files were generated without the CXXFLAGS. This meant that code
marked by the WITH_PYTHON flag was excluded. This is fixed by adding the
flag in the rule for .pyh files.
 2020-09-25 12:57:46 +02:00
Miodrag Milanovic 412332fdb3 Validate parameters only when they are used 2020-09-25 11:40:37 +02:00
Benedikt Tutzer 9266d20afc Fixed python installation path 
The path where python expects it's libraries seems to change from
operating system to operating system, but can be querried from the site
package.
 2020-09-25 11:21:16 +02:00
Yosys Bot cd8b2ed4e6 Bump version 2020-09-24 00:10:06 +00:00
Eddie Hung de79978372
xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325) 
* xilinx: eliminate SCCs from DSP48E1 model

* xilinx: add SCC test for DSP48E1

* Update techlibs/xilinx/cells_sim.v

* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1

Have a test that checks it works through ABC9 when enabled
 2020-09-23 09:15:24 -07:00
Miodrag Milanović 81348d2dce
Merge pull request #2384 from nakengelhardt/fix_2383 
switch argument order to work with macOS getopt
 2020-09-23 13:04:54 +02:00
N. Engelhardt 370243426e switch argument order to work with macOS getopt 2020-09-23 12:48:26 +02:00
Yosys Bot 8fbb517118 Bump version 2020-09-22 00:10:15 +00:00
N. Engelhardt ed5790382a
Merge pull request #2372 from nakengelhardt/name_is_public 
add IdString::isPublic()
 2020-09-21 15:18:06 +02:00
Xiretza e38b830cbb
tests/simple: remove "nullglob" shopt 2020-09-21 15:07:02 +02:00
Xiretza 01260344d3
tests: Parallelize 2020-09-21 15:07:02 +02:00
Xiretza acd47bbd52
tests: Centralize test collection and Makefile generation 2020-09-21 15:07:02 +02:00
Yosys Bot c6ff947f6b Bump version 2020-09-19 00:10:08 +00:00
clairexen e1ae20d542
Merge pull request #2381 from YosysHQ/unsupported 
Better error for unsupported SVA sequence
 2020-09-18 17:43:30 +02:00
Miodrag Milanovic 44705102b5 Better error for unsupported SVA sequence 2020-09-18 17:08:00 +02:00
Yosys Bot 7affef7c17 Bump version 2020-09-18 00:10:08 +00:00
clairexen f176bd7778
Merge pull request #2329 from antmicro/arrays-fix-multirange-size 
Rewrite multirange arrays sizes [n] as [n-1:0]
 2020-09-17 18:27:05 +02:00
clairexen 9e937961dc
Merge pull request #2330 from antmicro/arrays-fix-multirange-access 
Fix unsupported subarray access detection
 2020-09-17 18:21:53 +02:00
Udi Finkelstein 7ed0e23e19 We can now handle array slices (e.g. $size(x[1]) etc. ) 2020-09-17 00:55:17 +03:00
Udi Finkelstein 6de7ba02e3 Fixed comments, removed debug message 2020-09-16 10:57:06 +03:00
Udi Finkelstein b548722bee Added $high(), $low(), $left(), $right() 2020-09-15 20:49:52 +03:00
N. Engelhardt 3238190797 use the new isPublic() in a few places 2020-09-14 12:43:18 +02:00
Yosys Bot 859e52af59 Bump version 2020-09-11 00:10:06 +00:00
Miodrag Milanović da3002e580
Merge pull request #2369 from Xiretza/gitignores 
Add missing gitignores for test artifacts
 2020-09-10 13:37:49 +02:00
Yosys Bot 474cd02eb5 Bump version 2020-09-04 00:10:06 +00:00
N. Engelhardt 4af04be0b7 add IdString::isPublic() 2020-09-03 17:37:58 +02:00
whitequark c66d1dfad1
Merge pull request #2371 from whitequark/cxxrtl-debug-info 
cxxrtl: expose port direction and driver kind in debug information
 2020-09-03 09:45:40 +00:00
Yosys Bot d963bdb484 Bump version 2020-09-03 00:10:06 +00:00
whitequark 691418e13a cxxrtl: expose driver kind in debug information. 
This can be useful to determine whether the wire should be a part of
a design checkpoint, whether it can be used to override design state,
and whether driving it may cause a conflict.
 2020-09-02 18:00:12 +00:00
whitequark c7b2f07edf cxxrtl: improve handling of FFs with async inputs (other than CLK). 
Before this commit, the meaning of "sync def" included some flip-flop
cells but not others. There was no actual reason for this; it was
just poorly defined.

After this commit, a "sync def" means that a wire holds design state
because it is connected directly to a flip-flop output, and may never
be unbuffered. This is not affected by presence of async inputs.
 2020-09-02 18:00:12 +00:00
whitequark b025ee0aa6 cxxrtl: expose port direction in debug information. 
This can be useful to distinguish e.g. a combinatorially driven wire
with type `CXXRTL_VALUE` from a module input with the same type, as
well as general introspection.
 2020-09-02 17:19:11 +00:00
whitequark 8d6e5c6391 cxxrtl: fix typo in comment. NFC. 2020-09-02 15:23:49 +00:00
whitequark d880f6eda2 cxxrtl: fix inaccuracy in CXXRTL_ALIAS documentation. NFC. 
Nodes driven by a constant value have type CXXRTL_VALUE and their
`next` pointer set to NULL. (This is already documented.)
 2020-09-02 15:23:47 +00:00
Miodrag Milanovic 3f27a4ea68 Use latest verific 2020-09-02 10:22:25 +02:00