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2,236 Commits 81 Branches 48 Tags 64 MiB
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182 Commits

Author SHA1 Message Date
Clifford Wolf 49859393bb Improved attributes API and handling of "src" attributes 2015-04-24 22:04:05 +02:00
Clifford Wolf a1c62b79d5 Avoid parameter values with size 0 ($mem cells) 2015-04-05 18:04:19 +02:00
Clifford Wolf 706631225e Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types 2015-04-05 09:45:14 +02:00
Clifford Wolf b005eedf36 Added $assume cell type 2015-02-26 18:04:10 +01:00
Clifford Wolf dcf2e24240 Added $meminit support to "memory" command 2015-02-14 12:55:03 +01:00
Clifford Wolf 910556560f Added $meminit cell type 2015-02-14 10:23:03 +01:00
Clifford Wolf 05d4223fb6 Added SigSpec::has_const() 2015-02-08 00:01:51 +01:00
Clifford Wolf dce1fae777 Added cell->known(), cell->input(portname), cell->output(portname) 2015-02-07 11:40:19 +01:00
Clifford Wolf 5b41470e15 Skip blackbox modules in design->selected_modules() 2015-02-03 23:12:23 +01:00
Clifford Wolf f80f5b721d Added "equiv_make -blacklist <file> -encfile <file>" 2015-01-31 12:08:20 +01:00
Clifford Wolf 43951099cf Added dict/pool.sort() 2015-01-24 00:13:27 +01:00
Clifford Wolf abf8398216 Progress in equiv_simple 2015-01-21 23:59:58 +00:00
Clifford Wolf 76c5d863c5 Added equiv_make command 2015-01-19 13:59:08 +01:00
Clifford Wolf e13a45ae61 Added $equiv cell type 2015-01-19 11:55:05 +01:00
Clifford Wolf b32ba6f568 Optimizing no-op cell->setPort() 2015-01-17 12:04:40 +01:00
Clifford Wolf e62d838bd4 Removed SigSpec::extend_xx() api 2015-01-01 11:41:52 +01:00
Clifford Wolf 0675098733 added hashlib::mkhash_init 2014-12-30 18:51:24 +01:00
Clifford Wolf ecd64182c5 Added "yosys -X" 2014-12-29 13:33:33 +01:00
Clifford Wolf a2226e5307 Added mkhash_xorshift() 2014-12-29 00:12:36 +01:00
Clifford Wolf 8773fd5897 Added memhasher (yosys -M) 2014-12-28 21:27:51 +01:00
Clifford Wolf f3a97b75c7 Fixed performance bug in object hashing 2014-12-28 19:03:18 +01:00
Clifford Wolf 3da46d3437 Renamed hashmap.h to hashlib.h, some related improvements 2014-12-28 17:51:16 +01:00
Clifford Wolf 6c8b0a5fd1 More dict/pool related changes 2014-12-27 12:02:57 +01:00
Clifford Wolf 66ab88d7b0 More hashtable finetuning 2014-12-27 03:04:50 +01:00
Clifford Wolf ec4751e55c Replaced std::unordered_set (nodict) with Yosys::pool 2014-12-26 21:59:41 +01:00
Clifford Wolf 9e6fb0b02c Replaced std::unordered_map as implementation for Yosys::dict 2014-12-26 21:35:22 +01:00
Clifford Wolf e52d1f9b9a Added new_dict (hashmap.h) and re-enabled code coverage counters 2014-12-26 19:28:52 +01:00
Clifford Wolf a6c96b986b Added Yosys::{dict,nodict,vector} container types 2014-12-26 10:53:21 +01:00
Clifford Wolf edb3c9d0c4 Renamed extend() to extend_xx(), changed most users to extend_u0() 2014-12-24 09:51:17 +01:00
Clifford Wolf 7775d2806f Added IdString::destruct_guard hack 2014-12-11 21:46:36 +01:00
Clifford Wolf 7d6e586df8 Added bool constructors to SigBit and SigSpec 2014-12-08 15:08:02 +01:00
Clifford Wolf bca2442c67 Added module->addDffe() and module->addDffeGate() 2014-12-08 14:59:38 +01:00
Clifford Wolf f1764b4fe9 Added $dffe cell type 2014-12-08 10:50:19 +01:00
Clifford Wolf fad9cec47b Added $_DFFE_??_ cell types 2014-12-08 10:43:38 +01:00
Clifford Wolf fe829bdbdc Added log_warning() API 2014-11-09 10:44:23 +01:00
Clifford Wolf 70b2efdb05 Added support for $readmemh/$readmemb 2014-10-26 20:33:10 +01:00
Clifford Wolf 84ffe04075 Fixed various VS warnings 2014-10-18 15:20:38 +02:00
Clifford Wolf 468ae92374 Various win32 / vs build fixes 2014-10-17 14:01:47 +02:00
Clifford Wolf 3be5fa053f Fixed RTLIL::SigSpec::parse() for out-of-range bit- and part-selects 2014-10-16 00:54:14 +02:00
Clifford Wolf 4569a747f8 Renamed SIZE() to GetSize() because of name collision on Win32 2014-10-10 17:07:24 +02:00
Clifford Wolf c3e779a65f Added $_BUF_ cell type 2014-10-03 10:12:28 +02:00
Clifford Wolf 00964f2f61 Initialize RTLIL::Const from std::vector<bool> 2014-09-19 15:50:55 +02:00
Clifford Wolf 2442eb3832 Fixed monitor notifications for removed cell 2014-09-14 17:04:39 +02:00
Clifford Wolf af0c8873bb Added $lcu cell type 2014-09-08 13:31:04 +02:00
Clifford Wolf d46bac3305 Added "$fa" cell type 2014-09-08 12:15:39 +02:00
Clifford Wolf b847ec8a0b Added $macc cell type 2014-09-06 15:47:46 +02:00
Clifford Wolf 8927aa6148 Removed $bu0 cell type 2014-09-04 02:07:52 +02:00
Clifford Wolf da360771a1 Create a default selection stack in RTLIL::Design::Design() 2014-09-02 22:49:24 +02:00
Clifford Wolf e07698818d Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::data 2014-09-01 11:36:02 +02:00
Clifford Wolf 8649b57b6f Added $lut support in test_cell, techmap, satgen 2014-08-31 17:43:31 +02:00