Clifford Wolf
|
8a1d6ccf0c
|
Add DFSM generator to verific SVA importer
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-02-28 15:05:33 +01:00 |
Clifford Wolf
|
15902d495f
|
Continue refactoring of Verific SVA importer code
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-02-28 11:45:04 +01:00 |
Clifford Wolf
|
25e33d7ab8
|
Major redesign of Verific SVA importer
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-02-27 20:33:15 +01:00 |
Clifford Wolf
|
b6fbeb0969
|
Add handling of verific OPER_REDUCE_NOR
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-02-26 15:26:01 +01:00 |
Clifford Wolf
|
2aeb4d4e12
|
Add handling of verific OPER_SELECTOR and OPER_WIDE_SELECTOR
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-02-26 15:20:27 +01:00 |
Clifford Wolf
|
9cd9f5fc78
|
Add handling of verific OPER_NTO1MUX and OPER_WIDE_NTO1MUX
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-02-26 15:02:03 +01:00 |
Clifford Wolf
|
d1cb5150aa
|
Add "SVA syntax cheat sheet" comment to verificsva.cc
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-02-26 14:31:58 +01:00 |
Clifford Wolf
|
2521ed305e
|
Add Verific SVA support for ranges in repetition operator
|
2018-02-22 12:37:30 +01:00 |
Clifford Wolf
|
6d12c83d36
|
Add support for SVA throughout via Verific
|
2018-02-21 13:09:47 +01:00 |
Clifford Wolf
|
5c6247dfa6
|
Add support for SVA sequence concatenation ranges via verific
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-02-18 16:35:06 +01:00 |
Clifford Wolf
|
9d963cd29c
|
Add support for SVA until statements via Verific
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-02-18 14:57:52 +01:00 |
Clifford Wolf
|
5fa2aa2741
|
Move Verific SVA importer to extra C++ source file
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-02-18 13:52:49 +01:00 |
Clifford Wolf
|
c4bf34f6ce
|
Merge Verific SVA preprocessor and SVA importer
|
2018-02-18 13:28:08 +01:00 |
Clifford Wolf
|
bc8ab3ab44
|
Fix verific PRIM_SVA_AT handling in properties with PRIM_SVA_DISABLE_IFF
|
2018-02-15 15:26:37 +01:00 |
Clifford Wolf
|
6c00e064e2
|
Fix single-bit $stable handling in verific front-end
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-02-01 12:51:49 +01:00 |
Clifford Wolf
|
9af40faa0b
|
Add Verific attribute handling for assert/assume/cover/live/fair cells
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-01-31 19:06:51 +01:00 |
Clifford Wolf
|
675f53abbb
|
Fix permissions on verific vdb files
|
2018-01-28 18:52:01 +01:00 |
Clifford Wolf
|
1d8161b432
|
Fixed handling of synchronous and asynchronous assertion/assumption/cover in verific bindings
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-01-23 17:42:40 +01:00 |
Clifford Wolf
|
ba90e08398
|
Add support for Verific PRIM_SVA_NOT properties
|
2017-12-10 01:10:03 +01:00 |
Clifford Wolf
|
e4a4c0e10c
|
Add Verific OPER_SVA_STABLE support
|
2017-12-10 00:59:44 +01:00 |
Clifford Wolf
|
27916105a9
|
Refactoring Verific SVA rewriter
|
2017-12-10 00:26:26 +01:00 |
Clifford Wolf
|
0a31a0b3ae
|
Remove all PSL support code from verific.cc
|
2017-10-20 13:14:04 +02:00 |
Clifford Wolf
|
1954c78ea7
|
Add "verific -vlog-libdir"
|
2017-10-13 20:23:19 +02:00 |
Clifford Wolf
|
e7a3c47cc7
|
Add "verific -vlog-incdir" and "verific -vlog-define"
|
2017-10-13 20:12:51 +02:00 |
Clifford Wolf
|
05068af880
|
Update Verific README
|
2017-10-13 17:11:53 +02:00 |
Clifford Wolf
|
bc5cc4e103
|
Add Verific fairness/liveness support
|
2017-10-12 12:00:09 +02:00 |
Clifford Wolf
|
c10e96c9ec
|
Start work on pre-processor for Verific SVA properties
|
2017-10-10 15:16:39 +02:00 |
Clifford Wolf
|
fc3378916d
|
Improve handling of Verific errors
|
2017-10-05 14:38:32 +02:00 |
Clifford Wolf
|
ee56a887b6
|
Improve Verific error handling, check VHDL static asserts
|
2017-10-04 18:56:28 +02:00 |
Clifford Wolf
|
b92ff2706e
|
Fix nasty bug in Verific bindings
|
2017-10-04 17:23:42 +02:00 |
Clifford Wolf
|
15073790bf
|
Add merging of "past FFs" to verific importer
|
2017-07-29 00:10:38 +02:00 |
Clifford Wolf
|
d4b9602cbd
|
Add minimal support for PSL in VHDL via Verific
|
2017-07-28 17:39:49 +02:00 |
Clifford Wolf
|
5a828fff34
|
Improve Verific HDL language options
|
2017-07-28 15:32:54 +02:00 |
Clifford Wolf
|
acd6cfaf67
|
Fix handling of non-user-declared Verific netbus
|
2017-07-28 11:31:27 +02:00 |
Clifford Wolf
|
c1cfca8f54
|
Improve Verific SVA importer
|
2017-07-27 14:05:09 +02:00 |
Clifford Wolf
|
2336d5508b
|
Add log_warning_noprefix() API, Use for Verific warnings and errors
|
2017-07-27 12:17:04 +02:00 |
Clifford Wolf
|
d9641621d9
|
Add "verific -import -n" and "verific -import -nosva"
|
2017-07-27 11:54:45 +02:00 |
Clifford Wolf
|
90d8329f64
|
Improve Verific SVA import: negedge and $past
|
2017-07-27 11:40:07 +02:00 |
Clifford Wolf
|
147ff96ba3
|
Improve Verific SVA importer
|
2017-07-27 10:39:39 +02:00 |
Clifford Wolf
|
530040ba6f
|
Improve Verific bindings (mostly related to SVA)
|
2017-07-26 18:00:01 +02:00 |
Clifford Wolf
|
abd3b4e8e7
|
Improve "help verific" message
|
2017-07-25 15:13:22 +02:00 |
Clifford Wolf
|
6dbe1d4c92
|
Add "verific -extnets"
|
2017-07-25 14:53:11 +02:00 |
Clifford Wolf
|
c97c92e4ec
|
Improve "verific -all" handling
|
2017-07-25 13:33:25 +02:00 |
Clifford Wolf
|
41be530c4e
|
Add "verific -import -d <dump_file"
|
2017-07-24 13:57:16 +02:00 |
Clifford Wolf
|
92d3aad670
|
Add "verific -import -flatten" and "verific -import -v"
|
2017-07-24 11:29:06 +02:00 |
Clifford Wolf
|
5be535517c
|
Add "verific -import -k"
|
2017-07-22 16:16:44 +02:00 |
Clifford Wolf
|
2785aaffeb
|
Improve docs for verific bindings, add simply sby example
|
2017-07-22 11:58:51 +02:00 |
Clifford Wolf
|
28039c3063
|
Add Verific Release information to log
|
2017-07-04 20:01:30 +02:00 |
Clifford Wolf
|
cdb6ceb8c6
|
Add support for verific mem initialization
|
2017-02-11 15:57:36 +01:00 |
Clifford Wolf
|
c449f4b86f
|
Fix another stupid bug in the same line
|
2017-02-11 11:47:51 +01:00 |
Clifford Wolf
|
fa4a7efe15
|
Add verific support for initialized variables
|
2017-02-11 11:40:18 +01:00 |
Clifford Wolf
|
0b7aac645c
|
Improve handling of Verific warnings and error messages
|
2017-02-11 11:39:50 +01:00 |
Clifford Wolf
|
eb7b18e897
|
Fix extremely stupid typo
|
2017-02-11 11:09:07 +01:00 |
Clifford Wolf
|
2ca8d483dd
|
Add "rand" and "rand const" verific support
|
2017-02-09 12:53:46 +01:00 |
Clifford Wolf
|
1d1f56a361
|
Add PSL parser mode to verific front-end
|
2017-02-08 10:40:33 +01:00 |
Clifford Wolf
|
3928482a3c
|
Add $cover cell type and SVA cover() support
|
2017-02-04 14:14:26 +01:00 |
Clifford Wolf
|
911c44d164
|
Add assert/assume support to verific front-end
|
2017-02-04 13:36:00 +01:00 |
Clifford Wolf
|
0bc95f1e04
|
Added "yosys -D" feature
|
2016-04-21 23:28:37 +02:00 |
Clifford Wolf
|
7bd329afa0
|
Support for more Verific primitives (patch I got per email)
|
2016-02-13 08:19:30 +01:00 |
Clifford Wolf
|
6a27cbe5b1
|
Bugfix in Verific front-end
|
2016-02-03 08:59:57 +01:00 |
Clifford Wolf
|
4a3e1ded1e
|
Updated verific build instructions
|
2016-02-02 19:50:17 +01:00 |
Clifford Wolf
|
ba407da187
|
Added addBufGate module method
|
2016-02-02 11:26:07 +01:00 |
Clifford Wolf
|
ab2d8e5c8c
|
Added PRIM_DLATCHRS support to verific front-end
|
2015-11-24 12:16:19 +01:00 |
Clifford Wolf
|
415e0a1b90
|
Fixed performance bug in Verific importer
|
2015-11-16 12:38:56 +01:00 |
Clifford Wolf
|
b18f3a2974
|
Changes for Verific 3.16_484_32_151112
|
2015-11-12 19:28:14 +01:00 |
Clifford Wolf
|
207736b4ee
|
Import more std:: stuff into Yosys namespace
|
2015-10-25 19:30:49 +01:00 |
Clifford Wolf
|
924d9d6e86
|
Added read-enable to memory model
|
2015-09-25 12:23:11 +02:00 |
Clifford Wolf
|
84bf862f7c
|
Spell check (by Larry Doolittle)
|
2015-08-14 10:56:05 +02:00 |
Clifford Wolf
|
6c84341f22
|
Fixed trailing whitespaces
|
2015-07-02 11:14:30 +02:00 |
Clifford Wolf
|
61512b6f41
|
Verific build fixes
|
2015-05-17 08:19:52 +02:00 |
Clifford Wolf
|
fe829bdbdc
|
Added log_warning() API
|
2014-11-09 10:44:23 +01:00 |
Clifford Wolf
|
acf010d30d
|
Added "ENABLE_PLUGINS := 0" to verific amd64 build instructions
|
2014-11-08 11:38:44 +01:00 |
William Speirs
|
31267a1ae8
|
Header changes so it will compile on VS
|
2014-10-17 11:41:36 +02:00 |
Clifford Wolf
|
4569a747f8
|
Renamed SIZE() to GetSize() because of name collision on Win32
|
2014-10-10 17:07:24 +02:00 |
Ruben Undheim
|
79cbf9067c
|
Corrected spelling mistakes found by lintian
|
2014-09-06 08:47:06 +02:00 |
Clifford Wolf
|
7f734ecc09
|
Added module->uniquify()
|
2014-08-16 23:50:36 +02:00 |
Clifford Wolf
|
f092b50148
|
Renamed $_INV_ cell type to $_NOT_
|
2014-08-15 14:11:40 +02:00 |
Clifford Wolf
|
593264e9ed
|
Fixed building verific bindings
|
2014-08-12 15:21:06 +02:00 |
Clifford Wolf
|
c6fd82c70b
|
Fixed build of verific bindings
|
2014-07-31 16:45:23 +02:00 |
Clifford Wolf
|
e6d33513a5
|
Added module->design and cell->module, wire->module pointers
|
2014-07-31 14:11:39 +02:00 |
Clifford Wolf
|
1cb25c05b3
|
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
|
2014-07-31 13:19:47 +02:00 |
Clifford Wolf
|
7bd2d1064f
|
Using log_assert() instead of assert()
|
2014-07-28 11:27:48 +02:00 |
Clifford Wolf
|
7661ded8dd
|
Fixed verific bindings for new RTLIL api
|
2014-07-27 12:00:28 +02:00 |
Clifford Wolf
|
1488bc0c4f
|
Updated verific build/test instructions
|
2014-07-25 12:16:03 +02:00 |
Clifford Wolf
|
375aa71dfe
|
Various fixes in Verific frontend for new RTLIL API
|
2014-07-23 21:35:01 +02:00 |
Clifford Wolf
|
a3b9692a68
|
Fixed mapping of Verific WIDE_DFFRS operator
|
2014-03-20 13:40:01 +01:00 |
Clifford Wolf
|
470c2455e4
|
Fixed mapping of Verific FADD primitive with unconnected outputs
|
2014-03-20 13:26:52 +01:00 |
Clifford Wolf
|
cdf1257565
|
Progress in Verific bindings
|
2014-03-17 14:43:16 +01:00 |
Clifford Wolf
|
0b0dcfda7d
|
Progress in Verific bindings
|
2014-03-17 02:43:53 +01:00 |
Clifford Wolf
|
a67cd2d4a2
|
Progress in Verific bindings
|
2014-03-17 01:56:00 +01:00 |
Clifford Wolf
|
acda74c12c
|
Added support for memories to verific bindings
|
2014-03-16 17:05:05 +01:00 |
Clifford Wolf
|
7545510edc
|
Use Verific Net::{IsGnd,IsPwr} API in Verific bindings
|
2014-03-16 16:06:03 +01:00 |
Clifford Wolf
|
0ebee4c8e7
|
Progress in Verific bindings
|
2014-03-15 22:51:12 +01:00 |
Clifford Wolf
|
fc2c821407
|
Progress in Verific bindings
|
2014-03-15 15:31:54 +01:00 |
Clifford Wolf
|
1d00ad9d4d
|
Progress in Verific bindings
|
2014-03-15 14:36:11 +01:00 |
Clifford Wolf
|
e37d672ae7
|
Progress in Verific bindings
|
2014-03-14 16:40:25 +01:00 |
Clifford Wolf
|
0ac915a757
|
Progress in Verific bindings
|
2014-03-14 11:46:13 +01:00 |
Clifford Wolf
|
9a1accf692
|
Progress in Verific bindings
|
2014-03-13 18:21:00 +01:00 |
Clifford Wolf
|
6a53bc7b27
|
Copy Verific vdbs files to Yosys "share" data directory
|
2014-03-13 17:34:31 +01:00 |
Clifford Wolf
|
7a1ac11203
|
Added test_navre.ys for verific frontend
|
2014-03-13 13:12:06 +01:00 |
Clifford Wolf
|
5a15539c9b
|
Improved verific command (added support for some operators)
|
2014-03-10 12:06:57 +01:00 |
Clifford Wolf
|
c71791a1ff
|
Improvements in verific command
|
2014-03-10 03:03:08 +01:00 |
Clifford Wolf
|
8d06f9f2fe
|
Added "verific" command
|
2014-03-09 20:40:04 +01:00 |