Jeff Wang
6320f2692b
separate out enum_item/param implementation when they should be different
2020-02-17 04:42:30 -05:00
whitequark
c34d7b13f4
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT.
...
Before this commit, every initial assignment to a memory generated
two wires and four assigns in a process. For unknown reasons (I did
not investigate), large amounts of assigns cause quadratic slowdown
later in the AST frontend, in processAst/removeSignalFromCaseTree.
As a consequence, common and reasonable Verilog code, such as:
reg [`WIDTH:0] mem [0:`DEPTH];
integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0;
took extremely long time to be processed; around 80 s for a 8-wide,
8192-deep memory.
After this commit, initial assignments where address and/or data are
constant (after `generate`) do not incur the cost of intermediate
wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant.
This results in speedups of orders of magnitude for common memory
sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep
memory, and only 5.8 s to process a 8-wide, 131072-deep one.
As a bonus, this change also results in nontrivial speedups later
in the synthesis pipeline, since pass sequencing issues meant that
all of these intermediate wires were subject to transformations such
as width reduction, even though they existed solely to be constant
folded away in `memory_collect`.
2020-02-07 00:41:54 +00:00
Rodrigo Alejandro Melo
da485dc007
Modified $readmem[hb] to use '\' or '/' according the OS
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Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
2020-02-06 10:10:29 -03:00
Eddie Hung
fc33287bc1
verilog: instead of modifying localparam size, extend init constant expr
2020-02-05 17:19:42 -08:00
Rodrigo Alejandro Melo
313a425bd5
Merge branch 'master' of https://github.com/YosysHQ/yosys
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Solved a conflict into the CHANGELOG
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
2020-02-03 10:56:41 -03:00
Rodrigo Alejandro Melo
71f3afb9a2
Replaced strlen by GetSize into simplify.cc
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As recommended in CodingReadme.
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
2020-02-03 10:44:09 -03:00
Rodrigo Alejandro Melo
b4c30cfc8d
Fixed a bug in the new feature of $readmem[hb] when an empty string is provided
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Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-02-01 17:03:56 -03:00
Rodrigo Alejandro Melo
d74b9604e3
Modified the new search for files of $readmem[hb] to be backward compatible
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Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-01-31 22:10:51 -03:00
Rodrigo Alejandro Melo
7b3fe404ab
$readmem[hb] file inclusion is now relative to the Verilog file
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Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-01-31 18:20:22 -03:00
David Shah
22c967e35e
ast: Add support for $sformatf system function
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Signed-off-by: David Shah <dave@ds0.me>
2020-01-19 21:20:17 +00:00
Jeff Wang
98c6bd7630
fix bug introduced by not taking all of PeterCrozier's changes in 16ea4ea6
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The if(str == node->str) is in fact necessary (otherwise causes generate
for in Multiplier_2D in tests/simple/multiplier.v to fail with error
message "Right hand side of 3rd expression of generate for-loop is not
constant!"). Note: in PeterCrozier's implementation, the break only
breaks out of the switch-case, not the outer for loop.
2020-01-17 02:07:42 -05:00
Jeff Wang
549deb6373
fix enum in generate blocks
2020-01-16 18:13:30 -05:00
Jeff Wang
41a0a93dcc
allow enums to be declared at toplevel scope
2020-01-16 18:13:14 -05:00
Jeff Wang
16ea4ea61a
partial rebase of PeterCrozier's enum work onto current master
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I tried to keep only the enum-related changes, and minimize the diff. (The
original commit also had a lot of work done to get typedefs working, but yosys
has diverged quite a bit since the 2018-03-09 commit, with a new typedef
implementation.) I did not include the import related changes either.
Original commit:
"Initial implementation of enum, typedef, import. Still a WIP."
881833aa73
2020-01-16 13:51:47 -05:00
Eddie Hung
1ac1697e15
Stray log_dump
2019-12-11 16:59:00 -08:00
Eddie Hung
af36943cb9
Preserve size of $genval$-s in for loops
2019-12-11 16:52:37 -08:00
David Shah
e46e8753c8
frontends/ast: code style
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:55:43 +01:00
David Shah
5501d9090a
sv: Fix typedefs in blocks
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:45 +01:00
David Shah
af25585170
sv: Add support for memories of a typedef
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
David Shah
30d2326030
sv: Add support for memory typedefs
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
David Shah
e70e4afb60
sv: Fix typedefs in packages
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
David Shah
c962951612
sv: Fix typedef parameters
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
David Shah
f6b5e47e40
sv: Switch parser to glr, prep for typedef
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
Clifford Wolf
25b08b1afd
Fix handling of range selects on loop variables, fixes #1372
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-16 11:25:37 +02:00
Clifford Wolf
25e5fbac90
Properly construct $live and $fair cells from "if (...) assume/assert (s_eventually ...)"
...
Fixes https://github.com/YosysHQ/SymbiYosys/issues/59
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-02 22:56:38 +02:00
Eddie Hung
fe1b2337fd
Do not propagate mem2reg attribute through to result
2019-08-22 16:57:59 -07:00
Eddie Hung
a6776ee35e
mem2reg to preserve user attributes and src
2019-08-21 13:36:01 -07:00
Eddie Hung
6d77236f38
substr() -> compare()
2019-08-07 12:20:08 -07:00
Eddie Hung
e6d5147214
Merge remote-tracking branch 'origin/master' into eddie/cleanup
2019-08-07 11:11:50 -07:00
Eddie Hung
ee7c970367
IdString::str().substr() -> IdString::substr()
2019-08-06 19:08:33 -07:00
Clifford Wolf
f1f5b4e375
Fix handling of functions/tasks without top-level begin-end block, fixes #1231
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-06 18:06:14 +02:00
Clifford Wolf
d187be39d6
Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968
2019-05-06 15:41:13 +02:00
Clifford Wolf
6bbe2fdbf3
Add splitcmplxassign test case and silence splitcmplxassign warning
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-01 10:01:54 +02:00
Clifford Wolf
59d74a3348
Re-enable "final loop assignment" feature
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-01 09:02:39 +02:00
Clifford Wolf
e35fe1344d
Disabled "final loop assignment" feature
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 20:22:50 +02:00
Clifford Wolf
9af825e31e
Add final loop variable assignment when unrolling for-loops, fixes #968
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 15:03:32 +02:00
Clifford Wolf
4ad0ea5c3c
Determine correct signedness and expression width in for loop unrolling, fixes #370
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-22 18:19:02 +02:00
Zachary Snow
5855024ccc
support repeat loops with constant repeat counts outside of constant functions
2019-04-09 12:28:32 -04:00
Clifford Wolf
638be461c3
Fix mem2reg handling of memories with upto data ports, fixes #888
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-21 22:21:17 +01:00
Zachary Snow
a5f4b83637
fix local name resolution in prefix constructs
2019-03-18 20:43:20 -04:00
Clifford Wolf
d25a0c8ade
Improve handling of memories used in mem index expressions on LHS of an assignment
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-12 20:12:02 +01:00
Clifford Wolf
a4ddc569b4
Remove outdated "blocking assignment to memory" warning
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-12 20:10:55 +01:00
Clifford Wolf
ab5b50ae3c
Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-12 20:09:47 +01:00
Clifford Wolf
cebd21aa96
Merge pull request #858 from YosysHQ/clifford/svalabels
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Add support for using SVA labels in yosys-smtbmc console output
2019-03-09 11:14:57 -08:00
Clifford Wolf
a330c68363
Fix handling of task output ports in clocked always blocks, fixes #857
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-07 22:44:37 -08:00
Clifford Wolf
22ff60850e
Add support for SVA labels in read_verilog
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-07 11:17:32 -08:00
Clifford Wolf
ae9286386d
Only run derive on blackbox modules when ports have dynamic size
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-02 12:36:46 -08:00
Clifford Wolf
ce6695e22c
Fix $global_clock handling vs autowire
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-02 10:38:13 -08:00
Clifford Wolf
5d93dcce86
Fix $readmem[hb] for mem2reg memories, fixes #785
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-02 09:58:20 -08:00
Clifford Wolf
7cfae2c52f
Use mem2reg on memories that only have constant-index write ports
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-01 13:35:09 -08:00
Clifford Wolf
1816fe06af
Fix handling of defparam for when default_nettype is none
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-24 20:09:41 +01:00
Clifford Wolf
23148ffae1
Fixes related to handling of autowires and upto-ranges, fixes #814
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 18:40:11 +01:00
Clifford Wolf
974927adcf
Fix handling of expression width in $past, fixes #810
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 17:55:33 +01:00
Clifford Wolf
fdf7c42181
Fix segfault in AST simplify
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(as proposed by Dan Gisselquist)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-18 17:49:38 +01:00
Sylvain Munaut
86ce43999e
Make return value of $clog2 signed
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As per Verilog 2005 - 17.11.1.
Fixes #708
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-24 18:49:23 +01:00
Clifford Wolf
64e0582c29
Various indenting fixes in AST front-end (mostly space vs tab issues)
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-04 10:19:32 +01:00
ZipCPU
39f891aebc
Make and dependent upon LSB only
2018-11-03 13:39:32 -04:00
Clifford Wolf
d86ea6badd
Do not generate "reg assigned in a continuous assignment" warnings for "rand reg"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-01 15:25:24 +01:00
Clifford Wolf
f24bc1ed0a
Merge pull request #659 from rubund/sv_interfaces
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Support for SystemVerilog interfaces and modports
2018-10-18 10:58:47 +02:00
Clifford Wolf
38dbb44fa0
Merge pull request #638 from udif/pr_reg_wire_error
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Fix issue #630
2018-10-17 12:13:18 +02:00
Ruben Undheim
75009ada3c
Synthesis support for SystemVerilog interfaces
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This time doing the changes mostly in AST before RTLIL generation
2018-10-12 21:11:36 +02:00
Dan Gisselquist
62424ef3de
Add read_verilog $changed support
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-01 19:41:35 +02:00
Clifford Wolf
9f9fe94b35
Fix handling of $past 2nd argument in read_verilog
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-09-30 18:43:35 +02:00
Udi Finkelstein
80a07652f2
Fixed issue #630 by fixing a minor typo in the previous commit
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(as well as a non critical minor code optimization)
2018-09-25 00:32:57 +03:00
Udi Finkelstein
c693f595c5
Merge branch 'master' into pr_reg_wire_error
2018-09-18 01:27:01 +03:00
Udi Finkelstein
f6fe73b31f
Fixed remaining cases where we check fo wire reg/wire incorrect assignments
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on Yosys-generated assignments.
In this case, offending code was:
module top(input in, output out);
function func;
input arg;
func = arg;
endfunction
assign out = func(in);
endmodule
2018-09-18 01:23:40 +03:00
Clifford Wolf
d8e40c75eb
Merge pull request #590 from hzeller/remaining-file-error
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Fix remaining log_file_error(); emit dependent file references in new…
2018-08-15 14:01:34 +02:00
Clifford Wolf
3d27c1cc80
Merge pull request #513 from udif/pr_reg_wire_error
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Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
2018-08-15 13:35:41 +02:00
Henner Zeller
3101b9b8c9
Fix remaining log_file_error(); emit dependent file references in new line.
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There are some places that reference dependent file locations ("this function was
called from ..."). These are now in a separate line for ease of jumping to
it with the editor (behaves similarly to compilers that emit dependent
messages).
2018-07-20 18:52:52 -07:00
Henner Zeller
68b5d0c3b1
Convert more log_error() to log_file_error() where possible.
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Mostly statements that span over multiple lines and haven't been
caught with the previous conversion.
2018-07-20 09:37:44 -07:00
Henner Zeller
b5ea598ef6
Use log_file_warning(), log_file_error() functions.
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Wherever we can report a source-level location.
2018-07-20 08:19:06 -07:00
Udi Finkelstein
73d426bc87
Modified errors into warnings
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No longer false warnings for memories and assertions
2018-06-05 18:03:22 +03:00
Udi Finkelstein
2b9c75f8e3
This PR should be the base for discussion, do not merge it yet!
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It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements.
What it DOES'T do:
Detect registers connected to output ports of instances.
Where it FAILS:
memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals.
You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
2018-03-11 23:09:34 +02:00
Clifford Wolf
eb67a7532b
Add $allconst and $allseq cell types
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-23 13:14:47 +01:00
Clifford Wolf
a96c775a73
Add support for "yosys -E"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-07 16:36:13 +01:00
Clifford Wolf
8364f509e3
Fix error handling for nested always/initial
2017-12-02 18:52:05 +01:00
Clifford Wolf
bc80426d45
Remove some dead code
2017-10-10 12:00:48 +02:00
Clifford Wolf
caa78388cd
Allow $past, $stable, $rose, $fell in $global_clock blocks
2017-10-10 11:59:32 +02:00
Clifford Wolf
dbfd8460a9
Allow $size and $bits in verilog mode, actually check test case
2017-09-29 11:56:43 +02:00
Udi Finkelstein
e951ac0dfb
$size() now works correctly for all cases!
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It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.
2017-09-26 20:34:24 +03:00
Udi Finkelstein
6ddc6a7af4
$size() seems to work now with or without the optional parameter.
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Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
2017-09-26 19:18:25 +03:00
Udi Finkelstein
7e391ba904
enable $bits() and $size() functions only when the SystemVerilog flag is enabled for read_verilog
2017-09-26 09:19:56 +03:00
Udi Finkelstein
2dea42e903
Added $bits() for memories as well.
2017-09-26 09:11:25 +03:00
Udi Finkelstein
17f8b41605
$size() now works with memories as well!
2017-09-26 08:36:45 +03:00
Udi Finkelstein
64eb8f29ad
Add $size() function. At the moment it works only on expressions, not on memories.
2017-09-26 06:25:42 +03:00
Clifford Wolf
5f1d0b1024
Add $live and $fair cell types, add support for s_eventually keyword
2017-02-25 10:36:39 +01:00
Clifford Wolf
4fb8007171
Fix incorrect "incompatible re-declaration of wire" error in tasks/functions
2017-02-14 15:10:59 +01:00
Clifford Wolf
3928482a3c
Add $cover cell type and SVA cover() support
2017-02-04 14:14:26 +01:00
Clifford Wolf
78f65f89ff
Fix bug in AstNode::mem2reg_as_needed_pass2()
2017-01-15 13:52:50 +01:00
Clifford Wolf
2d32c6c4f6
Fixed handling of local memories in functions
2017-01-05 13:19:03 +01:00
Clifford Wolf
81a9ee2360
Added handling of local memories and error for local decls in unnamed blocks
2017-01-04 16:03:04 +01:00
Clifford Wolf
dfb461fe52
Added Verilog $rtoi and $itor support
2017-01-03 17:40:58 +01:00
Clifford Wolf
70d7a02cae
Added support for hierarchical defparams
2016-11-15 13:35:19 +01:00
Clifford Wolf
2874914bcb
Fixed anonymous genblock object names
2016-11-04 07:46:30 +01:00
Clifford Wolf
56e2bb88ae
Some fixes in handling of signed arrays
2016-11-01 23:17:43 +01:00
Clifford Wolf
bdc316db50
Added $anyseq cell type
2016-10-14 15:24:03 +02:00
Clifford Wolf
aaa99c35bd
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
Clifford Wolf
97583ab729
Avoid creation of bogus initial blocks for assert/assume in always @*
2016-09-06 17:34:42 +02:00
Clifford Wolf
6f41e5277d
Removed $aconst cell type
2016-08-30 19:09:56 +02:00
Clifford Wolf
eae390ae17
Removed $predict again
2016-08-28 21:35:33 +02:00
Clifford Wolf
450f6f59b4
Fixed bug with memories that do not have a down-to-zero data width
2016-08-22 14:27:46 +02:00
Clifford Wolf
82a4a0230f
Another bugfix in mem2reg code
2016-08-21 13:23:58 +02:00
Clifford Wolf
fe9315b7a1
Fixed finish_addr handling in $readmemh/$readmemb
2016-08-20 13:47:46 +02:00
Clifford Wolf
f6629b9c29
Optimize memory address port width in wreduce and memory_collect, not verilog front-end
2016-08-19 18:38:25 +02:00
Clifford Wolf
4056312987
Added $anyconst and $aconst
2016-07-27 15:41:22 +02:00
Clifford Wolf
7fef5ff104
Using $initstate in "initial assume" and "initial assert"
2016-07-21 14:37:28 +02:00
Clifford Wolf
5c166e76e5
Added $initstate cell type and vlog function
2016-07-21 14:23:22 +02:00
Clifford Wolf
d7763634b6
After reading the SV spec, using non-standard predict() instead of expect()
2016-07-21 13:34:33 +02:00
Clifford Wolf
721f1f5ecf
Added basic support for $expect cells
2016-07-13 16:56:17 +02:00
Clifford Wolf
9a101dc1f7
Fixed mem assignment in left-hand-side concatenation
2016-07-08 14:31:06 +02:00
Clifford Wolf
ee071586c5
Fixed access-after-delete bug in mem2reg code
2016-05-27 17:25:33 +02:00
Clifford Wolf
5a09fa4553
Fixed handling of parameters and const functions in casex/casez pattern
2016-04-21 15:31:54 +02:00
Clifford Wolf
5328a85149
Do not set "nosync" on task outputs, fixes #134
2016-03-24 12:16:47 +01:00
Clifford Wolf
4f0d4899ce
Added support for $stop system task
2016-03-21 16:19:51 +01:00
Clifford Wolf
e5d42ebb4d
Added $display %m support, fixed mem leak in $display, fixes #128
2016-03-19 11:51:13 +01:00
Clifford Wolf
ef4207d5ad
Fixed localparam signdness, fixes #127
2016-03-18 12:15:00 +01:00
Clifford Wolf
b6d08f39ba
Set "nosync" attribute on internal task/function wires
2016-03-18 10:53:29 +01:00
Clifford Wolf
bcc873b805
Fixed some visual studio warnings
2016-02-13 17:31:24 +01:00
Clifford Wolf
c86fbae3d1
Fixed handling of re-declarations of wires in tasks and functions
2015-11-23 17:09:57 +01:00
Clifford Wolf
7ae3d1b5a9
More bugfixes in handling of parameters in tasks and functions
2015-11-12 13:02:36 +01:00
Clifford Wolf
34f2b84fb6
Fixed handling of parameters and localparams in functions
2015-11-11 10:54:35 +01:00
Clifford Wolf
207736b4ee
Import more std:: stuff into Yosys namespace
2015-10-25 19:30:49 +01:00
Clifford Wolf
e51dcc83d0
Fixed complexity of assigning to vectors in constant functions
2015-10-01 12:15:35 +02:00
Clifford Wolf
9caeadf797
Fixed detection of unconditional $readmem[hb]
2015-09-30 15:46:51 +02:00
Clifford Wolf
f9d7df0869
Bugfixes in $readmem[hb]
2015-09-25 13:49:48 +02:00
Clifford Wolf
089c1e176f
Bugfix in handling of multi-dimensional memories
2015-09-23 07:56:17 +02:00
Clifford Wolf
559929e341
Warning for $display/$write outside initial block
2015-09-23 07:16:03 +02:00
Clifford Wolf
6176f4d081
Fixed multi-level prefix resolving
2015-09-22 20:52:02 +02:00
Andrew Zonenberg
c469f22144
Improvements to $display system task
2015-09-19 10:33:37 +02:00
Clifford Wolf
9db05d17fe
Added AST_INITIAL checks for $finish and $display
2015-09-18 09:50:57 +02:00
Andrew Zonenberg
7141f65533
Initial implementation of $display()
2015-09-18 09:36:46 +02:00
Andrew Zonenberg
e446e651cb
Initial implementation of $finish()
2015-09-18 09:30:25 +02:00
Clifford Wolf
eb38722e98
Fixed handling of memory read without address
2015-08-22 14:46:42 +02:00
Larry Doolittle
022f570563
Keep gcc from complaining about uninitialized variables
2015-08-14 23:26:49 +02:00
Clifford Wolf
84bf862f7c
Spell check (by Larry Doolittle)
2015-08-14 10:56:05 +02:00
Clifford Wolf
8d6d5c30d9
Added WORDS parameter to $meminit
2015-07-31 10:40:09 +02:00
Clifford Wolf
4513ff1b85
Fixed nested mem2reg
2015-07-29 16:37:08 +02:00
Clifford Wolf
6c84341f22
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
Clifford Wolf
13983e8318
Fixed handling of parameters with reversed range
2015-06-08 14:03:06 +02:00
Clifford Wolf
99b8746d27
Fixed signedness of genvar expressions
2015-05-29 20:08:00 +02:00
Clifford Wolf
1f1deda888
Added non-std verilog assume() statement
2015-02-26 18:47:39 +01:00
Clifford Wolf
d5ce9a32ef
Added deep recursion warning to AST simplify
2015-02-20 10:33:20 +01:00
Clifford Wolf
dc1a0f06fc
Parser support for complex delay expressions
2015-02-20 10:21:36 +01:00
Clifford Wolf
e9368a1d7e
Various fixes for memories with offsets
2015-02-14 14:21:15 +01:00
Clifford Wolf
7f1a1759d7
Added "read_verilog -nomeminit" and "nomeminit" attribute
2015-02-14 11:21:12 +01:00
Clifford Wolf
a8e9d37c14
Creating $meminit cells in verilog front-end
2015-02-14 10:49:30 +01:00
Clifford Wolf
cd919abdf1
Added AstNode::simplify() recursion counter
2015-02-13 12:33:12 +01:00
Clifford Wolf
2a9ad48eb6
Added ENABLE_NDEBUG makefile options
2015-01-24 12:16:46 +01:00
Clifford Wolf
df9d096a7d
Ignoring more system task and functions
2015-01-15 13:08:19 +01:00
Clifford Wolf
a588a4a5c9
Fixed handling of "input foo; reg [0:0] foo;"
2015-01-15 12:53:12 +01:00
Clifford Wolf
8e8e791fb5
Consolidate "Blocking assignment to memory.." msgs for the same line
2015-01-15 12:41:52 +01:00
Clifford Wolf
90bc71dd90
dict/pool changes in ast
2014-12-29 03:11:50 +01:00
Clifford Wolf
12ca6538a4
Fixed mem2reg warning message
2014-12-27 03:26:30 +01:00
Clifford Wolf
fe829bdbdc
Added log_warning() API
2014-11-09 10:44:23 +01:00
Clifford Wolf
37aa2e02db
AST simplifier: optimize constant AST_CASE nodes before recursively descending
2014-10-29 08:29:51 +01:00
Clifford Wolf
c4a2b3c1e9
Improvements in $readmem[bh] implementation
2014-10-26 23:29:36 +01:00
Clifford Wolf
70b2efdb05
Added support for $readmemh/$readmemb
2014-10-26 20:33:10 +01:00
Clifford Wolf
84ffe04075
Fixed various VS warnings
2014-10-18 15:20:38 +02:00
William Speirs
fda52f05f2
Wrapped math in int constructor
2014-10-17 11:28:14 +02:00
Clifford Wolf
6b05a9e807
Fixed handling of invalid array access in mem2reg code
2014-10-16 00:44:23 +02:00
Clifford Wolf
4569a747f8
Renamed SIZE() to GetSize() because of name collision on Win32
2014-10-10 17:07:24 +02:00
Clifford Wolf
48b00dccea
Another $clog2 bugfix
2014-09-08 12:25:23 +02:00
Clifford Wolf
680eaaac41
Fixed $clog2 (off by one error)
2014-09-06 19:31:04 +02:00
Ruben Undheim
79cbf9067c
Corrected spelling mistakes found by lintian
2014-09-06 08:47:06 +02:00
Clifford Wolf
ad146c2582
Fixed small memory leak in ast simplify
2014-08-21 17:33:40 +02:00
Clifford Wolf
6c5cafcd8b
Added support for DPI function with different names in C and Verilog
2014-08-21 17:22:04 +02:00
Clifford Wolf
490d7a5bf2
Fixed memory leak in DPI function calls
2014-08-21 13:09:47 +02:00
Clifford Wolf
7bfc4ae120
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
2014-08-21 12:43:51 +02:00
Clifford Wolf
640d9fc551
Added "via_celltype" attribute on task/func
2014-08-18 14:29:30 +02:00
Clifford Wolf
acb435b6cf
Added const folding of AST_CASE to AST simplifier
2014-08-18 00:02:30 +02:00
Clifford Wolf
85e3cc12ac
Fixed handling of task outputs
2014-08-14 22:26:10 +02:00
Clifford Wolf
d259abbda2
Added AST_MULTIRANGE (arrays with more than 1 dimension)
2014-08-06 15:52:54 +02:00
Clifford Wolf
91dd87e60b
Improved scope resolution of local regs in Verilog+AST frontend
2014-08-05 12:15:53 +02:00
Clifford Wolf
0129d41efa
Fixed AST handling of variables declared inside a functions main block
2014-08-05 08:35:51 +02:00
Clifford Wolf
768eb846c4
More bugfixes related to new RTLIL::IdString
2014-08-02 18:14:21 +02:00
Clifford Wolf
14412e6c95
Preparations for RTLIL::IdString redesign: cleanup of existing code
2014-08-02 00:45:25 +02:00
Clifford Wolf
1cb25c05b3
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
2014-07-31 13:19:47 +02:00
Clifford Wolf
48822e79a3
Removed left over debug code
2014-07-28 19:38:30 +02:00
Clifford Wolf
ec58965967
Fixed part selects of parameters
2014-07-28 19:24:28 +02:00
Clifford Wolf
27a872d1e7
Added support for "upto" wires to Verilog front- and back-end
2014-07-28 14:25:03 +02:00
Clifford Wolf
7bd2d1064f
Using log_assert() instead of assert()
2014-07-28 11:27:48 +02:00
Clifford Wolf
309d64d46a
Fixed two memory leaks in ast simplify
2014-07-25 13:24:10 +02:00
Clifford Wolf
20a7965f61
Various small fixes (from gcc compiler warnings)
2014-07-23 20:45:27 +02:00
Clifford Wolf
9b183539af
Implemented dynamic bit-/part-select for memory writes
2014-07-17 16:49:23 +02:00
Clifford Wolf
5867f6bcdc
Added support for bit/part select to mem2reg rewriter
2014-07-17 13:49:32 +02:00
Clifford Wolf
6d69d4aaa8
Added support for constant bit- or part-select for memory writes
2014-07-17 13:13:21 +02:00
Clifford Wolf
543551b80a
changes in verilog frontend for new $mem/$memwr WR_EN interface
2014-07-16 12:49:50 +02:00
Clifford Wolf
55a1b8dbac
Fixed processing of initial values for block-local variables
2014-07-11 13:05:53 +02:00
Clifford Wolf
076182c34e
Fixed handling of mixed real/int ternary expressions
2014-06-25 10:05:36 +02:00
Clifford Wolf
80e4594695
Added AstNode::MEM2REG_FL_CMPLX_LHS
2014-06-17 21:39:25 +02:00
Clifford Wolf
798ff88855
Improved handling of relational op of real values
2014-06-17 12:47:51 +02:00
Clifford Wolf
6c17d4f242
Improved ternary support for real values
2014-06-16 15:12:24 +02:00
Clifford Wolf
82bbd2f077
Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012
2014-06-16 15:05:37 +02:00
Clifford Wolf
48dc6ab98d
Improved AstNode::asReal for large integers
2014-06-15 08:38:31 +02:00
Clifford Wolf
149fe83a8d
improved (fixed) conversion of real values to bit vectors
2014-06-14 21:00:51 +02:00
Clifford Wolf
d5765b5e14
Fixed relational operators for const real expressions
2014-06-14 19:33:58 +02:00
Clifford Wolf
f3b4a9dd24
Added support for math functions
2014-06-14 13:36:23 +02:00
Clifford Wolf
9bd7d5c468
Added handling of real-valued parameters/localparams
2014-06-14 12:00:47 +02:00
Clifford Wolf
fc7b6d172a
Implemented more real arithmetic
2014-06-14 11:27:05 +02:00
Clifford Wolf
442a8e2875
Implemented basic real arithmetic
2014-06-14 08:51:22 +02:00