yosys

mirror of https://github.com/YosysHQ/yosys.git

Author	SHA1	Message	Date
Clifford Wolf	df9753d398	Added mem2reg option to verilog frontend	2013-03-24 11:13:32 +01:00
Clifford Wolf	a321a5c412	Moved stand-alone libs to libs/ directory and added libs/subcircuit	2013-02-27 09:32:19 +01:00
Clifford Wolf	4f0c2862a0	Added support for verilog genblock[index].member syntax	2013-02-26 13:18:22 +01:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00