Patrick Urban
5d08688054
gatemate: Fix minor issues with `memory_libmap` ( #3343 )
2022-05-27 23:35:26 +02:00
Marcelina Kościelnicka
2a2dc12eb6
gatemate: Use `memory_libmap` pass.
2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
2dcb0797f0
machxo2: Use `memory_libmap` pass.
2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
9d11575856
efinix: Use `memory_libmap` pass.
2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
f4d1426229
anlogic: Use `memory_libmap` pass.
2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
d7dc2313b9
ice40: Use `memory_libmap` pass.
2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
3b2f95953c
xilinx: Use `memory_libmap` pass.
2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
e4d811561c
gowin: Use `memory_libmap` pass.
2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
0a8eaca322
nexus: Use `memory_libmap` pass.
2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
a04b025abf
ecp5: Use `memory_libmap` pass.
2022-05-18 17:32:56 +02:00
Rick Luiken
414dc25a96
Add missing parameters for ecp5
2022-04-25 15:31:41 +01:00
Tim Pambor
30bc0d26ea
gowin: Add oscillator primitives
2022-03-28 13:33:24 +02:00
Marcelina Kościelnicka
be9595e18f
xilinx: Add RAMB4* blackboxes
2022-03-21 13:11:52 +01:00
YRabbit
19b7633aca
gowin: add support for Double Data Rate primitives
...
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-03-14 23:14:21 +01:00
Lofty
9f7a55c99f
intel_alm: M10K write-enable is negative-true
2022-03-09 20:18:06 +00:00
YRabbit
22d9bbb308
gowin: Remove unnecessary attributes
...
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-02-24 05:38:33 +01:00
YRabbit
9b3cd4f0d8
gowin: Add support for true differential output
...
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-02-24 05:38:33 +01:00
Marcelina Kościelnicka
d0f4d0b153
ecp5: Do not use specify in generate in cells_sim.v.
2022-02-21 17:52:31 +01:00
Marcelina Kościelnicka
3a62fa0c97
gowin: Add remaining block RAM blackboxes.
2022-02-12 11:48:57 +01:00
Marcelina Kościelnicka
f61f2a4078
gowin: Fix LUT RAM inference, add more models.
2022-02-09 09:04:34 +01:00
Marcelina Kościelnicka
ac2bb70b52
ecp5: Fix DPR16X4 sim model.
2022-02-09 09:02:13 +01:00
Marcelina Kościelnicka
958c3a46ad
nexus: Fix arith_map CO signal.
...
Fixes #3187 .
2022-02-06 13:05:30 +01:00
Xing GUO
0520e99968
Fix the help message of synth_quicklogic.
2022-01-31 02:23:59 +08:00
Marcelina Kościelnicka
93508d58da
Add $bmux and $demux cells.
2022-01-28 23:34:41 +01:00
gatecat
f699c4ba58
nexus: Fix BB sim model
...
Signed-off-by: gatecat <gatecat@ds0.me>
2022-01-19 18:14:24 +00:00
Miodrag Milanovic
36482680d5
Removed dbits 8 since 9 will always be picked
2022-01-19 08:51:25 +01:00
Miodrag Milanović
4525e419f6
Merge pull request #3120 from Icenowy/anlogic-bram
...
anlogic: support BRAM mapping
2022-01-19 08:49:58 +01:00
Lofty
d015c2b48a
intel_alm: disable 256x40 M10K mode
...
This BRAM mode uses both address ports, making it effectively single-port.
Since memory_bram can't presently map to single-port memories, remove it.
2021-12-22 00:42:33 +01:00
Icenowy Zheng
c2b7ad3b28
anlogic: support BRAM mapping
...
Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being
true dual port (or 18bit*512 when simple dual port), the other is
16bit*2K.
Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and
32Kbit BRAM with 8bit width are not support yet.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2021-12-17 20:28:22 +08:00
Lofty
a31c8a82be
intel_alm: preliminary Arria V support
2021-11-25 17:20:36 +01:00
Patrick Urban
cb41209095
synth_gatemate Revert cascade A/B port mixup
2021-11-13 21:53:25 +01:00
Patrick Urban
decdc743db
synth_gatemate: Remove iob_map invokation
2021-11-13 21:53:25 +01:00
Patrick Urban
0d871b6c49
synth_gatemate: Add block RAM cascade support
...
* add simulation model for block RAM cascade in 40K mode
* limit 20K_SDP and 40K_SDP to 40 and 80 bits (the only useful configurations)
2021-11-13 21:53:25 +01:00
Patrick Urban
285ec0547b
synth_gatemate: Remove obsolete iob_map
2021-11-13 21:53:25 +01:00
Patrick Urban
81964d6d6f
synth_gatemate: Update pass
...
* remove `write_edif` and `write_blif` options
* remove redundant `abc` call before muxcover
* update style
2021-11-13 21:53:25 +01:00
Patrick Urban
74aee88e81
synth_gatemate: Remove specify blocks
2021-11-13 21:53:25 +01:00
Patrick Urban
05f24adca9
synth_gatemate: Remove gatemate_bramopt pass
2021-11-13 21:53:25 +01:00
Patrick Urban
4bee908ae8
synth_gatemate: Revise block RAM read modes and initialization
...
* enable mixed read-width / write-width ports in SDP mode
* fix NO_CHANGE and WRITE_THROUGH behavior during read access
* remove redundant zero-initialization
* set A/B_WE bit during map (gatemate_bramopt pass could be removed later)
* differentiate "upper" and "lower" initialization for cascade mode
2021-11-13 21:53:25 +01:00
Patrick Urban
3f4ccdf2f5
synth_gatemate: Remove unsupported FF initialization
2021-11-13 21:53:25 +01:00
Patrick Urban
d592bd93b8
synth_gatemate: Rename multiplier factor parameters
2021-11-13 21:53:25 +01:00
Patrick Urban
6825de6343
synth_gatemate: Registers are uninitialized
2021-11-13 21:53:25 +01:00
Patrick Urban
0a72952d5f
synth_gatemate: Apply review remarks
...
* remove unused techmap models in `map_regs.v`
* replace RAM initilization loops with 320-bit-writes
* add script to test targets in top-level Makefile
* remove `MAXWIDTH` parameter and treat both vector widths individually in `mult_map.v`
* iterate over all modules in `gatemate_bramopt` pass
2021-11-13 21:53:25 +01:00
Patrick Urban
cfcc38582a
synth_gatemate: Apply review remarks
2021-11-13 21:53:25 +01:00
Patrick Urban
240d289fff
synth_gatemate: Initial implementation
...
Signed-off-by: Patrick Urban <patrick.urban@web.de>
2021-11-13 21:53:25 +01:00
Marcelina Kościelnicka
15b0d717ed
iopadmap: Add native support for negative-polarity output enable.
2021-11-09 15:40:16 +01:00
Pepijn de Vos
4bf8deacbb
synth_gowin: move splitnets to after iopadmap ( #2435 )
2021-11-07 18:00:18 +01:00
Pepijn de Vos
a3eec687e0
Remove noalu from synth_gowin json output as Apicula now supports it
2021-11-07 03:04:21 +01:00
Pepijn de Vos
0c7461fe5e
gowin: widelut support ( #3042 )
2021-11-06 16:09:30 +01:00
Marcelina Kościelnicka
e14302a3ea
ecp5: Add support for mapping aldff.
2021-10-27 16:18:05 +02:00
Claire Xenia Wolf
fe9689c136
Fixed Verific parser error in ice40 cell library
...
non-net output port 'Q' cannot be initialized at declaration in SystemVerilog mode
2021-10-19 12:33:18 +02:00
Olivier Galibert
6e78a80ff9
CycloneV: Add (passthrough) support for cyclonev_oscillator
2021-10-17 20:00:03 +02:00
Olivier Galibert
6253d4ec9e
CycloneV: Add (passthrough) support for cyclonev_hps_interface_mpu_general_purpose
2021-10-17 10:39:13 +02:00
Marcelina Kościelnicka
e7d89e653c
Hook up $aldff support in various passes.
2021-10-02 21:01:21 +02:00
Marcelina Kościelnicka
ec2b5548fe
Add $aldff and $aldffe: flip-flops with async load.
2021-10-02 18:12:52 +02:00
Eddie Hung
f03e2c30aa
abc9: replace cell type/parameters if derived type already processed ( #2991 )
...
* Add close bracket
* Add testcase
* Replace cell type/param if in unmap_design
* Improve abc9_box error message too
* Update comment as per review
2021-09-09 10:05:55 -07:00
kittennbfive
6de500ec08
[ECP5] fix wrong link for syn_* attributes description ( #2984 )
2021-08-29 11:45:23 +02:00
ECP5-PCIe
dfc453b246
Add DLLDELD
2021-08-22 18:48:44 +02:00
Pepijn de Vos
c2d358484f
Gowin: deal with active-low tristate ( #2971 )
...
* deal with active-low tristate
* remove empty port
* update sim models
* add expected lut1 to tests
2021-08-20 21:21:06 +02:00
Sylvain Munaut
3806b07303
ice40: Fix typo in SB_CARRY specify for LP/UltraPlus
...
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2021-08-17 14:33:30 +02:00
Marcelina Kościelnicka
fd79217763
Add v2 memory cells.
2021-08-11 13:34:10 +02:00
Maciej Dudek
cfddef5d7d
Fixes xc7 BRAM36s
...
UG473 from Xilinx states that 15 bit should always be set if RAMB isn't in cascade mode.
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
2021-07-30 16:17:22 +02:00
Marcelina Kościelnicka
54e75129e5
opt_lut: Allow more than one -dlogic per cell type.
...
Fixes #2061 .
2021-07-29 17:30:07 +02:00
Marcelina Kościelnicka
19720b970d
memory: Introduce $meminit_v2 cell, with EN input.
2021-07-28 23:18:38 +02:00
Marcelina Kościelnicka
726fabd65e
ice40: Fix LUT input indices in opt_lut -dlogic (again).
...
Fixes #2061 .
2021-07-10 21:30:01 +02:00
gatecat
2b8f1633ce
ecp5: Add DCSC blackbox
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-06 14:07:20 +01:00
Claire Xenia Wolf
06b99950ed
Fix icestorm links
...
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-06-09 12:39:12 +02:00
Claire Xenia Wolf
0ada13cbe2
Use HTTPS for website links, gatecat email
...
git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g ;
2021-06-09 12:16:56 +02:00
Claire Xenia Wolf
92e705cb51
Fix files with CRLF line endings
2021-06-09 12:16:33 +02:00
Claire Xenia Wolf
72787f52fc
Fixing old e-mail addresses and deadnames
...
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g ;
2021-06-08 00:39:36 +02:00
gatecat
34a08750fa
intel_alm: Fix illegal carry chains
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 22:37:06 +01:00
gatecat
eb106732d9
intel_alm: Add global buffer insertion
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 22:37:06 +01:00
gatecat
5dba138c87
intel_alm: Add IO buffer insertion
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 22:37:06 +01:00
Adam Greig
9e02786d39
Add missing parameters for MULT18X18D and ALU54B to ECP5 techlib.
2021-05-12 10:04:34 +01:00
Michael Christensen
67d6f3973b
Fix use of blif name in synth_xilinx command
2021-04-27 02:29:52 -07:00
Claire Xenia Wolf
46d3f03d27
Add default assignments to other SB_* simulation models
...
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-04-20 18:52:36 +02:00
Claire Xenia Wolf
8aee80040d
Add default assignments to SB_LUT4
...
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-04-20 12:46:21 +02:00
Lofty
dce037a62c
quicklogic: ABC9 synthesis
2021-04-17 20:54:58 +02:00
Stefan Riesenberger
a58571d0fe
sf2: fix name of AND modules
2021-04-09 16:46:05 +02:00
Eddie Hung
55dc5a4e4f
abc9: fix SCC issues ( #2694 )
...
* xilinx: add SCC test for DSP48E1
* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1
Have a test that checks it works through ABC9 when enabled
* abc9 to break SCCs using $__ABC9_SCC_BREAKER module
* Add test
* abc9_ops: remove refs to (* abc9_keep *) on wires
* abc9_ops: do not bypass cells in an SCC
* Add myself to CODEOWNERS for abc9*
* Fix compile
* abc9_ops: run -prep_hier before scc
* Fix tests
* Remove bug reference pending fix
* abc9: fix for -prep_hier -dff
* xaiger: restore PI handling
* abc9_ops: -prep_xaiger sigmap
* abc9_ops: -mark_scc -> -break_scc
* abc9: eliminate hard-coded abc9.box from tests
Also tidy up
* Address review
2021-03-29 22:01:57 -07:00
Lofty
f4298b057a
quicklogic: PolarPro 3 support
...
Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com>
Co-authored-by: Maciej Kurc <mkurc@antmicro.com>
Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com>
Co-authored-by: Lalit Sharma <lsharma@quicklogic.com>
Co-authored-by: kkumar23 <kkumar@quicklogic.com>
2021-03-18 13:28:16 +01:00
gatecat
cae905f551
Blackbox all whiteboxes after synthesis
...
This prevents issues like processes in whiteboxes triggering an error in
the JSON backend.
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-17 21:07:20 +00:00
Marcelina Kościelnicka
a3528649c8
memory_dff: Remove now-useless write port handling.
2021-03-08 20:16:29 +01:00
Marcelina Kościelnicka
cde73428b0
Fix syntax error in adff2dff.v
...
Fixes #2600 .
2021-02-24 01:07:34 +01:00
William D. Jones
ae07298a6b
machxo2: Switch to LUT4 sim model which propagates less undefined/don't care values.
2021-02-23 17:39:58 +01:00
William D. Jones
8f1a350f5e
machxo2: Add experimental status to help.
2021-02-23 17:39:58 +01:00
William D. Jones
e3974809ec
machxo2: Add DCCA and DCMA blackbox primitives.
2021-02-23 17:39:58 +01:00
William D. Jones
a1ea1430b6
machxo2: Fix reversed interpretation of REG_SD config bits.
2021-02-23 17:39:58 +01:00
William D. Jones
4e9def23de
machxo2: Tristate is active-low.
2021-02-23 17:39:58 +01:00
William D. Jones
8b14152506
machxo2: Fix typos in FACADE_FF sim model.
2021-02-23 17:39:58 +01:00
William D. Jones
8348c45e4f
machxo2: Fix naming of TRELLIS_IO ports to match PIO pins in routing graph.
2021-02-23 17:39:58 +01:00
William D. Jones
120404bfda
machxo2: Improve help_mode output in synth_machxo2.
2021-02-23 17:39:58 +01:00
William D. Jones
3674eb34d4
machxo2: Use attrmvcp pass to move LOC and src attributes from ports/wires to IO cells.
2021-02-23 17:39:58 +01:00
William D. Jones
124780ecd9
machxo2: Add missing OSCH oscillator primitive.
2021-02-23 17:39:58 +01:00
William D. Jones
597a54dbd0
machxo2: Add -noiopad option to synth_machxo2.
2021-02-23 17:39:58 +01:00
William D. Jones
3697f351d5
machxo2: Use correct INITVAL for LUT1 in FACADE_SLICE.
2021-02-23 17:39:58 +01:00
William D. Jones
f07b8eb606
machxo2: Fix cells_sim typo where OFX1 was multiply-driven.
2021-02-23 17:39:58 +01:00
William D. Jones
c76f361b56
machxo2: synth_machxo2 now maps ports to FACADE_IO.
2021-02-23 17:39:58 +01:00
William D. Jones
03cbf1327d
machxo2: Add initial value for Q in FACADE_FF.
2021-02-23 17:39:58 +01:00
William D. Jones
0364ded385
machxo2: Add FACADE_IO simulation model. More comments on models.
2021-02-23 17:39:58 +01:00
William D. Jones
1b703d3f03
machxo2: Add FACADE_SLICE simulation model.
2021-02-23 17:39:58 +01:00
William D. Jones
cc52eb53cd
machxo2: Improve FACADE_FF simulation model.
2021-02-23 17:39:58 +01:00
William D. Jones
427fed23ee
machxo2: Improve LUT4 techmap. Use same output port name for LUT4 as Lattice.
2021-02-23 17:39:58 +01:00
William D. Jones
84937e9689
machxo2: Add dff.ys test, fix another cells_map.v typo.
2021-02-23 17:39:58 +01:00
William D. Jones
044393b990
machxo2: Fix more oversights in machxo2 models. logic.ys test passes.
2021-02-23 17:39:58 +01:00
William D. Jones
b87f6a0906
machxo2: Fix typos. test/arch/run-test.sh passes.
2021-02-23 17:39:58 +01:00
William D. Jones
88c8f81260
machxo2: Create basic techlibs and synth_machxo2 pass.
2021-02-23 17:39:58 +01:00
gatecat
9f7cd10c98
Merge pull request #2585 from YosysHQ/dave/nexus-dotproduct
...
nexus: Add MULTADDSUB9X9WIDE sim model
2021-02-12 12:07:12 +00:00
Zachary Snow
fe74b0cd95
verilog: significant block scoping improvements
...
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-31 09:42:09 -05:00
Marcelina Kościelnicka
ea79e16bab
xilinx_dffopt: Don't crash on missing IS_*_INVERTED.
...
The presence of IS_*_INVERTED on FD* cells follows Vivado, which
apparently has been decided by a dice roll. Just assume false if the
parameter doesn't exist.
Fixes #2559 .
2021-01-27 00:32:00 +01:00
Marcelina Kościelnicka
cd6f0732f3
xilinx: Add FDRSE_1, FDCPE_1.
2021-01-27 00:32:00 +01:00
Tom Verbeure
87637e8359
Fix some trivial typos.
2021-01-03 23:52:59 -08:00
whitequark
b0d4c63957
Merge pull request #2480 from YosysHQ/dave/nexus-lram
...
nexus: Add LRAM inference
2021-01-01 09:49:00 +00:00
Marcelina Kościelnicka
f2932628fc
xilinx: Add some missing blackbox cells.
2020-12-21 05:34:26 +01:00
Marcelina Kościelnicka
5ffb676fa9
xilinx: Regenerate cells_xtra.v using Vivado 2020.2
2020-12-21 05:34:26 +01:00
Marcelina Kościelnicka
871fc34ad4
xilinx: Add FDDRCPE and FDDRRSE blackbox cells.
...
These are necessary primitives for proper DDR support on Virtex 2 and
Spartan 3.
2020-12-17 03:25:07 +01:00
David Shah
f5cc1224f9
nexus: Add MULTADDSUB9X9WIDE sim model
...
Signed-off-by: David Shah <dave@ds0.me>
2020-12-08 15:49:20 +00:00
David Shah
17812a1560
nexus: Add LRAM inference
...
Signed-off-by: David Shah <dave@ds0.me>
2020-12-07 13:27:17 +00:00
David Shah
264e924abb
nexus: More efficient CO mapping
...
Signed-off-by: David Shah <dave@ds0.me>
2020-12-02 17:08:39 +00:00
Pepijn de Vos
f155826a70
add -noalu and -json option for apicula
2020-11-30 11:43:12 +01:00
David Shah
9f241c9a42
nexus: DSP inference support
...
Signed-off-by: David Shah <dave@ds0.me>
2020-11-20 08:45:55 +00:00
Miodrag Milanović
c8d809897f
Merge pull request #2441 from YosysHQ/dave/nexus_dsp_sim
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nexus: Add DSP simulation model
2020-11-18 12:22:05 +01:00
David Shah
923843b3fa
nexus: Add DSP simulation model
...
Signed-off-by: David Shah <dave@ds0.me>
2020-11-18 10:21:17 +00:00
Miodrag Milanovic
aa4d94f7d8
Fix duplicated parameter name typo
2020-11-18 10:03:57 +01:00
Konrad Beckmann
5b9a975eba
synth_gowin: Add rPLL blackbox
2020-11-11 17:06:54 +01:00
David Shah
6d63e58e46
nexus: Add make_transp to BRAMs
...
Signed-off-by: David Shah <dave@ds0.me>
2020-10-22 15:11:59 +01:00
clairexen
e919d0c125
Merge pull request #2405 from byuccl/fix_xilinx_cells
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xilinx/cells_sim.v: Move signal declaration to before first use
2020-10-20 17:11:36 +02:00
Jeff Goeders
8be56960a2
Move signal declarations to before first use
...
Signed-off-by: Jeff Goeders <jeff.goeders@gmail.com>
2020-10-19 16:09:18 -06:00
David Shah
4d584d9319
synth_nexus: Initial implementation
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Signed-off-by: David Shah <dave@ds0.me>
2020-10-15 08:52:15 +01:00
Eddie Hung
de79978372
xilinx: do not make DSP48E1 a whitebox for ABC9 by default ( #2325 )
...
* xilinx: eliminate SCCs from DSP48E1 model
* xilinx: add SCC test for DSP48E1
* Update techlibs/xilinx/cells_sim.v
* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1
Have a test that checks it works through ABC9 when enabled
2020-09-23 09:15:24 -07:00
Dan Ravensloft
028f96e536
intel_alm: better map wide but shallow multiplies
2020-08-28 23:44:16 +02:00
Dan Ravensloft
1a07b330f8
intel_alm: Add multiply signedness to cells
...
Quartus assumes unsigned multiplication by default, breaking signed
multiplies, so add an input signedness parameter to the MISTRAL_MUL*
cells to propagate to Quartus' <family>_mac cells.
2020-08-26 22:50:16 +02:00
Marcelina Kościelnicka
082cbcb4c7
synth_intel: Remove incomplete Arria 10 GX support.
...
The techmap rules for this target do not work in the first place (note
lack of >2-input LUT mappings), and if proper support is ever added,
it'd be better placed in the synth_intel_alm backend.
2020-08-21 01:46:06 +02:00
Dan Ravensloft
034b9ec716
intel: move Cyclone V support to intel_alm
2020-08-20 18:25:05 +02:00
clairexen
d9dd8bc748
Merge pull request #2347 from YosysHQ/mwk/techmap-shift-fixes
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techmap/shift_shiftx: Remove the "shiftx2mux" special path.
2020-08-20 16:25:56 +02:00
clairexen
1cdb533fa5
Merge pull request #2319 from YosysHQ/mwk/techmap-celltype-pattern
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techmap: Add support for [] wildcards in techmap_celltype.
2020-08-20 16:18:40 +02:00
Marcelina Kościelnicka
50d532f01c
techmap/shift_shiftx: Remove the "shiftx2mux" special path.
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Our techmap rules for $shift and $shiftx cells contained a special path
that aimed to decompose the shift LSB-first instead of MSB-first in
select cases that come up in pmux lowering. This path was needlessly
overcomplicated and contained bugs.
Instead of doing that, just switch over the main path to iterate
LSB-first (except for the specially-handled MSB for signed shifts
and overflow handling). This also makes the code consistent with
shl/shr/sshl/sshr cells, which are already decomposed LSB-first.
Fixes #2346 .
2020-08-20 12:44:09 +02:00
Xiretza
928fd40c2e
Respect \A_SIGNED for $shift
...
This reflects the behaviour of $shr/$shl, which sign-extend their A
operands to the size of their output, then do a logical shift (shift in
0-bits).
2020-08-18 19:36:24 +02:00
Dan Ravensloft
3b534a203a
intel_alm: fix typo in MISTRAL_MUL27X27 cell name
2020-08-13 17:08:50 +02:00
Dan Ravensloft
97daf612cb
intel_alm: add more megafunctions. NFC.
2020-08-12 18:39:22 +02:00
Marcelina Kościelnicka
9a4f420b4b
Replace opt_rmdff with opt_dff.
2020-08-07 13:21:03 +02:00
Marcelina Kościelnicka
522788f016
techmap: Add support for [] wildcards in techmap_celltype.
...
Fixes #1826 .
2020-08-02 22:46:48 +02:00
Marcelina Kościelnicka
6cd135a5eb
opt_expr: Remove -clkinv option, make it the default.
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Adds -noclkinv option just in case the old behavior was actually useful
to someone.
2020-07-31 00:08:15 +02:00
Marcelina Kościelnicka
cf60699884
synth_ice40: Use opt_dff.
...
The main part is converting ice40_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the mux patterns on
its own.
The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.
2020-07-30 22:26:20 +02:00
Marcelina Kościelnicka
8501342fc5
synth_xilinx: Use opt_dff.
...
The main part is converting xilinx_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the patterns on its
own.
The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.
2020-07-30 22:26:09 +02:00
Dan Ravensloft
a2fb84fd0c
intel_alm: direct M10K instantiation
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This reverts commit a3a90f6377
.
2020-07-27 15:39:06 +02:00
Dan Ravensloft
62311b7ec0
intel_alm: increase abc9 -W
2020-07-26 23:56:54 +02:00
clairexen
02583ad504
Merge pull request #2294 from Ravenslofty/intel_alm_timings
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intel_alm: add additional ABC9 timings
2020-07-23 18:21:20 +02:00
Dan Ravensloft
4d9d90079c
intel_alm: add additional ABC9 timings
2020-07-23 11:57:07 +01:00
Keith Rothman
819f1d8c20
Remove EXPLICIT_CARRY logic.
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The symbiflow-arch-defs tool chain no longer needs the EXPLICIT_CARRY
within yosys itself.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2020-07-23 00:56:09 +02:00
Marcelina Kościelnicka
1b95b0e570
sf2: Emit CLKINT even if -clkbuf not passed
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This restores pre #2229 behavior.
2020-07-17 15:01:47 +02:00
Miodrag Milanović
10bc0967e2
Merge pull request #2274 from YosysHQ/mwk/anlogic-ff-fix
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anlogic: Fix FF mapping.
2020-07-17 14:39:31 +02:00
Marcelina Kościelnicka
a4f7777e9d
anlogic: Fix FF mapping.
2020-07-17 14:03:21 +02:00
clairexen
9a5d6e1789
Merge pull request #2229 from Ravenslofty/sf2_remove_sf2_iobs
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sf2: replace sf2_iobs with {clkbuf,iopad}map
2020-07-16 18:33:56 +02:00
Miodrag Milanović
910f421324
Merge pull request #2238 from YosysHQ/mwk/dfflegalize-anlogic
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anlogic: Use dfflegalize.
2020-07-16 18:07:58 +02:00
Miodrag Milanović
b74eb598bc
Merge pull request #2226 from YosysHQ/mwk/nuke-efinix-gbuf
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efinix: Nuke efinix_gbuf in favor of clkbufmap.
2020-07-16 18:07:41 +02:00
Marcelina Kościelnicka
a786091b46
achronix: Use dfflegalize.
2020-07-14 23:12:16 +02:00
Marcelina Kościelnicka
3050454d6e
anlogic: Use dfflegalize.
2020-07-14 05:02:50 +02:00
Marcelina Kościelnicka
3209c0762a
intel: Use dfflegalize.
2020-07-13 19:21:05 +02:00
Lofty
a3a90f6377
Revert "intel_alm: direct M10K instantiation"
...
This reverts commit 09ecb9b2cf
.
2020-07-13 18:05:38 +02:00
Marcelina Kościelnicka
347dd01c2f
xilinx: Fix srl regression.
...
Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and
$_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the
point where xilinx_srl is called for non-abc9. Fix this by running
ff_map.v first, resulting in FDRE cells, which are handled correctly.
2020-07-12 23:41:27 +02:00
Dan Ravensloft
7dc0439de4
sf2: replace sf2_iobs with {clkbuf,iopad}map
2020-07-09 21:28:52 +01:00
Marcelina Kościelnicka
edbaf2fdf6
sf2: Use dfflegalize.
2020-07-09 21:56:14 +02:00
Marcelina Kościelnicka
f313211c32
xilinx: Use dfflegalize.
2020-07-09 18:54:23 +02:00
Marcelina Kościelnicka
d5e5d96527
efinix: Use dfflegalize.
2020-07-06 12:28:17 +02:00
Marcelina Kościelnicka
c73ebeb90e
gowin: Use dfflegalize.
2020-07-06 12:27:46 +02:00
Dan Ravensloft
09ecb9b2cf
intel_alm: direct M10K instantiation
2020-07-05 23:28:59 +02:00
Dan Ravensloft
7f45cab27a
synth_gowin: ABC9 support
...
This adds ABC9 support for synth_gowin; drastically improving
synthesis quality.
2020-07-05 22:07:17 +02:00
Marcelina Kościelnicka
b5f3b70cfe
Merge pull request #2236 from YosysHQ/mwk/dfflegalize-ice40
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ice40: Use dfflegalize.
2020-07-05 18:50:25 +02:00
Marcelina Kościelnicka
372521ca56
ecp5: Use dfflegalize.
2020-07-05 18:49:41 +02:00
Marcelina Kościelnicka
90b89e5ebc
Merge pull request #2232 from YosysHQ/mwk/gowin-sim-init
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gowin: Fix INIT values in sim library.
2020-07-05 12:02:31 +02:00
Dan Ravensloft
b004f09018
intel_alm: DSP inference
2020-07-05 05:39:20 +02:00
Marcelina Kościelnicka
1fc8c3a0d1
ice40: Use dfflegalize.
2020-07-05 05:12:09 +02:00
Marcelina Kościelnicka
9beed4d771
gowin: Fix INIT values in sim library.
2020-07-05 03:03:48 +02:00
Dan Ravensloft
01772dec8c
gowin: replace determine_init with setundef
2020-07-04 23:26:56 +02:00
Marcelina Kościelnicka
3ca2de0f77
synth_intel_alm: Use dfflegalize.
2020-07-04 22:56:16 +02:00
Marcelina Kościelnicka
6b0ac04698
efinix: Nuke efinix_gbuf in favor of clkbufmap.
2020-07-04 20:53:43 +02:00
Dan Ravensloft
c6765443fd
Improve MISTRAL_FF specify rules
...
Co-authored-by: Eddie Hung <eddie@fpgeh.com>
2020-07-04 19:45:10 +02:00
Eddie Hung
2bdced0d68
intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FF
2020-07-04 19:45:10 +02:00
Eddie Hung
3db3e1e149
intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLY
2020-07-04 19:45:10 +02:00
Dan Ravensloft
83cde2d02b
intel_alm: ABC9 sequential optimisations
2020-07-04 19:45:10 +02:00
Marcelina Kościelnicka
817ae04ee0
simcells: Fix reset polarity for $_DLATCH_???_ cells.
2020-06-30 15:32:06 +02:00
Marcelina Kościelnicka
88e7f90663
Update dff2dffe, dff2dffs, zinit to new FF types.
2020-06-23 18:24:53 +02:00
Marcelina Kościelnicka
832acc8648
Add new FF types to simplemap.
2020-06-23 15:40:02 +02:00
Marcelina Kościelnicka
b0bee396a8
Add new builtin FF types
...
The new types include:
- FFs with async reset and enable (`$adffe`, `$_DFFE_[NP][NP][01][NP]_`)
- FFs with sync reset (`$sdff`, `$_SDFF_[NP][NP][01]_`)
- FFs with sync reset and enable, reset priority (`$sdffs`, `$_SDFFE_[NP][NP][01][NP]_`)
- FFs with sync reset and enable, enable priority (`$sdffce`, `$_SDFFCE_[NP][NP][01][NP]_`)
- FFs with async reset, set, and enable (`$dffsre`, `$_DFFSRE_[NP][NP][NP][NP]_`)
- latches with reset or set (`$adlatch`, `$_DLATCH_[NP][NP][01]_`)
The new FF types are not actually used anywhere yet (this is left
for future commits).
2020-06-23 15:40:02 +02:00
whitequark
7191dd16f9
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
Xark
9509444ef2
Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTH
2020-06-14 00:45:22 -07:00
Dan Ravensloft
8b4eb78849
intel_alm: fix DFFE matching
2020-06-11 19:55:51 +02:00
Claire Wolf
3c7122c378
Do not optimize away FFs in "prep" and Verific fron-end
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-06-09 15:54:14 +02:00
Eddie Hung
69850204c4
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve
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abc9: -dff improvements
2020-06-04 08:15:25 -07:00
Eddie Hung
d3b53bc495
abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_
2020-05-29 17:17:40 -07:00
Xiretza
edd8ff2c07
Add flooring division operator
...
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $divfloor cell provides this flooring division.
This commit also fixes the handling of $div in opt_expr, which was
previously optimized as if it was $divfloor.
2020-05-28 22:59:04 +02:00
Xiretza
17163cf43a
Add flooring modulo operator
...
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $modfloor cell provides this flooring modulo (also known as "remainder"
in several languages, but this name is ambiguous).
This commit also fixes the handling of $mod in opt_expr, which was
previously optimized as if it was $modfloor.
2020-05-28 22:59:03 +02:00
Eddie Hung
5b81df57c8
xilinx: tidy up cells_sim.v a little
2020-05-25 09:48:11 -07:00
Eddie Hung
76e0cc8276
ecp5: cleanup unused +/ecp5/abc9_model.v
2020-05-23 08:17:40 -07:00
Marcelina Kościelnicka
aee439360b
Add force_downto and force_upto wire attributes.
...
Fixes #2058 .
2020-05-19 01:42:40 +02:00
Eddie Hung
67fc0c3698
abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_
...
instead of moving them to $__ prefix
2020-05-14 16:44:35 -07:00
Eddie Hung
13f9d65b6f
abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it
2020-05-14 10:33:57 -07:00
Eddie Hung
97a0a04314
abc9_ops/xaiger: further reducing Module::derive() calls by ...
...
replacing _all_ (* abc9_box *) instantiations with their derived types
2020-05-14 10:33:57 -07:00
Eddie Hung
e79127fceb
Cleanup; reduce Module::derive() calls
2020-05-14 10:33:57 -07:00
Eddie Hung
cea614f5ae
ecp5: latches_map.v if *not* -asyncprld
2020-05-14 10:33:57 -07:00
Eddie Hung
fdc340db8e
ecp5: synth_ecp5 to no longer need +/ecp5/abc9_{,un}map.v
2020-05-14 10:33:57 -07:00
Eddie Hung
39759d5f0e
ecp5: fix rebase mistake
2020-05-14 10:33:57 -07:00
Eddie Hung
ca4f8c9444
xilinx: gate specify/attributes from iverilog
2020-05-14 10:33:57 -07:00
Eddie Hung
57c478c537
abc9: only do +/abc9_map if `DFF
2020-05-14 10:33:57 -07:00
Eddie Hung
8cda29137e
ecp5: TRELLIS_FF bypass path only in async mode
2020-05-14 10:33:56 -07:00
Eddie Hung
6c34945371
xilinx/ice40/ecp5: zinit requires selected wires, so select them all
2020-05-14 10:33:56 -07:00
Eddie Hung
a323881e15
xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cells
2020-05-14 10:33:56 -07:00
Eddie Hung
7cd3f4a79b
abc9_ops: add -prep_bypass for auto bypass boxes; refactor
...
Eliminate need for abc9_{,un}map.v in xilinx
-prep_dff_{hier,unmap} -> -prep_hier
2020-05-14 10:33:56 -07:00
Eddie Hung
722540dbf9
abc9: not enough to techmap_fail on (* init=1 *), hide them using $__
2020-05-14 10:33:56 -07:00
Eddie Hung
8fbb55f4ab
synth_*: no need to explicitly read +/abc9_model.v
2020-05-14 10:33:56 -07:00
Eddie Hung
48052ad813
abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too
2020-05-14 10:33:56 -07:00
Eddie Hung
4cec21b93e
abc9_ops: -prep_dff_map to error if async flop found
2020-05-14 10:33:56 -07:00
Eddie Hung
6c66030dfb
Uncomment negative setup times; clamp to zero for connectivity
2020-05-14 10:33:56 -07:00
Eddie Hung
0d84ff3fc4
Revert "ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init"
...
This reverts commit 8c702b6cc0221a00021a3e4661c883bb591c924b.
2020-05-14 10:33:56 -07:00
Eddie Hung
a52f779eca
ecp5: (* abc9_flop *) gated behind YOSYS
2020-05-14 10:33:56 -07:00
Eddie Hung
34c7732642
ecp5: add synth_ecp5 -dff to work with -abc9
2020-05-14 10:33:56 -07:00
Eddie Hung
23c53a6bdd
ice40: synth_ice40 cleanup
2020-05-14 10:33:56 -07:00
Eddie Hung
5d5029fa75
ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init
2020-05-14 10:33:56 -07:00
Eddie Hung
fe7965e0ee
ice40: add synth_ice40 -dff option, support with -abc9
2020-05-14 10:33:56 -07:00
Eddie Hung
4a10c87ae1
ice40: split out cells_map.v into ff_map.v
2020-05-14 10:33:56 -07:00
Eddie Hung
c10757a8ea
synth_xilinx: rename dff_mode -> dff
2020-05-14 10:33:56 -07:00
Eddie Hung
95763c8d18
abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxes
2020-05-14 10:33:56 -07:00
Claire Wolf
ee0beb481d
Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto
...
ast: swap range regardless of range_left >= 0
2020-05-14 18:06:18 +02:00
Eddie Hung
27b7ffc754
ice40: fix ICESTORM_LC process sensitivity
2020-05-12 15:40:48 -07:00
Eddie Hung
4ecae8a673
ice40: fix whitespace
2020-05-12 15:40:13 -07:00
David Shah
95fb3cf487
ecp5: Add missing SERDES parameters
...
Signed-off-by: David Shah <dave@ds0.me>
2020-05-12 21:12:26 +01:00
Dan Ravensloft
5b779f7f4e
intel_alm: direct LUTRAM cell instantiation
...
By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.
While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.
2020-05-07 21:03:13 +02:00
Eddie Hung
004999218f
techlibs/common: more robustness when *_WIDTH = 0
2020-05-05 08:01:27 -07:00
Eddie Hung
e6b55e8b38
synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpad
2020-05-04 11:44:00 -07:00
whitequark
26cda3c247
gowin,ecp5: remove generated files in `make clean`.
2020-04-24 23:26:39 +00:00
Dan Ravensloft
4ca5f9799b
intel_alm: cleanup duplication
2020-04-24 11:26:48 +02:00
Dan Ravensloft
3d149aff73
intel_alm: work around a Quartus ICE
2020-04-23 11:03:28 +02:00
Eddie Hung
51ae0f4e20
ecp5: ecp5_gsr to skip cells that don't have GSR parameter again
2020-04-22 17:53:08 -07:00
Eddie Hung
d2d90e4504
xilinx: improve xilinx_dffopt message
2020-04-22 16:25:23 -07:00
Eddie Hung
7f33a0294b
Cleanup use of hard-coded default parameters in light of #1945
2020-04-22 12:02:30 -07:00
Dan Ravensloft
16a3048308
intel_alm: Documentation improvements
2020-04-21 19:38:15 +02:00
Marcelina Kościelnicka
b4d76309e1
Use default parameter value in getParam
...
Fixes #1822 .
2020-04-21 19:09:00 +02:00
David Shah
1664bcda12
ecp5: Force SIGNED ports to be 1 bit
...
Signed-off-by: David Shah <dave@ds0.me>
2020-04-16 16:38:19 +01:00
Marcelina Kościelnicka
53ba3cf718
Fix the truth table for $_SR_* cells.
...
This brings the documented behavior for these cells in line with
$_DFFSR_* and $_DLATCHSR_*, which is that R has priority over S.
The models were already reflecting that behavior.
Also get rid of sim-synth mismatch in the models while we're at it.
2020-04-15 17:17:48 +02:00
Marcelina Kościelnicka
38a0c30d65
Get rid of dffsr2dff.
...
This pass is a proper subset of opt_rmdff, which is called by opt, which
is called by every synth flow in the coarse part. Thus, it never
actually does anything and can be safely removed.
2020-04-15 16:22:37 +02:00
Dan Ravensloft
43cc6bd8a1
synth_intel_alm: VQM support
2020-04-15 16:15:25 +02:00
Dan Ravensloft
2e37e62e6b
synth_intel_alm: alternative synthesis for Intel FPGAs
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By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.
This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2020-04-15 11:40:41 +02:00
whitequark
93ef516d91
Merge pull request #1603 from whitequark/ice40-ram_style
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ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
2020-04-10 14:51:01 +00:00
Eddie Hung
d61a6b81fc
Merge pull request #1648 from YosysHQ/eddie/cmp2lcu
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"techmap -map +/cmp2lcu.v" for decomposing arithmetic compares to $lcu
2020-04-03 16:28:25 -07:00
Eddie Hung
7b38cde2df
cmp2lcu: rename _90_lcu_cmp -> _80_lcu_cmp
2020-04-03 14:28:22 -07:00
Eddie Hung
7b09a20c0c
cmp2lcu: fail if `LUT_WIDTH < 2
2020-04-03 14:28:22 -07:00
Eddie Hung
34c9b83854
synth: only techmap cmp2{lut,lcu} if -lut
2020-04-03 14:28:22 -07:00
Eddie Hung
5b87720b16
synth: use +/cmp2lcu.v in generic 'synth' too
2020-04-03 14:28:22 -07:00
Eddie Hung
2bf03c6ae0
Cleanup +/cmp2lut.v
2020-04-03 14:28:22 -07:00
Eddie Hung
051aefc3c2
synth_xilinx: techmap +/cmp2lut.v and +/cmp2lcu.v in 'coarse'
2020-04-03 14:28:22 -07:00