Clifford Wolf
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978a933b6a
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Added RTLIL::SigSpec::to_sigbit_map()
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2014-08-14 23:14:47 +02:00 |
Clifford Wolf
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2f44d8ccf8
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Added sig.{replace,remove,extract} variants for std::{map,set} pattern
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2014-08-14 22:32:18 +02:00 |
Clifford Wolf
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1bf7a18fec
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Added module->ports
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2014-08-14 16:22:52 +02:00 |
Clifford Wolf
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746aac540b
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Refactoring of CellType class
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2014-08-14 15:46:51 +02:00 |
Clifford Wolf
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13f2f36884
|
RIP $safe_pmux
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2014-08-14 11:39:46 +02:00 |
Clifford Wolf
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523df73145
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Added support for truncating of wires to wreduce pass
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2014-08-05 14:47:03 +02:00 |
Clifford Wolf
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b6acbc82e6
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Bugfix in "techmap -extern"
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2014-08-02 20:54:30 +02:00 |
Clifford Wolf
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8e7361f128
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Removed at() method from RTLIL::IdString
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2014-08-02 19:08:02 +02:00 |
Clifford Wolf
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04727c7e0f
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No implicit conversion from IdString to anything else
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2014-08-02 18:58:40 +02:00 |
Clifford Wolf
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e590ffc84d
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Improvements in new RTLIL::IdString implementation
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2014-08-02 15:44:10 +02:00 |
Clifford Wolf
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60f3dc9923
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Implemented new reference counting RTLIL::IdString
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2014-08-02 15:11:35 +02:00 |
Clifford Wolf
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b9bd22b8c8
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More cleanups related to RTLIL::IdString usage
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2014-08-02 13:19:57 +02:00 |
Clifford Wolf
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d13eb7e099
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Added ModIndex helper class, some changes to RTLIL::Monitor
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2014-08-01 17:14:32 +02:00 |
Clifford Wolf
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97a17d39e2
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Packed SigBit::data and SigBit::offset in a union
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2014-08-01 15:25:42 +02:00 |
Clifford Wolf
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cdae8abe16
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Renamed port access function on RTLIL::Cell, added param access functions
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2014-07-31 16:38:54 +02:00 |
Clifford Wolf
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cd9407404a
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Added RTLIL::Monitor
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2014-07-31 14:45:14 +02:00 |
Clifford Wolf
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e6d33513a5
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Added module->design and cell->module, wire->module pointers
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2014-07-31 14:11:39 +02:00 |
Clifford Wolf
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1cb25c05b3
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Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
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2014-07-31 13:19:47 +02:00 |
Clifford Wolf
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03c96f9ce7
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Added "techmap -map %{design-name}"
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2014-07-29 16:35:13 +02:00 |
Clifford Wolf
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397b00252d
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Added $shift and $shiftx cell types (needed for correct part select behavior)
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2014-07-29 16:35:13 +02:00 |
Clifford Wolf
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3c45277ee0
|
Added wire->upto flag for signals such as "wire [0:7] x;"
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2014-07-28 12:12:13 +02:00 |
Clifford Wolf
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7bd2d1064f
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Using log_assert() instead of assert()
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2014-07-28 11:27:48 +02:00 |
Clifford Wolf
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d86a25f145
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Added std::initializer_list<> constructor to SigSpec
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2014-07-28 10:52:58 +02:00 |
Clifford Wolf
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f99495a895
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Added cover() to all SigSpec constructors
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2014-07-28 10:52:30 +02:00 |
Clifford Wolf
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c4bdba78cb
|
Added proper Design->addModule interface
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2014-07-27 21:12:09 +02:00 |
Clifford Wolf
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4be645860b
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Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs
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2014-07-27 14:47:48 +02:00 |
Clifford Wolf
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675cb93da9
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Added RTLIL::Module::wire(id) and cell(id) lookup functions
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2014-07-27 11:18:31 +02:00 |
Clifford Wolf
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10e5791c5e
|
Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-27 11:18:30 +02:00 |
Clifford Wolf
|
1c8fdaeef8
|
Added RTLIL::ObjIterator and RTLIL::ObjRange
|
2014-07-27 11:18:30 +02:00 |
Clifford Wolf
|
4c4b602156
|
Refactoring: Renamed RTLIL::Module::cells to cells_
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2014-07-27 01:51:45 +02:00 |
Clifford Wolf
|
f9946232ad
|
Refactoring: Renamed RTLIL::Module::wires to wires_
|
2014-07-27 01:49:51 +02:00 |
Clifford Wolf
|
d68c993ed2
|
Changed more code to the new RTLIL::Wire constructors
|
2014-07-26 21:30:38 +02:00 |
Clifford Wolf
|
946ddff9ce
|
Changed a lot of code to the new RTLIL::Wire constructors
|
2014-07-26 20:12:50 +02:00 |
Clifford Wolf
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97a59851a6
|
Added RTLIL::Cell::has(portname)
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2014-07-26 16:11:28 +02:00 |
Clifford Wolf
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f8fdc47d33
|
Manual fixes for new cell connections API
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2014-07-26 15:58:23 +02:00 |
Clifford Wolf
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b7dda72302
|
Changed users of cell->connections_ to the new API (sed command)
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
|
2014-07-26 15:58:23 +02:00 |
Clifford Wolf
|
cd6574ecf6
|
Added some missing "const" in rtlil.h
|
2014-07-26 15:58:22 +02:00 |
Clifford Wolf
|
7ac9dc7f6e
|
Added RTLIL::Module::connections()
|
2014-07-26 15:58:21 +02:00 |
Clifford Wolf
|
b03aec6e32
|
Added RTLIL::Module::connect(const RTLIL::SigSig&)
|
2014-07-26 14:31:47 +02:00 |
Clifford Wolf
|
3719281ed4
|
Automatically pack SigSpec on copy/assign
|
2014-07-26 13:59:30 +02:00 |
Clifford Wolf
|
e75e495c2b
|
Added new RTLIL::Cell port access methods
|
2014-07-26 12:22:58 +02:00 |
Clifford Wolf
|
cc4f10883b
|
Renamed RTLIL::{Module,Cell}::connections to connections_
|
2014-07-26 11:58:03 +02:00 |
Clifford Wolf
|
4755e14e7b
|
Added copy-constructor-like module->addCell(name, other) method
|
2014-07-26 00:38:44 +02:00 |
Clifford Wolf
|
2bec47a404
|
Use only module->addCell() and module->remove() to create and delete cells
|
2014-07-25 17:56:19 +02:00 |
Clifford Wolf
|
c762050e7f
|
Added RTLIL::SigSpec is_chunk()/as_chunk() API
|
2014-07-25 14:23:10 +02:00 |
Clifford Wolf
|
7f1789ad1b
|
Fixed typo in cover id
|
2014-07-25 03:41:53 +02:00 |
Clifford Wolf
|
6aa792c864
|
Replaced more old SigChunk programming patterns
|
2014-07-24 23:10:58 +02:00 |
Clifford Wolf
|
e589289df7
|
Some improvements in SigSpec packing/unpacking and checking
|
2014-07-24 15:05:41 +02:00 |
Clifford Wolf
|
22ede43b3f
|
Small changes regarding cover() and check() in SigSpec
|
2014-07-24 04:46:36 +02:00 |
Clifford Wolf
|
798f713629
|
Added support for YOSYS_COVER_FILE env variable
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2014-07-24 04:16:32 +02:00 |