riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
10,866 Commits 81 Branches 48 Tags 64 MiB
Commit Graph

1 Commits

Author SHA1 Message Date
Zachary Snow 4fadcc8f25 verilog: allow spaces in macro arguments 2021-01-20 08:49:58 -07:00